MJB42CT4G [ONSEMI]
Complementary Silicon Plastic Power Transistors; 互补硅塑料功率晶体管
| 型号： | MJB42CT4G |
| 厂家： | 
ONSEMI |
| 描述： | Complementary Silicon Plastic Power Transistors |
| 文件： | 总6页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MJB41C (NPN),
MJB42C (PNP)
Preferred Devices
Complementary Silicon
Plastic Power Transistors
D2PAK for Surface Mount
http://onsemi.com
Features
COMPLEMENTARY SILICON
POWER TRANSISTORS
6 AMPERES,
• Lead Formed for Surface Mount Applications in Plastic Sleeves
(No Suffix)
• Electrically the Same as TIP41 and T1P42 Series
• Pb−Free Packages are Available
100 VOLTS, 65 WATTS
MARKING
DIAGRAM
MAXIMUM RATINGS
Rating
Collector−Emitter Voltage
Collector−Base Voltage
Emitter−Base Voltage
Symbol
Value
100
Unit
Vdc
Vdc
Vdc
Adc
V
CEO
2
D PAK
V
100
CB
EB
J4xCG
AYWW
CASE 418B
STYLE 1
V
5.0
Collector Current − Continuous
− Peak
I
6.0
10
C
Base Current
I
2.0
Adc
B
J4xC = Specific Device Code
x = 1 or 2
Total Power Dissipation
P
D
@ T = 25_C
C
65
0.52
W
W/_C
A
Y
= Assembly Location
= Year
Derate above 25_C
WW = Work Week
= Pb−Free Package
Total Power Dissipation
P
D
G
@ T = 25_C
A
2.0
0.016
W
Derate above 25_C
W/_C
mJ
ORDERING INFORMATION
Unclamped Inductive Load Energy (Note 1)
E
62.5
†
Operating and Storage Junction
Temperature Range
T , T
−65 to +150
_C
J
stg
Device
MJB41C
MJB41CG
Package
Shipping
2
D PAK
50 Units/Rail
50 Units/Rail
THERMAL CHARACTERISTICS
Characteristic
2
D PAK
Symbol
Max
1.92
62.5
Unit
_C/W
_C/W
(Pb−Free)
Thermal Resistance, Junction−to−Case
R
q
JC
2
MJB41CT4
D PAK
800/Tape & Reel
800/Tape & Reel
Thermal Resistance,
Junction−to−Ambient
R
q
JA
JA
L
2
MJB41CT4G
D PAK
(Pb−Free)
Thermal Resistance,
R
q
50
_C/W
_C
2
MJB42C
D PAK
50 Units/Rail
50 Units/Rail
Junction−to−Ambient (Note 2)
2
MJB42CG
D PAK
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
T
260
(Pb−Free)
2
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
MJB42CT4
D PAK
800/Tape & Reel
800/Tape & Reel
2
MJB42CT4G
D PAK
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1. I = 2.5 A, L = 20 mH, P.R.F. = 10 Hz, V = 10 V, R = 100 W
C
CC
BE
2. When surface mounted to an FR−4 board using the minimum recommended
pad size.
Preferred devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
December, 2005 − Rev. 1
MJB41C/D
−
9.0 V
MJB41C (NPN),
ELECTRICAL CHARACTERISTICS (T = 25_C unless otherwise noted)
C
Characteristic
Symbol
Min
Max
Unit
OFF CHARACTERISTICS
Collector−Emitter Sustaining Voltage (Note 3) (I = 30 mAdc, I = 0)
V
CEO(sus)
100
−
−
Vdc
mAdc
mAdc
mAdc
C
B
Collector Cutoff Current (V = 60 Vdc, I = 0)
I
CEO
0.7
100
50
CE
B
Collector Cutoff Current (V = 100 Vdc, V = 0)
I
−
CE
EB
CES
EBO
Emitter Cutoff Current (V = 5.0 Vdc, I = 0)
I
−
BE
C
ON CHARACTERISTICS (Note 3)
DC Current Gain
(I = 0.3 Adc, V = 4.0 Vdc)
h
FE
30
15
−
75
−
C
CE
(I = 3.0 Adc, V = 4.0 Vdc)
C
CE
Collector−Emitter Saturation Voltage (I = 6.0 Adc, I = 600 mAdc)
V
CE(sat)
−
−
1.5
2.0
Vdc
Vdc
C
B
Base−Emitter On Voltage (I = 6.0 Adc, V = 4.0 Vdc)
V
BE(on)
C
CE
DYNAMIC CHARACTERISTICS
Current−Gain − Bandwidth Product (I = 500 mAdc, V = 10 Vdc, f
= 1.0 MHz)
f
T
3.0
20
−
−
MHz
−
C
CE
test
Small−Signal Current Gain (I = 0.5 Adc, V = 10 Vdc, f = 1.0 kHz)
h
fe
C
CE
3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2.0%.
T
A
T
C
4.0 80
3.0 60
2.0 40
1.0 20
T
C
T
A
0
0
0
20
40
60
100
120
140
160
80
T, TEMPERATURE (°C)
Figure 1. Power Derating
V
CC
+ꢂ30 V
2.0
T = 25°C
1.0
J
R
25 ms
V = 30 V
CC
I /I = 10
C
0.7
0.5
SCOPE
+11 V
0
C
B
R
B
0.3
0.2
t
r
D
1
t , t ≤ 10 ns
0.1
0.07
0.05
r
f
DUTY CYCLE = 1.0%
t @ V
d
≈ 5.0 V
−ꢂ4 V
BE(off)
R and R VARIED TO OBTAIN DESIRED CURRENT LEVELS
C
B
0.03
0.02
D MUST BE FAST RECOVERY TYPE, e.g.:
1
ꢃꢃ1N5825 USED ABOVE I ≈ 100 mA
0.06 0.1
0.2
0.4 0.6
1.0
2.0
4.0 6.0
B
ꢃꢃMSD6100 USED BELOW I ≈ 100 mA
B
I , COLLECTOR CURRENT (AMP)
C
Figure 2. Switching Time Test Circuit
Figure 3. Turn−On Time
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2
MJB41C (NPN),
1.0
0.7
0.5
D = 0.5
0.3
0.2
0.2
0.1
P
0.1
0.07
0.05
(pk)
Z
= r(t) R
q
JC
q
JC(t)
0.05
R
= 1.92°C/W MAX
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
0.02
0.01
t
1
0.03
0.02
t
1
2
T
− T = P
C
Z
q
(pk) JC(t)
J(pk)
DUTY CYCLE, D = t /t
1
2
SINGLE PULSE
0.05 1.0
0.01
0.01
0.02
0.2
0.5
1.0
2.0
5.0
10
20
50
100
200
500
1.0 k
t, TIME (ms)
Figure 4. Thermal Response
10
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
0.5ꢁms
5.0
breakdown. Safe operating area curves indicate I − V
C
CE
1.0ꢁms
3.0
2.0
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
SECONDARY BREAKDOWN LTD
BONDING WIRE LTD
5.0ꢁms
1.0
0.5
The data of Figure 5 is based on T
variable depending on conditions. Second breakdown pulse
= 150_C; T is
J(pk)
C
THERMAL LIMITATION @ T = 25°C
C
(SINGLE PULSE)
limits are valid for duty cycles to 10% provided T
J(pk)
CURVES APPLY BELOW RATED V
CEO
0.3
0.2
v 150_C.
T
may be calculated from the data in
J(pk)
Figure 4. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
0.1
5.0
10
20
40
60
80 100
V
, COLLECTOR−EMITTER VOLTAGE (VOLTS)
CE
Figure 5. Active−Region Safe Operating Area
5.0
300
T = 25°C
J
3.0
2.0
T = 25°C
J
200
V
I /I = 10
= 30 V
CC
C
B
t
s
I = I
B1 B2
1.0
C
C
ib
0.7
0.5
100
70
0.3
0.2
t
f
ob
50
0.1
0.07
0.05
30
0.06 0.1
0.2
0.4 0.6
1.0
2.0
4.0 6.0
0.5
1.0
2.0 3.0
5.0
10
20 30
50
I , COLLECTOR CURRENT (AMP)
C
V , REVERSE VOLTAGE (VOLTS)
R
Figure 6. Turn−Off Time
Figure 7. Capacitance
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3
−
.2
−0
.1
V
0
+ꢂ0.1 +ꢂ0.2 +ꢂ0.3 +ꢂ0.4 +ꢂ0.5 +ꢂ0.6 +ꢂ0.7
20
40
60
80
100
120
140
160
0.3 −
0
−55°C
MJB41C (NPN),
500
2.0
T = 25°C
300
200
J
V
= 2.0 V
CE
1.6
1.2
0.8
0.4
0
T = 150°C
J
100
70
25°C
I = 1.0 A
C
2.5 A
5.0 A
50
30
20
10
7.0
5.0
0.06 0.1
0.2 0.3 0.4 0.6
1.0
2.0
4.0 6.0
10
20 30
50
100
200 300 500
1000
I , COLLECTOR CURRENT (AMP)
C
I , BASE CURRENT (mA)
B
Figure 8. DC Current Gain
Figure 9. Collector Saturation Region
2.0
1.6
1.2
0.8
0.4
0
+ꢂ2.5
+ꢂ2.0
+ꢂ1.5
T = 25°C
J
*APPLIES FOR I /I ≤ h /4
C
B
FE
+ꢂ1.0
+ꢂ0.5
0
+ꢂ25 °C to +ꢂ150°C
*ꢂq FOR V
VC
CE(sat)
−ꢂ55°C to +ꢂ25°C
+ꢂ25 °C to +ꢂ150°C
V
V
@ I /I = 10
C B
BE(sat)
−ꢂ0.5
−ꢂ1.0
−ꢂ1.5
−ꢂ2.0
−ꢂ2.5
V
@ V = 4.0 V
CE
BE
q
FOR V
BE
VB
−ꢂ55°C to +ꢂ25°C
@ I /I = 10
C B
CE(sat)
0.06 0.1
0.2 0.3 0.4 0.6
1.0
2.0 3.0 4.0 6.0
0.06 0.1
0.2 0.3
0.5
1.0
2.0 3.0 4.0 6.0
I , COLLECTOR CURRENT (AMP)
C
I , COLLECTOR CURRENT (AMP)
C
Figure 10. “On” Voltages
Figure 11. Temperature Coefficients
3
2
1
0
10
10
10
10
10ꢁM
V
= 30 V
CE
V
= 30 V
CE
1.0ꢁM
100ꢁk
10ꢁk
I = 10 x I
C
CES
T = 150°C
J
100°C
I
C
≈ I
CES
25°C
I = I
C
−1
−2
CES
I = 2 x I
C
CES
10
10
10
1.0ꢁk
0.1ꢁk
REVERSE
FORWARD
(TYPICAL I VALUES
CES
OBTAINED FROM FIGURE 12)
−3
, BASE−EMITTER VOLTAGE (VOLTS)
T , JUNCTION TEMPERATURE (°C)
BE
J
Figure 12. Collector Cut−Off Region
Figure 13. Effects of Base−Emitter Resistance
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4
MJB41C (NPN),
PACKAGE DIMENSIONS
D2PAK 3
CASE 418B−04
ISSUE J
NOTES:
C
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
E
V
W
−B−
4
INCHES
DIM MIN MAX
MILLIMETERS
MIN
MAX
A
B
C
D
E
F
G
H
J
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
8.64
9.65 10.29
4.06
0.51
1.14
7.87
9.65
A
4.83
0.89
1.40
8.89
S
1
2
3
2.54 BSC
−T−
SEATING
PLANE
0.080
0.018 0.025
0.090 0.110
0.110
2.03
0.46
2.29
1.32
7.11
5.00 REF
2.00 REF
0.99 REF
2.79
0.64
2.79
1.83
8.13
K
W
J
K
L
G
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
M
N
P
R
S
V
H
D 3 PL
M
M
T B
0.13 (0.005)
0.575 0.625 14.60 15.88
0.045 0.055 1.14 1.40
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
VARIABLE
CONFIGURATION
ZONE
N
P
R
U
L
L
L
M
M
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
SOLDERING FOOTPRINT*
8.38
0.33
1.016
0.04
10.66
0.42
5.08
0.20
3.05
0.12
17.02
0.67
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MJB41C (NPN),
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your
local Sales Representative.
MJB41C/D
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