MC74LVX74M [ONSEMI]
LOW-VOLTAGE CMOS; 低电压CMOS
| 型号： | MC74LVX74M |
| 厂家： | 
ONSEMI |
| 描述： | LOW-VOLTAGE CMOS |
| 文件： | 总7页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The MC74LVX74 is an advanced high speed CMOS D–type flip–flop.
The inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
The signal level applied to the D input is transferred to O output during
the positive going transition of the Clock pulse.
LOW–VOLTAGE CMOS
Clear (CD) and Set (SD) are independent of the Clock (CP) and are
accomplished by setting the appropriate input Low.
• High Speed: f
= 145MHz (Typ) at V
= 3.3V
max
• Low Power Dissipation: I
CC
= 2µA (Max) at T = 25°C
CC
A
D SUFFIX
14–LEAD SOIC PACKAGE
CASE 751A–03
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Low Noise: V
= 0.5V (Max)
OLP
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
DT SUFFIX
14–LEAD TSSOP PACKAGE
CASE 948G–01
V
CD2
13
D2
12
CP2 SD2
O2
9
O2
8
CC
14
11
10
M SUFFIX
14–LEAD SOIC EIAJ PACKAGE
CASE 965–01
1
2
3
4
5
6
7
CD1
D1
CP1
SD1
O1
O1
GND
PIN NAMES
Figure 1. 14–Lead Pinout (Top View)
Pins
Function
CP1, CP2
D1, D2
Clock Pulse Inputs
Data Inputs
CD1, CD2
SD1, SD2
On, On
Direct Clear Inputs
Direct Set Inputs
Outputs
6/97
Motorola, Inc. 1997
REV 0
MC74LVX74
4
SD1
SD
CD
2
3
5
6
D1
D
O1
O1
Q
Q
CP1
CP
1
CD1
SD2
10
SD
CD
12
11
9
8
D2
D
O2
O2
Q
Q
CP2
CP
13
CD2
Figure 2. Logic Diagram
OUTPUTS
INPUTS
SDn
CDn
CPn
Dn
On
On
OPERATING MODE
L
H
H
L
X
X
X
X
H
L
L
H
Asynchronous Set
Asynchronous Clear
L
L
X
X
H
H
Undetermined
H
H
H
H
↑
↑
h
l
H
L
L
H
Load and Read Register
H
H
↑
X
NC
NC
Hold
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Low–to–High Clock Transition; L = Low Voltage Level; l = Low
Voltage Level One Setup Time Prior to the Low–to–High Clock Transition; NC = No Change; X = High or Low Voltage Level or Transitions
are Acceptable; ↑ = Low–to–High Transition; ↑ = Not a Low–to–High Transition; For I
Reasons DO NOT FLOAT Inputs
CC
MOTOROLA
2
MC74LVX74
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
V
V
DC Supply Voltage
DC Input Voltage
–0.5 to +7.0
–0.5 to +7.0
CC
V
in
V
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
–0.5 to V
+0.5
V
out
CC
I
I
I
I
–20
mA
mA
mA
mA
mW
C
IK
±20
±25
OK
out
CC
DC Supply Current, V
Power Dissipation
and GND Pins
±50
CC
P
D
180
T
stg
Storage Temperature
–65 to +150
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
3.6
Unit
V
V
CC
DC Supply Voltage
V
in
DC Input Voltage
5.5
V
V
out
DC Output Voltage
0
V
CC
V
T
Operating Temperature, All Package Types
Input Rise and Fall Time
–40
0
+85
100
C
A
∆t/∆V
ns/V
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = – 40 to 85°C
A
V
CC
V
Symbol
Parameter
Test Conditions
Unit
Min
Typ
Max
Min
Max
V
IH
High–Level Input Voltage
2.0
3.0
3.6
1.5
2.0
2.4
1.5
2.0
2.4
V
V
V
V
Low–Level Input Voltage
2.0
3.0
3.6
0.5
0.8
0.8
0.5
0.8
0.8
V
V
V
IL
High–Level Output Voltage
I
I
I
= –50µA
= –50µA
= –4mA
2.0
3.0
3.0
1.9
2.9
2.58
2.0
3.0
1.9
2.9
2.48
OH
OL
OH
OH
OH
(V = V or V
in IH
)
IL
Low–Level Output Voltage
I
I
I
= 50µA
= 50µA
= 4mA
2.0
3.0
3.0
0.0
0.0
0.1
0.1
0.36
0.1
0.1
0.44
OL
OL
OL
(V = V or V
in IH
)
IL
I
I
Input Leakage Current
V
= 5.5V or GND
3.6
3.6
±0.1
±1.0
µA
µA
in
in
in
Quiescent Supply Current
V
= V
or GND
2.0
20.0
CC
CC
3
MOTOROLA
MC74LVX74
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T = – 40 to 85°C
A
Symbol
Parameter
Test Conditions
Unit
Min
Typ
Max
Min
Max
t
t
,
Propagation Delay
CP to O or O
V
V
V
V
V
V
= 2.7V
C
C
= 15pF
= 50pF
7.3
9.8
15.0
18.5
1.0
1.0
18.5
22.0
ns
PLH
PHL
CC
CC
CC
CC
CC
CC
L
L
= 3.3 ± 0.3V
= 2.7V
C
C
= 15pF
= 50pF
5.7
8.2
9.7
13.2
1.0
1.0
11.5
15.0
L
L
t
t
,
Propagation Delay
SD or CD to O or O
C
C
= 15pF
= 50pF
8.4
10.9
15.6
19.1
1.0
1.0
18.5
22.0
ns
MHz
ns
PLH
PHL
L
L
= 3.3 ± 0.3V
= 2.7V
C
C
= 15pF
= 50pF
6.6
9.1
10.1
13.6
1.0
1.0
12.0
15.5
L
L
f
Maximum Clock Frequency
(50% Duty Cycle)
C
C
= 15pF
= 50pF
55
45
135
60
50
40
max
L
L
= 3.3 ± 0.3V
C
C
= 15pF
= 50pF
95
60
145
85
80
50
L
L
t
t
Output–to–Output Skew
(Note 1.)
V
CC
V
CC
= 2.7V
= 3.3 ±0.3V
C
C
= 50pF
= 50pF
1.5
1.5
1.5
1.5
OSHL
OSLH
L
L
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (t
guaranteed by design.
) or LOW–to–HIGH (t
OSHL
); parameter
OSLH
TIMING REQUIREMENTS (Input t = t = 3.0ns)
r
f
Guaranteed Limit
V
CC
V
T
A
= – 40 to
85 C
Symbol
Parameter
Unit
T
A
= 25 C
t
t
t
t
t
Minimum Pulse Width, CP
2.7V
3.3V ±0.3
8.5
6.0
10.0
7.0
ns
w
Minimum Pulse Width, CD or SD
Minimum Setup Time, D to CP
2.7V
3.3V ±0.3
8.5
6.0
10.0
7.0
ns
ns
ns
ns
w
2.7V
3.3V ±0.3
8.0
5.5
9.5
6.5
su
h
Minimum Hold Time, D to CP
2.7V
3.3V ±0.3
0.5
0.5
0.5
0.5
Minimum Recovery Time, SD or CD to CP
2.7V
3.3V ±0.3
6.5
5.0
7.5
5.0
rec
CAPACITIVE CHARACTERISTICS
Symbol
T
A
= 25°C
Typ
4
T = – 40 to 85°C
A
Parameter
Unit
pF
Min
Max
Min
Max
C
C
Input Capacitance
Power Dissipation Capacitance (Note 2.)
10
10
in
25
pF
PD
2. C
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
= C
V
f
+ I
/2 (per flip–flop). C
is used to determine the
CC(OPR)
PD
CC in CC
PD
2
no–load dynamic power consumption; P = C
V
f
+ I
in CC
V
.
D
PD
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V
= 3.3V, Measured in SOIC Package)
r
f
L
CC
T
A
= 25°C
Symbol
Characteristic
Unit
V
Typ
Max
0.5
V
OLP
Quiet Output Maximum Dynamic V
0.3
OL
V
Quiet Output Minimum Dynamic V
–0.3
–0.5
2.0
V
OLV
OL
V
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
IHD
V
0.8
V
ILD
MOTOROLA
4
MC74LVX74
SWITCHING WAVEFORMS
t
w
V
CC
50%
SD or CD
GND
t
PHL
V
CC
CP
50%
50% V
O or O
CC
GND
t
w
t
PLH
1/f
max
50% V
CC
t
t
PHL
O or O
CP
PLH
t
rec
50% V
CC
V
O or O
CC
50%
GND
Figure 3.
Figure 4.
VALID
V
CC
50%
D
GND
t
t
h
su
V
CC
50%
CP
GND
Figure 5.
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
* Includes all probe and jig capacitance
Figure 6.
5
MOTOROLA
MC74LVX74
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–A
–
14
1
8
7
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B
–
P 7 PL
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
M
M
0.25 (0.010)
B
MILLIMETERS
INCHES
G
F
R X 45°
DIM
A
B
C
D
F
G
J
MIN
8.55
3.80
1.35
0.35
0.40
MAX
8.75
4.00
1.75
0.49
1.25
MIN
MAX
0.344
0.157
0.068
0.019
0.049
C
0.337
0.150
0.054
0.014
0.016
J
M
SEATING
PLANE
K
D 14 PL
1.27 BSC
0.050 BSC
0.19
0.10
0.25
0.25
0.008
0.004
0.009
0.009
M
S
S
0.25 (0.010)
T
B
A
K
M
P
R
0
5.80
0.25
°
7
6.20
0.50
°
0
°
7°
0.244
0.019
0.228
0.010
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 965–01
ISSUE O
NOTES:
1
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2
3
CONTROLLING DIMENSION: MILLIMETER.
DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
E
14
8
7
Q
1
E H
4
5
TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
M
THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
A
DIM
A
MIN
---
MAX
2.05
0.20
0.50
0.27
10.50
5.45
MIN
---
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
0.05
0.35
0.18
9.90
5.10
0.002
0.014
0.007
0.390
0.201
1
b
c
D
E
e
b
A
1
M
1.27 BSC
0.050 BSC
0.13 (0.005)
0.10 (0.004)
H
7.40
0.50
1.10
0
8.20
0.85
1.50
10
0.291
0.020
0.043
0
0.323
0.033
0.059
10
E
L
L
M
E
Q
Z
0.70
---
0.90
1.42
0.028
---
0.035
0.056
1
MOTOROLA
6
MC74LVX74
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
NOTES:
14X K REF
0.10 (0.004)
1
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
T
U
V
2
3
CONTROLLING DIMENSION: MILLIMETER.
DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
4
5
DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
8
7
2X L/2
M
B
L
N
–U–
PIN 1
IDENT.
F
1
6
7
TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
DETAIL E
S
K
0.15 (0.006) T
U
A
MILLIMETERS
INCHES
K1
DIM
A
B
C
D
F
G
H
J
J1
K
MIN
4.90
4.30
–––
0.05
0.50
MAX
5.10
4.50
1.20
0.15
0.75
MIN
MAX
0.200
0.177
0.047
0.006
0.030
–V–
0.193
0.169
–––
0.002
0.020
J J1
SECTION N–N
0.65 BSC
0.026 BSC
0.50
0.09
0.09
0.19
0.19
0.60
0.20
0.16
0.30
0.25
0.020
0.004
0.004
0.007
0.007
0.024
0.008
0.006
0.012
0.010
–W–
C
K1
L
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
SEATING
PLANE
–T–
H
G
DETAIL E
D
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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MC74LVX74/D
◊
相关型号：
MC74LVX74MR2
LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, EIAJ, SO-14
ONSEMI
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