MC74LVX8051DT [ONSEMI]
Analog Multiplexer/Demultiplexer; 模拟复用器/解复用器
| 型号： | MC74LVX8051DT |
| 厂家： | 
ONSEMI |
| 描述： | Analog Multiplexer/Demultiplexer |
| 文件： | 总12页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High–Performance Silicon–Gate CMOS
The MC74LVX8051 utilizes silicon–gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
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(from V
to GND).
CC
The LVX8051 is similar in pinout to the high–speed HC4051A and
the metal–gate MC14051B. The Channel–Select inputs determine
which one of the Analog Inputs/Outputs is to be connected, by means
of an analog switch, to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
16–LEAD SOIC
D SUFFIX
CASE 751B
16–LEAD TSSOP
DT SUFFIX
CASE 948F
The Channel–Select and Enable inputs are compatible with standard
CMOS outputs; with pull–up resistors they are compatible with
LSTTL outputs.
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
V
X2
15
X1
14
X0
13
X3
12
A
B
C
9
CC
This device has been designed so that the ON resistance (R ) is
on
16
11
10
more linear over input voltage than R of metal–gate CMOS analog
on
switches.
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
1
2
3
4
5
6
7
8
• Diode Protection on All Inputs/Outputs
X4
X6
X
X7
X5 Enable NC GND
• Analog Power Supply Range (V
– GND) = 2.0 to 6.0 V
CC
For detailed package marking information, see the Marking
Diagram section on page 11 of this data sheet.
• Digital (Control) Power Supply Range (V
CC
– GND) = 2.0 to 6.0 V
• Improved Linearity and Lower ON Resistance Than Metal–Gate
Counterparts
• Low Noise
ORDERING INFORMATION
• In Compliance With the Requirements of JEDEC Standard No. 7A
• Chip Complexity: LVX8051 — 184 FETs or 46 Equivalent Gates
Device
Package
SOIC
Shipping
48 Units/Rail
96 Units/Rail
MC74LVX8051D
MC74LVX8051DT
LOGIC DIAGRAM
MC74LVX8051
TSSOP
Single–Pole, 8–Position Plus Common Off
13
X0
14
X1
15
FUNCTION TABLE – MC74LVX8051
3
X2
X3
X4
X5
X6
X7
A
COMMON
OUTPUT/
INPUT
X
ANALOG
INPUTS/
12
1
MULTIPLEXER/
DEMULTIPLEXER
Control Inputs
OUTPUTS
Select
5
Enable
C
B
A
ON Channels
2
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
X0
X1
X2
X3
X4
X5
X6
X7
NONE
4
11
10
9
CHANNEL
SELECT
INPUTS
L
B
H
H
H
H
X
C
L
6
ENABLE
H
H
X
PIN 16 = V
CC
PIN 8 = GND
X = Don’t Care
Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
October, 1999 – Rev. 1.0
MC74LVX8051/D
MC74LVX8051
MAXIMUM RATINGS*
Symbol
Parameter
(Referenced to GND)
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
CC
Positive DC Supply Voltage
– 0.5 to + 7.0
V
IS
Analog Input Voltage
– 0.5 to V
+ 0.5
V
CC
V
Digital Input Voltage (Referenced to GND)
DC Current, Into or Out of Any Pin
– 0.5 to V
+ 0.5
V
in
CC
I
± 20
mA
mW
cuit. For proper operation, V and
in
P
D
Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
500
450
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
in out
Unused inputs must always be
tied to an appropriate logic voltage
T
Storage Temperature Range
– 65 to + 150
260
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
level (e.g., either GND or V
).
CC
Unused outputs must be left open.
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Positive DC Supply Voltage
Analog Input Voltage
Min
2.0
Max
Unit
V
V
CC
(Referenced to GND)
6.0
V
IS
0.0
V
V
V
CC
V
in
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature Range, All Package Types
GND
V
CC
V
IO
*
1.2
V
T
A
– 55
+ 85
C
t , t
r f
Input Rise/Fall Time
(Channel Select or Enable Inputs)
ns/V
V
CC
V
CC
= 3.3 V ± 0.3 V
= 5.0 V ± 0.5 V
0
0
100
20
*For voltage drops across switch greater than 1.2 V (switch on), excessive V
be drawn; i.e., the current out of the switch may contain both V
CC
current may
and switch input
CC
components. The reliability of the device will be unaffected unless the Maximum Ratings are
exceeded.
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2
MC74LVX8051
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND)
Guaranteed Limit
V
CC
V
Symbol
Parameter
Condition
= Per Spec
Unit
–55 to 25°C ≤85°C ≤125°C
V
IH
Minimum High–Level Input
Voltage, Channel–Select or
Enable Inputs
R
R
2.0
3.0
4.5
5.5
1.50
2.10
3.15
3.85
1.50
2.10
3.15
3.85
1.50
2.10
3.15
3.85
V
on
on
V
IL
Maximum Low–Level Input
Voltage, Channel–Select or
Enable Inputs
= Per Spec
2.0
3.0
4.5
5.5
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
V
I
Maximum Input Leakage Current,
Channel–Select or Enable Inputs
V
= V
or GND
CC
5.5
± 0.1
± 1.0
± 1.0
µA
µA
in
in
I
Maximum Quiescent Supply
Current (per Package)
Channel Select, Enable and
5.5
4.0
40
160
CC
V
V
= V
CC
= 0 V
or GND;
IS
IO
DC ELECTRICAL CHARACTERISTICS Analog Section
Guaranteed Limit
85 C
V
CC
V
– 55 to
25 C
Symbol
Parameter
Test Conditions
Unit
125 C
R
Maximum “ON” Resistance
Ω
V
V
|I |
S
= V or V
IL
3.0
4.5
5.5
30
25
20
35
28
25
40
35
30
on
in
IS
IH
= V
to GND
CC
10.0 mA (Figures 1, 2)
V
V
|I |
S
= V or V
IL
3.0
4.5
5.5
30
25
20
35
28
25
40
35
30
in
IS
IH
= V
or GND (Endpoints)
CC
10.0 mA (Figures 1, 2)
∆R
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
V
V
|I |
S
= V or V
IH
3.0
4.5
5.5
15
8.0
8.0
20
12
12
25
15
15
Ω
on
in
IS
IL
= 1/2 (V
– GND)
CC
10.0 mA
I
Maximum Off–Channel Leakage
Current, Any One Channel
V
V
= V or V
IL IH
;
5.5
5.5
5.5
0.1
0.2
0.2
0.5
2.0
2.0
1.0
4.0
4.0
µA
off
in
= V
or GND;
IO
CC
Switch Off (Figure 3)
Maximum Off–Channel
Leakage Current,
Common Channel
V
V
= V or V ;
IL
in
IO
IH
or GND;
CC
= V
Switch Off (Figure 4)
I
on
Maximum On–Channel
Leakage Current,
Channel–to–Channel
V
in
= V or V ;
IL IH
µA
Switch–to–Switch =
V or GND; (Figure 5)
CC
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3
MC74LVX8051
AC CHARACTERISTICS (C = 50 pF, Input t = t = 3 ns)
L
r
f
Guaranteed Limit
V
CC
V
Symbol
Parameter
Unit
–55 to 25°C
≤85°C
≤125°C
t
t
t
,
Maximum Propagation Delay, Channel–Select to Analog Output
(Figure 9)
2.0
3.0
4.5
5.5
30
20
15
15
35
25
18
18
40
30
22
20
ns
PLH
t
PHL
,
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
2.0
3.0
4.5
5.5
4.0
3.0
1.0
1.0
6.0
5.0
2.0
2.0
8.0
6.0
2.0
2.0
ns
ns
ns
PLH
t
PHL
,
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
3.0
4.5
5.5
30
20
15
15
35
25
18
18
40
30
22
20
PLZ
t
PHZ
t
t
,
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
3.0
4.5
5.5
20
12
8.0
8.0
25
14
10
10
30
15
12
12
PZL
PZH
C
Maximum Input Capacitance, Channel–Select or Enable Inputs
10
35
10
35
10
35
pF
pF
in
C
Maximum Capacitance
(All Switches Off)
Analog I/O
Common O/I
Feedthrough
I/O
130
1.0
130
1.0
130
1.0
C
pF
PD
Typical @ 25°C, V
= 5.0 V
CC
Power Dissipation Capacitance (Figure 13)*
45
2
* Used to determine the no–load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
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4
MC74LVX8051
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Limit*
V
CC
V
Symbol
Parameter
Condition
= 1MHz Sine Wave; Adjust f Voltage to Obtain
Unit
25°C
BW
Maximum On–Channel Bandwidth
or Minimum Frequency Response
(Figure 6)
f
MHz
in
in
0dBm at V ; Increase f Frequency Until dB
OS
in
3.0
4.5
5.5
80
80
80
Meter Reads –3dB;
R
= 50Ω, C = 10pF
L
L
—
—
Off–Channel Feedthrough Isolation
(Figure 7)
f
= Sine Wave; Adjust f Voltage to Obtain 0dBm
in
3.0
4.5
5.5
–50
–50
–50
dB
in
at V
IS
f
in
= 10kHz, R = 600Ω, C = 50pF
L L
3.0
4.5
5.5
–37
–37
–37
f
in
= 1.0MHz, R = 50Ω, C = 10pF
L L
Feedthrough Noise.
Channel–Select Input to Common
I/O (Figure 8)
V
≤ 1MHz Square Wave (t = t = 6ns); Adjust R
3.0
4.5
5.5
25
105
135
mV
PP
in
r
f
L
at Setup so that I = 0A;
S
Enable = GND
R = 600Ω, C = 50pF
L L
3.0
4.5
5.5
35
145
190
R
= 10kΩ, C = 10pF
L
L
THD
Total Harmonic Distortion
(Figure 14)
f
= 1kHz, R = 10kΩ, C = 50pF
%
in
THD = THD
L
L
– THD
measured
source
V
IS
V
IS
V
IS
= 2.0V
= 4.0V
= 5.0V
sine wave
sine wave
sine wave
3.0
4.5
5.5
0.10
0.08
0.05
PP
PP
PP
*Limits not tested. Determined by design and verified by qualification.
25
20
15
10
5
125°C
85°C
25°C
–55°C
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V , INPUT VOLTAGE (VOLTS)
IN
Figure 1a. Typical On Resistance, V
= 3.0 V
CC
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MC74LVX8051
20
18
18
125°C
85°C
16
14
12
10
8
125°C
85°C
16
14
12
10
8
25°C
25°C
–55°C
–55°C
6
6
4
4
2
0
2
0
0
1.0
2.0
3.0
4.0
5.0
0
1.0
2.0
3.0
4.0
5.0
6.0
V , INPUT VOLTAGE (VOLTS)
IN
V , INPUT VOLTAGE (VOLTS)
IN
Figure 1b. Typical On Resistance, V
= 4.5 V
Figure 1c. Typical On Resistance, V
= 5.5 V
CC
CC
PLOTTER
PROGRAMMABLE
POWER
MINI COMPUTER
DC ANALYZER
SUPPLY
–
+
V
CC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
GND
GND
Figure 2. On Resistance Test Set–Up
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MC74LVX8051
V
CC
V
CC
V
V
CC
CC
16
16
GND
GND
ANALOG I/O
OFF
OFF
OFF
OFF
A
V
V
CC
V
CC
COMMON O/I
NC
COMMON O/I
V
6
8
6
8
IH
IH
Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set–Up
Figure 4. Maximum Off Channel Leakage Current,
Common Channel, Test Set–Up
V
CC
16
V
OS
V
CC
V
CC
16
0.1µF
A
dB
METER
f
in
ON
ON
N/C
R
L
GND
C *
L
COMMON O/I
OFF
V
CC
ANALOG I/O
V
IL
6
8
6
8
*Includes all probe and jig capacitance
Figure 5. Maximum On Channel Leakage Current,
Channel to Channel, Test Set–Up
Figure 6. Maximum On Channel Bandwidth,
Test Set–Up
V
CC
16
V
CC
16
V
IS
V
OS
0.1µF
dB
METER
R
L
f
in
OFF
ON/OFF
OFF/ON
COMMON O/I
TEST
ANALOG I/O
R
L
R
L
C *
L
POINT
R
L
C *
L
R
L
6
8
6
8
V
CC
V ≤ 1 MHz
in
11
t = t = 3 ns
r
f
V
CC
GND
CHANNEL SELECT
*Includes all probe and jig capacitance
CHANNEL SELECT
*Includes all probe and jig capacitance
V
IL
or V
IH
Figure 7. Off Channel Feedthrough Isolation,
Test Set–Up
Figure 8. Feedthrough Noise, Channel Select to
Common Out, Test Set–Up
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MC74LVX8051
V
CC
16
V
CC
V
CC
ON/OFF
OFF/ON
COMMON O/I
C *
CHANNEL
SELECT
TEST
POINT
50%
ANALOG I/O
GND
L
t
t
PHL
PLH
6
8
ANALOG
OUT
50%
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 9a. Propagation Delays, Channel Select
to Analog Out
Figure 9b. Propagation Delay, Test Set–Up Channel
Select to Analog Out
V
CC
16
COMMON O/I
C *
ANALOG I/O
TEST
POINT
V
CC
ON
ANALOG
IN
50%
L
GND
t
t
PHL
PLH
6
8
ANALOG
OUT
50%
*Includes all probe and jig capacitance
Figure 10a. Propagation Delays, Analog In
to Analog Out
Figure 10b. Propagation Delay, Test Set–Up
Analog In to Analog Out
t
t
POSITION 1 WHEN TESTING t
POSITION 2 WHEN TESTING t
AND t
AND t
f
r
PHZ
PLZ
PZH
PZL
1
2
V
CC
90%
50%
10%
ENABLE
V
CC
16
GND
1kΩ
V
CC
t
t
PZL PLZ
HIGH
IMPEDANCE
1
2
ANALOG I/O
ENABLE
TEST
POINT
ON/OFF
ANALOG
OUT
50%
C *
L
10%
V
OL
t
t
PZH PHZ
6
8
V
OH
90%
ANALOG
OUT
50%
HIGH
IMPEDANCE
Figure 11a. Propagation Delays, Enable to
Analog Out
Figure 11b. Propagation Delay, Test Set–Up
Enable to Analog Out
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MC74LVX8051
V
CC
V
IS
A
V
CC
16
16
R
L
V
OS
ON/OFF
OFF/ON
COMMON O/I
f
in
ON
NC
ANALOG I/O
0.1µF
OFF
R
L
R
L
C *
L
C *
L
V
CC
R
L
6
8
6
8
11
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 12. Crosstalk Between Any Two
Switches, Test Set–Up
Figure 13. Power Dissipation Capacitance,
Test Set–Up
0
–10
–20
–30
–40
V
IS
FUNDAMENTAL FREQUENCY
V
CC
16
V
OS
0.1µF
TO
f
in
DISTORTION
METER
ON
R
L
C *
L
–50
–60
–70
–80
–90
–100
DEVICE
SOURCE
6
8
*Includes all probe and jig capacitance
1.0
2.0
3.125
FREQUENCY (kHz)
Figure 14a. Total Harmonic Distortion, Test Set–Up
Figure 14b. Plot, Harmonic Distortion
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at connected). However, tying unused analog inputs and
V
CC
or GND logic levels. V being recognized as a logic outputs to V or GND through a low value resistor helps
CC CC
high and GND being recognized as a logic low. In this
example:
minimize crosstalk and feedthrough noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
V
= +5V = logic high
CC
GND = 0V = logic low
The maximum analog voltage swing is determined by the
supply voltage V . The positive peak analog voltage
should not exceed V . Similarly, the negative peak analog
CC
voltage should not go below GND. In this example, the
V
CC
– GND = 2 to 6 volts
CC
When voltage transients above V
and/or below GND
CC
are anticipated on the analog channels, external Germanium
difference between V
and GND is five volts. Therefore,
or Schottky diodes (D ) are recommended as shown in
CC
x
using the configuration of Figure 15, a maximum analog
signal of five volts peak–to–peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
Figure 16. These diodes should be able to absorb the
maximum anticipated current surges during clipping.
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MC74LVX8051
V
V
CC
CC
+5V
V
CC
16
ON/OFF
D
D
x
16
x
+5V
0V
+5V
0V
ANALOG
SIGNAL
ANALOG
SIGNAL
ON
D
D
x
x
GND
GND
TO EXTERNAL CMOS
CIRCUITRY 0 to 5V
DIGITAL SIGNALS
6
8
11
10
9
8
Figure 15. Application Example
Figure 16. External Germanium or
Schottky Clipping Diodes
+5V
16
+5V
16
+5V
+5V
+5V
+5V
ANALOG
SIGNAL
ANALOG
ANALOG
SIGNAL
ANALOG
ON/OFF
ON/OFF
SIGNAL
SIGNAL
GND
GND
GND
GND
+5V
*
R
R
R
+5V
6
8
11
10
9
6
8
11
10
9
LSTTL/NMOS
CIRCUITRY
LSTTL/NMOS
CIRCUITRY
* 2K ≤ R ≤ 10K
VHCT1GT50
BUFFERS
a. Using Pull–Up Resistors
b. Using HCT Interface
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs
11
10
9
13
X0
LEVEL
SHIFTER
A
B
C
14
X1
15
X2
LEVEL
SHIFTER
12
X3
1
LEVEL
SHIFTER
X4
5
X5
6
2
LEVEL
SHIFTER
ENABLE
X6
4
X7
3
X
Figure 18. Function Diagram, LVX8051
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MC74LVX8051
MARKING DIAGRAMS
(Top View)
16 15 14 13 12 11 10
9
8
16
15
14
13
12
11
6
10
9
8
LVX
LVX8051
8051
AWLYWW*
ALYW*
1
2
3
4
5
7
1
2
3
4
5
6
7
16–LEAD SOIC
D SUFFIX
16–LEAD TSSOP
DT SUFFIX
CASE 751B
CASE 948F
*See Applications Note #AND8004/D for date code and traceability information.
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B
–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
MIN MAX
DIM MIN
MAX
A
B
C
D
F
G
J
K
M
P
9.80 10.00
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
F
K
R X 45°
3.80
1.35
0.35
0.40
4.00
1.75
0.49
1.25
C
1.27 BSC
–T
0.19
0.10
0°
0.25
0.25
7°
0.008 0.009
0.004 0.009
J
SEAT–ING
M
PLANE
D 16 PL
0°
7°
5.80
0.25
6.20
0.50
0.229 0.244
0.010 0.019
M
S
S
0.25 (0.010)
T
B
A
R
http://onsemi.com
11
MC74LVX8051
PACKAGE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X KREF
M
S
S
0.10 (0.004)
T U
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
S
0.15 (0.006) T U
K
Y14.5M, 1982.
K1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
16
9
2X L/2
J1
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
B
–U–
SECTION N–N
L
0.25 (0.010) PER SIDE.
J
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
PIN 1
IDENT.
8
1
N
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
S
0.15 (0.006) T U
A
M
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
–V–
N
A
B
C
D
F
G
H
J
J1
K
K1
L
4.90
4.30
–––
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
F
1.20
––– 0.047
0.15 0.002 0.006
0.75 0.020 0.030
0.026 BSC
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
DETAIL E
0.65 BSC
0.18
0.09
0.09
0.19
0.19
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
DETAIL E
H
SEATING
PLANE
–T–
D
G
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