MC74LVX8051DTR2 [ONSEMI]
Analog Multiplexer / Demultiplexer High−Performance Silicon−Gate CMOS; 模拟多路复用器/多路解复用器高性能硅栅CMOS
| 型号： | MC74LVX8051DTR2 |
| 厂家： | 
ONSEMI |
| 描述： | Analog Multiplexer / Demultiplexer High−Performance Silicon−Gate CMOS |
| 文件： | 总12页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LVX8051
Analog Multiplexer /
Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74LVX8051 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
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MARKING
DIAGRAMS
(from V to GND).
CC
The LVX8051 is similar in pinout to the high−speed HC4051A and
the metal−gate MC14051B. The Channel−Select inputs determine
which one of the Analog Inputs/Outputs is to be connected, by means
of an analog switch, to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
CMOS outputs; with pull−up resistors they are compatible with
LSTTL outputs.
16
SOIC−16
D SUFFIX
CASE 751B
LVX8051
AWLYWW
1
16
LVX
8051
ALYW
TSSOP−16
DT SUFFIX
CASE 948F
This device has been designed so that the ON resistance (R ) is
on
more linear over input voltage than R of metal−gate CMOS analog
on
switches.
1
Features
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
16
1
SOEIAJ−16
M SUFFIX
CASE 966
LVX8051
ALYW
• Analog Power Supply Range (V − GND) = 2.5 to 6.0 V
CC
• Digital (Control) Power Supply Range (V − GND) = 2.5 to 6.0 V
CC
• Improved Linearity and Lower ON Resistance Than Metal−Gate
A
=
=
=
=
Assembly Location
Wafer Lot
Year
Counterparts
WL or L
Y
WW or W
• Low Noise
Work Week
• In Compliance With the Requirements of JEDEC Standard No. 7A
• Chip Complexity: LVX8051 − 184 FETs or 46 Equivalent Gates
• Pb−Free Packages are Available*
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
April, 2005 − Rev. 4
MC74LVX8051/D
MC74LVX8051
V
X2
15
X1
14
X0
13
X3
12
A
B
C
9
CC
16
11
10
13
14
15
12
1
X0
X1
X2
X3
X4
X5
X6
X7
A
3
COMMON
OUTPUT/
INPUT
X
1
2
3
4
5
6
7
ANALOG
INPUTS/
OUTPUTS
8
MULTIPLEXER/
DEMULTIPLEXER
X4
X6
X
X7
X5 Enable NC GND
5
PIN CONNECTION AND
2
MARKING DIAGRAM (Top View)
4
11
10
9
FUNCTION TABLE − MC74LVX8051
CHANNEL
SELECT
INPUTS
B
Control Inputs
C
6
Select
B
ENABLE
Enable
C
A
ON Channels
PIN 16 = V
CC
PIN 8 = GND
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
X0
X1
X2
X3
X4
X5
X6
X7
NONE
LOGIC DIAGRAM
MC74LVX8051
Single−Pole, 8−Position Plus Common Off
L
H
H
H
H
X
L
H
H
X
X = Don’t Care
ORDERING INFORMATION
Device
†
Package
Shipping
MC74LVX8051DR2
MC74LVX8051DR2G
SOIC−16
2500 Tape & Reel
SOIC−16
(Pb−Free)
MC74LVX8051DT
MC74LVX8051DTR2
MC74LVX8051M
TSSOP−16*
TSSOP−16*
SOEIAJ−16
96 Units / Rail
2500 Tape & Reel
50 Units / Rail
MC74LVX8051MG
SOEIAJ−16
(Pb−Free)
MC74LVX8051MEL
MC74LVX8051MELG
SOEIAJ−16
2000 Tape & Reel
SOEIAJ−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74LVX8051
MAXIMUM RATINGS
Symbol
Parameter
(Referenced to GND)
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
CC
Positive DC Supply Voltage
– 0.5 to + 7.0
V
IS
Analog Input Voltage
− 0.5 to V + 0.5
V
CC
V
Digital Input Voltage (Referenced to GND)
DC Current, Into or Out of Any Pin
– 0.5 to V + 0.5
V
in
CC
I
± 20
mA
mW
cuit. For proper operation, V and
in
P
D
Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
500
450
V
out
should be constrained to the
range GND v (V or V ) v V
.
in
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
T
stg
Storage Temperature Range
– 65 to + 150
260
_C
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are not
valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating − SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Positive DC Supply Voltage (Referenced to GND)
Analog Input Voltage
Min
2.5
Max
Unit
V
V
CC
6.0
V
IS
0.0
V
CC
V
CC
V
V
in
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature Range, All Package Types
GND
V
V *
IO
1.2
V
T
A
– 55
+ 85
_C
ns/V
t , t
Input Rise/Fall Time
r
f
(Channel Select or Enable Inputs)
V
CC
V
CC
= 3.3 V ± 0.3 V
= 5.0 V ± 0.5 V
0
0
100
20
*For voltage drops across switch greater than 1.2 V (switch on), excessive V current may be
CC
drawn; i.e., the current out of the switch may contain both V and switch input components. The
CC
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
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3
MC74LVX8051
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND)
Guaranteed Limit
−55 to 25°C ≤85°C ≤125°C
V
V
CC
Symbol
Parameter
Condition
= Per Spec
Unit
V
IH
Minimum High−Level Input Voltage,
Channel−Select or Enable Inputs
R
R
2.5
3.0
4.5
5.5
1.50
2.10
3.15
3.85
1.50
2.10
3.15
3.85
1.50
2.10
3.15
3.85
V
on
on
V
IL
Maximum Low−Level Input Voltage,
Channel−Select or Enable Inputs
= Per Spec
2.5
3.0
4.5
5.5
0.5
0.9
0.5
0.9
0.5
0.9
V
1.35
1.65
1.35
1.65
1.35
1.65
I
Maximum Input Leakage Current,
Channel−Select or Enable Inputs
V
= V or GND
5.5
± 0.1
± 1.0
± 1.0
mA
mA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
Channel Select, Enable and
= V or GND; V = 0 V
5.5
4.0
40
160
CC
V
IS
CC
IO
DC ELECTRICAL CHARACTERISTICS Analog Section
Guaranteed Limit
– 55 to
v
v
V
V
CC
25_C
40
30
25
85_C
125_C
Symbol
Parameter
Test Conditions
= V or V
Unit
R
Maximum “ON” Resistance
V
V
3.0
4.5
5.5
45
32
28
50
37
30
W
on
in
IL
IH
= V to GND
IS
CC
|I | v 10.0 mA (Figures 1, 2)
S
V
V
= V or V
IH
3.0
4.5
5.5
30
25
20
35
28
25
40
35
30
in
IL
= V or GND (Endpoints)
IS
CC
|I | v 10.0 mA (Figures 1, 2)
S
DR
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
V
V
= V or V
IH
3.0
4.5
5.5
15
8.0
8.0
20
12
12
25
15
15
W
on
in
IL
= 1/2 (V − GND)
IS
CC
|I | v 10.0 mA
S
I
off
Maximum Off−Channel Leakage
Current, Any One Channel
V
V
= V or V ;
IH
5.5
5.5
5.5
0.1
0.2
0.2
0.5
2.0
2.0
1.0
4.0
4.0
mA
in
IL
= V or GND;
IO
CC
Switch Off (Figure 3)
Maximum Off−Channel
Leakage Current,
Common Channel
V
V
= V or V ;
IL IH
in
= V or GND;
IO
CC
Switch Off (Figure 4)
I
on
Maximum On−Channel
Leakage Current,
V
in
= V or V
;
IH
mA
IL
Switch−to−Switch =
Channel−to−Channel
V
CC
or GND; (Figure 5)
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4
MC74LVX8051
AC CHARACTERISTICS (C = 50 pF, Input t = t = 3 ns)
L
r
f
Guaranteed Limit
−55 to 25°C ≤85°C ≤125°C
V
V
CC
Symbol
Parameter
Unit
t
t
t
t
,
Maximum Propagation Delay, Channel−Select to Analog Output
(Figure 9)
2.5
3.0
4.5
5.5
30
20
15
15
35
25
18
18
40
30
22
20
ns
PLH
t
PHL
,
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
2.5
3.0
4.5
5.5
4.0
3.0
1.0
1.0
6.0
5.0
2.0
2.0
8.0
6.0
2.0
2.0
ns
ns
ns
PLH
t
PHL
,
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.5
3.0
4.5
5.5
30
20
15
15
35
25
18
18
40
30
22
20
PLZ
t
PHZ
,
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.5
3.0
4.5
5.5
20
12
8.0
8.0
25
14
10
10
30
15
12
12
PZL
t
PZH
C
Maximum Input Capacitance, Channel−Select or Enable Inputs
10
35
10
35
10
35
pF
pF
in
C
Maximum Capacitance
(All Switches Off)
Analog I/O
I/O
Common O/I
Feedthrough
130
1.0
130
1.0
130
1.0
Typical @ 25°C, V = 5.0 V
CC
45
C
Power Dissipation Capacitance (Figure 13)*
pF
PD
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Limit*
V
CC
25°C
V
Symbol
Parameter
Condition
= 1MHz Sine Wave; Adjust f Voltage to Obtain
Unit
BW
Maximum On−Channel Bandwidth or
Minimum Frequency Response
(Figure 6)
f
MHz
in
in
0dBm at V ; Increase f Frequency Until dB
OS
in
80
80
80
3.0
4.5
5.5
Meter Reads −3dB;
R = 50W, C = 10pF
L
L
—
—
Off−Channel Feedthrough Isolation
(Figure 7)
f
= Sine Wave; Adjust f Voltage to Obtain 0dBm
3.0
4.5
5.5
−50
−50
−50
dB
in
in
at V
IS
f
in
= 10kHz, R = 600W, C = 50pF
L L
3.0
4.5
5.5
−37
−37
−37
f
in
= 1.0MHz, R = 50W, C = 10pF
L L
Feedthrough Noise. Channel−Select
Input to Common I/O (Figure 8)
V
≤ 1MHz Square Wave (t = t = 6ns); Adjust R
3.0
4.5
5.5
25
105
135
mV
PP
in
r
f
L
at Setup so that I = 0A;
Enable = GND
S
R = 600W, C = 50pF
L L
3.0
4.5
5.5
35
145
190
R = 10kW, C = 10pF
L
L
THD
Total Harmonic Distortion
(Figure 14)
f
= 1kHz, R = 10kW, C = 50pF
%
in
L
L
THD = THD
− THD
measured
source
V
= 2.0V sine wave
3.0
4.5
5.5
0.10
0.08
0.05
IS
PP
V
IS
V
IS
= 4.0V sine wave
PP
= 5.0V sine wave
PP
*Limits not tested. Determined by design and verified by qualification.
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5
MC74LVX8051
40
35
30
25
20
15
10
5
125°C
85°C
25°C
−ꢀ55°C
0
0
1.0
2.0
3.0
4.0
V , INPUT VOLTAGE (VOLTS)
IN
Figure 1a. Typical On Resistance, VCC = 3.0 V
30
25
20
15
25
125°C
85°C
20
125°C
85°C
25°C
15
25°C
−ꢀ55°C
−ꢀ55°C
10
10
5
5
0
0
0
1.0
2.0
3.0
4.0
5.0
0
1.0
2.0
3.0
4.0
5.0
6.0
V , INPUT VOLTAGE (VOLTS)
IN
V , INPUT VOLTAGE (VOLTS)
IN
Figure 1b. Typical On Resistance, VCC = 4.5 V
Figure 1c. Typical On Resistance, VCC = 5.5 V
PLOTTER
PROGRAMMABLE
POWER
SUPPLY
MINI COMPUTER
DC ANALYZER
−
+
V
CC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
GND
GND
Figure 2. On Resistance Test Set−Up
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6
MC74LVX8051
V
CC
V
CC
V
V
CC
CC
16
16
GND
GND
ANALOG I/O
OFF
OFF
OFF
OFF
A
V
V
CC
V
CC
COMMON O/I
NC
COMMON O/I
V
IH
6
8
6
8
IH
Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up
Figure 4. Maximum Off Channel Leakage Current,
Common Channel, Test Set−Up
V
CC
V
OS
V
CC
V
CC
16
16
0.1mF
A
dB
METER
f
in
ON
ON
N/C
R
L
GND
C *
L
COMMON O/I
OFF
V
CC
ANALOG I/O
V
IL
6
8
6
8
*Includes all probe and jig capacitance
Figure 5. Maximum On Channel Leakage Current,
Channel to Channel, Test Set−Up
Figure 6. Maximum On Channel Bandwidth,
Test Set−Up
V
CC
V
CC
V
IS
V
OS
16
16
0.1mF
dB
METER
R
L
f
in
OFF
ON/OFF
OFF/ON
COMMON O/I
TEST
POINT
ANALOG I/O
R
L
R
L
C *
L
R
L
C *
L
R
L
6
8
6
8
V
CC
V
≤ 1 MHz
11
in
t = t = 3 ns
r
f
V
CC
CHANNEL SELECT
*Includes all probe and jig capacitance
CHANNEL SELECT
*Includes all probe and jig capacitance
V
IL
or V
GND
IH
Figure 7. Off Channel Feedthrough Isolation,
Test Set−Up
Figure 8. Feedthrough Noise, Channel Select to
Common Out, Test Set−Up
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MC74LVX8051
V
CC
V
CC
16
V
CC
ON/OFF
OFF/ON
COMMON O/I
C *
CHANNEL
SELECT
TEST
POINT
50%
ANALOG I/O
GND
L
t
t
PHL
PLH
6
8
ANALOG
OUT
50%
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 9a. Propagation Delays, Channel Select
to Analog Out
Figure 9b. Propagation Delay, Test Set−Up Channel
Select to Analog Out
V
CC
16
COMMON O/I
C *
ANALOG I/O
TEST
POINT
V
CC
ON
ANALOG
IN
50%
L
GND
t
t
PHL
PLH
6
8
ANALOG
OUT
50%
*Includes all probe and jig capacitance
Figure 10a. Propagation Delays, Analog In
to Analog Out
Figure 10b. Propagation Delay, Test Set−Up
Analog In to Analog Out
t
t
POSITION 1 WHEN TESTING t
AND t
PZH
POSITION 2 WHEN TESTING t AND t
f
r
PHZ
1
2
PLZ
PZL
V
CC
90%
50%
10%
ENABLE
V
CC
GND
1kW
V
CC
16
t
t
PLZ
PZL
HIGH
IMPEDANCE
1
2
ANALOG I/O
ENABLE
TEST
POINT
ON/OFF
ANALOG
OUT
50%
C *
L
10%
V
OL
t
t
PHZ
PZH
6
8
V
OH
90%
ANALOG
OUT
50%
HIGH
IMPEDANCE
Figure 11a. Propagation Delays, Enable to
Analog Out
Figure 11b. Propagation Delay, Test Set−Up
Enable to Analog Out
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MC74LVX8051
V
CC
V
IS
A
V
CC
16
16
R
L
V
OS
ON/OFF
OFF/ON
COMMON O/I
f
in
ON
NC
ANALOG I/O
0.1mF
OFF
R
L
R
L
C *
L
C *
L
V
CC
R
L
6
8
6
8
11
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 12. Crosstalk Between Any Two
Switches, Test Set−Up
Figure 13. Power Dissipation Capacitance,
Test Set−Up
0
−ꢀ10
−ꢀ20
−ꢀ30
−ꢀ40
V
IS
FUNDAMENTAL FREQUENCY
V
CC
V
OS
16
0.1mF
TO
DISTORTION
METER
f
in
ON
R
L
C *
L
−ꢀ50
−ꢀ60
DEVICE
SOURCE
6
8
−ꢀ70
−ꢀ80
−ꢀ90
*Includes all probe and jig capacitance
−100
1.0
2.0
3.125
FREQUENCY (kHz)
Figure 14a. Total Harmonic Distortion, Test Set−Up
Figure 14b. Plot, Harmonic Distortion
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at connected). However, tying unused analog inputs and
V
CC
or GND logic levels. V being recognized as a logic
outputs to V or GND through a low value resistor helps
CC
CC
high and GND being recognized as a logic low. In this
example:
minimize crosstalk and feedthrough noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
V
= +5V = logic high
CC
GND = 0V = logic low
The maximum analog voltage swing is determined by the
supply voltage V . The positive peak analog voltage
V
CC
− GND = 2 to 6 volts
CC
should not exceed V . Similarly, the negative peak analog
When voltage transients above V and/or below GND
CC
CC
voltage should not go below GND. In this example, the
are anticipated on the analog channels, external Germanium
difference between V and GND is five volts. Therefore,
or Schottky diodes (D ) are recommended as shown in
CC
x
using the configuration of Figure 15, a maximum analog
signal of five volts peak−to−peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
Figure 16. These diodes should be able to absorb the
maximum anticipated current surges during clipping.
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MC74LVX8051
V
CC
V
CC
+5V
V
CC
D
D
16
x
16
ON/OFF
x
+5V
0V
+5V
0V
ANALOG
SIGNAL
ANALOG
SIGNAL
ON
D
x
D
x
GND
GND
TO EXTERNAL CMOS
CIRCUITRY 0 to 5V
DIGITAL SIGNALS
6
8
11
10
9
8
Figure 15. Application Example
Figure 16. External Germanium or
Schottky Clipping Diodes
+5V
+5V
16
16
+5V
+5V
+5V
+5V
ANALOG
SIGNAL
ANALOG
SIGNAL
ANALOG
SIGNAL
ANALOG
SIGNAL
ON/OFF
ON/OFF
GND
GND
GND
GND
+5V
*
R
R
R
+5V
6
8
11
10
9
6
8
11
10
9
LSTTL/NMOS
CIRCUITRY
LSTTL/NMOS
CIRCUITRY
* 2K ≤ R ≤ 10K
VHCT1GT50
BUFFERS
a. Using Pull−Up Resistors
b. Using HCT Interface
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs
11
10
9
13
X0
LEVEL
SHIFTER
A
14
X1
15
X2
LEVEL
SHIFTER
B
12
X3
1
LEVEL
SHIFTER
C
X4
5
X5
6
2
LEVEL
SHIFTER
ENABLE
X6
4
X7
3
X
Figure 18. Function Diagram, LVX8051
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10
MC74LVX8051
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
G
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
7
0
_
_
_
_
M
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE A
NOTES:
16X KREF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T U
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
M
−V−
A
B
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
N
C
1.20
−−− 0.047
D
F
0.15 0.002 0.006
0.75 0.020 0.030
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
DETAIL E
H
SEATING
PLANE
−T−
D
G
http://onsemi.com
11
MC74LVX8051
SOEIAJ−16
M SUFFIX
CASE 966−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
9
L
E
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
Q
1
H
E
M
_
E
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
8
L
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN
−−−
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
A
−−−
0.05
0.35
0.18
9.90
5.10
2.05
A
A
1
0.20 0.002
0.50 0.014
0.27 0.007
1
b
0.13 (0.005)
b
c
0.10 (0.004)
M
D
E
10.50
5.45 0.201
0.390
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0.90 0.028
10
_
0.035
0.031
0
_
_
_
0.70
−−−
1
Z
0.78
−−−
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