MC14532BCPG [ONSEMI]
MC14532B_06;
ONSEMI 
MC14532B
8−Bit Priority Encoder
The MC14532B is constructed with complementary MOS (CMOS)
enhancement mode devices. The primary function of a priority
encoder is to provide a binary address for the active input with the
highest priority. Eight data inputs (D0 thru D7) and an enable input
(E are provided. Five outputs are available, three are address outputs
in)
http://onsemi.com
MARKING
(Q0 thru Q2), one group select (GS) and one enable output (E ).
out
Features
• Diode Protection on All Inputs
DIAGRAMS
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load over the Rated Temperature Range
• Pb−Free Packages are Available*
MC14532BCP
AWLYYWWG
1
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
1
PDIP−16
P SUFFIX
CASE 648
Rating
Symbol
Value
−0.5 to +18.0
Unit
V
DC Supply Voltage Range
V
DD
Input or Output Voltage Range
(DC or Transient)
V ,
−0.5 to V + 0.5
V
in
DD
V
out
Input or Output Current
(DC or Transient) per Pin
I , I
in out
10
mA
Power Dissipation, per Package (Note 1)
Ambient Temperature Range
P
T
500
mW
°C
D
14532BG
AWLYWW
−55 to +125
−65 to +150
260
A
SOIC−16
D SUFFIX
CASE 751B
1
Storage Temperature Range
T
stg
°C
1
Lead Temperature (8 Sec Soldering)
T
°C
L
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
A
WL
= Assembly Location
= Wafer Lot
YY, Y = Year
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
WW = Work Week
G
= Pb−Free Package
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V and V should be constrained
in
out
PIN ASSIGNMENT
to the range V v (V or V ) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D4
D5
D6
D7
V
E
SS
DD
DD
TRUTH TABLE
out
Input
Output
GS
E
D7 D6 D5 D4 D3 D2 D1 D0 GS Q2 Q1 Q0
E
D3
D2
D1
D0
Q0
in
out
0
1
0
1
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
0
0
0
0
0
0
0
0
E
in
Q2
Q1
1
1
1
1
1
0
0
0
X
1
0
0
X
X
1
0
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
0
0
0
0
V
SS
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
X
1
0
0
X
X
1
0
X
X
X
1
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
0
0
0
0
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
X = Don’t Care
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
April, 2006 − Rev. 6
MC14532B/D
MC14532B
ORDERING INFORMATION
Device
†
Package
Shipping
MC14532BCP
PDIP−16
25 Units / Rail
48 Units / Rail
MC14532BCPG
PDIP−16
(Pb−Free)
MC14532BD
SOIC−16
MC14532BDG
SOIC−16
(Pb−Free)
MC14532BDR2
SOIC−16
2500 / Tape & Reel
MC14532BDR2G
SOIC−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
− 55_C
25_C
Typ
125_C
V
DD
(Note 2)
Min
Max
Min
Max
Min
Max
Symbol
Vdc
Characteristic
Output Voltage
Unit
“0” Level
V
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
OL
V
in
= V or 0
DD
V
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Vdc
“1” Level
“0” Level
OH
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
V
Vdc
“1” Level
IH
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
(V = 0.5 or 4.5 Vdc)
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
–3.0
– 0.64
–1.6
−
−
−
−
–2.4
– 0.51
–1.3
–4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
–1.7
– 0.36
–0.9
−
−
−
−
OH
OH
OH
OH
15
– 4.2
–3.4
–2.4
(V = 0.4 Vdc)
I
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
OL
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
I
15
−
−
−
0.1
−
−
−
0.00001
5.0
0.1
7.5
−
−
1.0
−
mAdc
in
Input Capacitance
C
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.005
0.010
0.015
5.0
10
20
−
−
−
150
300
600
mAdc
mAdc
DD
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent,
Per Package)
I
5.0
10
15
I
I
I
= (1.74 mA/kHz) f + I
= (3.65 mA/kHz) f + I
= (5.73 mA/kHz) f + I
T
T
T
T
DD
DD
DD
(C = 50 pF on all outputs, all
L
buffers switching)
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in mA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.005.
T
L
DD
SS
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2
MC14532B
SWITCHING CHARACTERISTICS (C = 50 pF, T = 25_C) (Note 5)
L
A
Characteristic
Symbol
V
Min
Typ
Max
Unit
DD
(Note 6)
Output Rise and Fall Time
t
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
= (0.75 ns/pF) C + 12.5 ns
= (0.55 ns/pF) C + 9.5 ns
5.0
10
15
−
−
−
100
50
40
200
100
80
TLH THL
L
THL
, t
TLH THL
L
L
, t
TLH THL
Propagation Delay Time — E to E
t
t
t
t
t
,
PLH
ns
ns
ns
ns
ns
in
out
t
t
t
, t
= (1.7 ns/pF) C + 120 ns
t
5.0
10
15
−
−
−
205
110
80
410
220
160
PLH PHL
L
PHL
, t
= (0.66 ns/pF) C + 77 ns
PLH PHL
L
, t
= (0.5 ns/pF) C + 55 ns
L
PLH PHL
Propagation Delay Time — E to GS
,
PLH
in
t
t
t
, t
= (1.7 ns/pF) C + 90 ns
t
5.0
10
15
−
−
−
175
90
65
350
180
130
PLH PHL
L
PHL
, t
= (0.66 ns/pF) C 57 ns
PLH PHL
L
, t
= (0.5 ns/pF) C + 40 ns
PLH PHL
L
Propagation Delay Time — E to Q
,
PHL
in
n
t
t
t
, t
= (1.7 ns/pF) C + 195 ns
t
5.0
10
15
−
−
−
280
140
100
560
280
200
PLH PHL
L
PLH
, t
= (0.66 ns/pF) C + 107 ns
PLH PHL
L
, t
= (0.5 ns/pF) C + 75 ns
L
PLH PHL
Propagation Delay Time — D to Q
,
PLH
n
n
t
t
t
, t
= (1.7 ns/pF) C + 265 ns
t
5.0
10
15
−
−
−
300
170
110
600
340
220
PLH PHL
L
PHL
, t
= (0.66 ns/pF) C + 137 ns
PLH PHL
L
, t
= (0.5 ns/pF) C + 85 ns
L
PLH PHL
Propagation Delay Time — D to GS
,
PLH
n
t
t
t
, t
= (1.7 ns/pF) C + 195 ns
t
5.0
10
15
−
−
−
280
140
100
560
280
200
PLH PHL
L
PHL
, t
= (0.66 ns/pF) C + 107 ns
PLH PHL
L
, t
= (0.5 ns/pF) C + 75 ns
L
PLH PHL
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
V
out
E
in
D0
D1
E
out
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
GS
SWITCH
MATRIX
V
DD
I
D
500 mF
I
D
0.01 mF
EXTERNAL
POWER
SUPPLY
E
E
out
in
C
L
D0
D1
Q0
V
V
= V
V
= – V
GS DD
GS
DD
C
L
= V
V
= V
– V
DD
D2
D3
D4
D5
D6
D7
DS
out
DS
out
Output
Under
Test
Sink Current
Source Current
D0 thru D6 D7 E
in
Q1
Q2
GS
C
L
D0 thru D7
E
in
E
X
X
X
X
X
0
0
0
0
0
0
0
1
1
1
1
1
out
C
L
PULSE
GENERATOR
(f )
Q0
Q1
Q2
GS
0
0
0
0
1
1
1
1
C
o
L
V
SS
Figure 1. Typical Sink and Source
Current Characteristics
Figure 2. Typical Power Dissipation Test Circuit
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3
MC14532B
V
DD
E
E
out
in
D0
D1
C
L
Q0
Q1
D2
D3
D4
D5
D6
D7
C
PROGRAMMABLE
PULSE
GENERATOR
L
C
L
Q2
GS
C
L
C
L
V
SS
NOTE: Input rise and fall times are 20 ns
PIN
NO.
50%
D0 10
50%
D1
11
50%
D2 12
D3 13
50%
50%
D4
D5
1
2
50%
50%
D6
D7
3
4
50%
50%
E
5
in
t
t
PHL
PLH
90%
50%
10%
E
15
out
t
THL
t
PHL
t
TLH
t
PLH
90%
50%
10%
GS 14
t
t
t
t
t
TLH
t
PLH
PLH
PLH
THL
t
t
t
t
PHL
PLH
PHL
PHL
PHL
90%
50%
10%
Q0
Q1
9
7
t
t
t
t
PLH
PLH
TLH
THL
t
t
PHL
PHL
90%
50%
10%
t
t
THL
TLH
t
t
PHL
PLH
90%
50%
10%
Q2
6
t
t
TLH
THL
Figure 3. AC Test Circuit and Waveforms
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4
MC14532B
LOGIC EQUATIONS
E
= E ꢀ D0 ꢀ D1 ꢀ D2 ꢀ D3 ꢀ D4 ꢀ D5 ꢀ D6 ꢀ D7
in
out
Q0 = E ꢀ (D1 ꢀ D2 ꢀ D4 ꢀ D6 + D3 ꢀ D4 ꢀ D6 + D5 ꢀ D6 + D7)
in
Q1 = E ꢀ (D2 ꢀ D4 ꢀ D5 + D3 ꢀ D4 ꢀ D5 + D6 + D7)
in
10
11
Q2 = E ꢀ (D4 + D5 + D6 + D7)
in
D0
D1
GS = E ꢀ (D0 + D1 + D2 + D3 + D4 + 05 + D6 + D7)
in
9
Q0
12
13
1
D2
D3
D4
D5
7
Q1
2
3
4
D6
D7
6
Q2
GS
5
E
in
14
15
E
out
Figure 4. Logic Diagram
(Positive Logic)
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5
MC14532B
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
E
= ꢀ1"
WITH D = ꢀ0"
out
V
E
E
E
E
out
DD
in
out
in
in
GS
Q2 Q1 Q0
Q2 Q1 Q0
3/4 MC14071B
Q3
Q2
Q1
Q0
Figure 5. Two MC14532B’s Cascaded for 4−Bit Output
V
V
SS
DD
CLOCK
INPUT
C
E
R
C
E
R
1/2 MC14520B
Q2 Q3
1/2 MC14520B
Q2 Q3
DIGITAL TO ANALOG CONVERSION
Q1
Q4
Q1
Q4
The digital eight−bit word to be converted is applied to the
inputs of the MC14512 with the most significant bit at X7
and the least significant bit at X0. A clock input of up to
2.5 MHz (at V
= 10 V) is applied to the MC14520B.
DD
A compromise between I
for the MC1710 and DR be-
bias
tween N and P−channel outputs gives a value of R of 33 kW.
In order to filter out the switching frequencies, RC should
be about 1.0 ms (if R = 33 kW, C [ 0.03 mF). The analog 3.0
dB bandwidth would then be dc to 1.0 kHz.
DIGITAL INPUT/OUTPUT
D0 D1 D2 D3 D4 D5 D6 D7
8−BIT WORD
TO BE CONVERTED
E
in
V
ANALOG TO DIGITAL CONVERSION
DD
Q2 Q1 Q0
An analog signal is applied to the analog input of the
MC1710. A digital eight−bit word known to represent a dig-
itized level less than the analog input is applied to the
MC14512 as in the D to A conversion. The word is increm-
ented at rates sufficient to allow steady state to be reached
between incrementations (i.e. 3.0 ms). The output of the
MC1710 will change when the digital input represents the
first digitized level above the analog input. This word is the
digital representation of the analog word.
X7 X6 X5 X4 X3 X2 X1 X0
A
B
C
MC14512
Z
MC1710
R
ANALOG
OUTPUT
STOP
WORD
INCREMENTATION
C
ANALOG
INPUT
Figure 6. Digital to Analog and Analog to Digital Converter
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6
MC14532B
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
16
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
F
C
L
MIN MAX
A
B
C
D
F
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
−T−
0.040
0.70
G
H
J
K
L
0.100 BSC
2.54 BSC
1.27 BSC
K
M
H
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
J
0.21
0.38
3.30
7.74
10
G
2.80
7.50
0
D 16 PL
M
M
0.25 (0.010)
T A
M
S
0
10
_
_
_
_
0.020 0.040
0.51
1.01
SOIC−16
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
5.80
0.25
0.25
0.25
7
6.20
0.50
0.008
0.004
0
0.229
0.010
0.009
0.009
7
0.244
0.019
−T−
SEATING
PLANE
K
M
P
R
J
_
_
_
_
M
D
16 PL
M
S
S
0.25 (0.010)
T
B
A
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
MC14532B/D
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