MC14532BDR2 [ONSEMI]
8-Bit Priority Encoder; 8位优先编码器
| 型号： | MC14532BDR2 |
| 厂家： | 
ONSEMI |
| 描述： | 8-Bit Priority Encoder |
| 文件： | 总12页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC14532B is constructed with complementary MOS (CMOS)
enhancement mode devices. The primary function of a priority
encoder is to provide a binary address for the active input with the
highest priority. Eight data inputs (D0 thru D7) and an enable input
(E are provided. Five outputs are available, three are address outputs
in)
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(Q0 thru Q2), one group select (GS) and one enable output (E ).
out
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
MARKING
DIAGRAMS
16
• Capable of Driving Two Low–power TTL Loads or One Low–Power
PDIP–16
P SUFFIX
CASE 648
Schottky TTL Load over the Rated Temperature Range
MC14532BCP
AWLYYWW
1
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
16
SS
SOIC–16
D SUFFIX
CASE 751B
Symbol
Parameter
Value
Unit
V
14532B
AWLYWW
V
DD
DC Supply Voltage Range
–0.5 to +18.0
1
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
16
I , I
Input or Output Current
(DC or Transient) per Pin
±10
mA
in out
SOEIAJ–16
F SUFFIX
CASE 966
MC14532B
AWLYWW
P
D
Power Dissipation,
500
mW
per Package (Note 3.)
1
T
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
A
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
T
stg
T
Lead Temperature
(8–Second Soldering)
L
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
ORDERING INFORMATION
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Device
Package
PDIP–16
SOIC–16
Shipping
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
MC14532BCP
MC14532BD
2000/Box
48/Rail
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
MC14532BDR2
SOIC–16 2500/Tape & Reel
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
MC14532BF
SOEIAJ–16
SOEIAJ–16
SOEIAJ–16
See Note 1.
See Note 1.
See Note 1.
SS
DD
MC14532BFEL
MC14532BFR1
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14532B/D
MC14532B
PIN ASSIGNMENT
D4
D5
D6
D7
1
2
3
4
5
6
7
8
16
15
V
DD
E
out
14 GS
13 D3
12 D2
11 D1
10 D0
E
in
Q2
Q1
V
SS
9
Q0
TRUTH TABLE
Input
Output
E
in
D7 D6 D5 D4 D3 D2 D1 D0 GS Q2 Q1 Q0
E
out
0
1
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
X
1
0
0
X
X
1
0
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
X
1
0
0
X
X
1
0
X
X
X
1
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
0
0
0
0
X = Don’t Care
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2
MC14532B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
125 C
V
Vdc
DD
(4.)
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
(5.) (6.)
Total Supply Current
I
T
5.0
10
15
I = (1.74 µA/kHz) f + I
T
I = (3.65 µA/kHz) f + I
T
I = (5.73 µA/kHz) f + I
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25 C.
6. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.005.
T
L
DD
SS
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3
MC14532B
SWITCHING CHARACTERISTICS (7.) (C = 50 pF, T = 25 C)
L
A
(8.)
Characteristic
Symbol
V
DD
Min
Typ
Max
Unit
Output Rise and Fall Time
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
, t
= (0.75 ns/pF) C + 12.5 ns
TLH THL
L
, t
= (0.55 ns/pF) C + 9.5 ns
L
TLH THL
Propagation Delay Time — E to E
t
t
t
t
t
,
ns
ns
ns
ns
ns
in
out
PLH
t
t
t
, t
= (1.7 ns/pF) C + 120 ns
= (0.66 ns/pF) C + 77 ns
L
= (0.5 ns/pF) C + 55 ns
L
t
PHL
5.0
10
15
—
—
—
205
110
80
410
220
160
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
Propagation Delay Time — E to GS
,
PLH
t
PHL
in
t
t
t
, t
= (1.7 ns/pF) C + 90 ns
= (0.66 ns/pF) C 57 ns
L
5.0
10
15
—
—
—
175
90
65
350
180
130
PLH PHL
L
, t
PLH PHL
, t
= (0.5 ns/pF) C + 40 ns
PLH PHL
L
Propagation Delay Time — E to Q
,
PHL
t
PLH
in
n
t
t
t
, t
= (1.7 ns/pF) C + 195 ns
= (0.66 ns/pF) C + 107 ns
L
= (0.5 ns/pF) C + 75 ns
L
5.0
10
15
—
—
—
280
140
100
560
280
200
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
Propagation Delay Time — D to Q
,
PLH
t
PHL
n
n
t
t
t
, t
= (1.7 ns/pF) C + 265 ns
= (0.66 ns/pF) C + 137 ns
L
= (0.5 ns/pF) C + 85 ns
L
5.0
10
15
—
—
—
300
170
110
600
340
220
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
Propagation Delay Time — D to GS
,
PLH
n
t
t
t
, t
= (1.7 ns/pF) C + 195 ns
= (0.66 ns/pF) C + 107 ns
L
= (0.5 ns/pF) C + 75 ns
L
t
PHL
5.0
10
15
—
—
—
280
140
100
560
280
200
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
7. The formulas given are for the typical characteristics only at 25 C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
V
out
E
in
D0
D1
E
out
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
GS
SWITCH
MATRIX
V
DD
I
D
500 µF
I
D
0.01 µF
EXTERNAL
POWER
SUPPLY
E
in
E
out
C
L
D0
D1
Q0
Q1
V
V
= V
V
= – V
GS
DD
GS DD
C
L
D2
D3
D4
D5
D6
D7
= V
V
= V
– V
DD
DS
out
DS
out
Output
Under
Test
Sink Current
Source Current
D0 thru D6 D7 E
in
C
L
D0 thru D7
E
in
Q2
GS
E
X
X
X
X
X
0
0
0
0
0
0
0
1
1
1
1
1
out
C
L
PULSE
GENERATOR
Q0
Q1
Q2
GS
0
0
0
0
1
1
1
1
(f )
o
C
L
V
SS
Figure 1. Typical Sink and Source
Current Characteristics
Figure 2. Typical Power Dissipation Test Circuit
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4
MC14532B
V
DD
E
in
E
out
D0
D1
C
L
Q0
Q1
D2
D3
D4
D5
D6
D7
C
L
PROGRAMMABLE
PULSE
GENERATOR
C
L
Q2
GS
C
L
C
L
V
SS
NOTE: Input rise and fall times are 20 ns
PIN
NO.
50%
D0 10
50%
D1 11
D2 12
50%
50%
D3 13
50%
D4
D5
1
2
50%
50%
D6
D7
3
4
50%
50%
E
in
5
t
t
PHL
PLH
90%
50%
10%
E
out
15
t
THL
t
PHL
t
TLH
t
PLH
90%
50%
10%
GS 14
t
t
t
t
t
TLH
PLH
PLH
PLH
THL
t
t
t
t
t
PLH
PHL
PHL
PHL
PHL
90%
50%
10%
Q0
Q1
9
7
t
t
t
t
PLH
PLH
TLH
THL
t
t
PHL
PHL
90%
50%
10%
t
t
THL
TLH
t
t
PLH
PHL
90%
50%
10%
Q2
6
t
t
TLH
THL
Figure 3. AC Test Circuit and Waveforms
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5
MC14532B
LOGIC DIAGRAM
(Positive Logic)
LOGIC EQUATIONS
E
= E
D0 D1 D2 D3 D4 D5 D6 D7
(D1 D2 D4 D6 + D3 D4 D6 + D5 D6 + D7)
(D2 D4 D5 + D3 D4 D5 + D6 + D7)
(D4 + D5 + D6 + D7)
out
in
Q0 = E
Q1 = E
Q2 = E
in
in
in
10
11
D0
D1
GS = E
(D0 + D1 + D2 + D3 + D4 + 05 + D6 + D7)
in
9
Q0
12
13
1
D2
D3
D4
D5
7
Q1
2
3
4
D6
D7
6
Q2
5
E
in
14
GS
15
E
out
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6
MC14532B
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
E
= “1”
out
V
DD
E
in
E
out
E
in
E
out
WITH D = “0”
in
GS
Q2 Q1 Q0
Q2 Q1 Q0
3/4 MC14071B
Q3
Q2
Q1
Q0
Figure 4. Two MC14532B’s Cascaded for 4–Bit Output
V
DD
V
SS
CLOCK
INPUT
C
E
R
C
E
R
1/2 MC14520B
Q2 Q3
1/2 MC14520B
Q2 Q3
DIGITAL TO ANALOG CONVERSION
Q1
Q4
Q1
Q4
Thedigitaleight–bitwordtobeconvertedisappliedtothe
inputs of the MC14512 with the most significant bit at
X7 and the least significant bit at X0. A clock input of up to
2.5 MHz (at V
= 10 V) is applied to the MC14520B.
DD
A compromise between I
for the MC1710 and ∆R
bias
between N and P–channel outputs gives a value of R of
33 k ohms. In order to filter out the switching frequencies,
RC should be about 1.0 ms (if R = 33 k ohms, C 0.03 µF).
The analog 3.0 dB bandwidth would then be dc to 1.0 kHz.
DIGITAL INPUT/OUTPUT
D0 D1 D2 D3 D4 D5 D6 D7
8–BIT WORD
TO BE CONVERTED
E
in
V
DD
Q2 Q1 Q0
ANALOG TO DIGITAL CONVERSION
X7 X6 X5 X4 X3 X2 X1 X0
An analog signal is applied to the analog input of the
MC1710. A digital eight–bit word known to represent a dig-
itized level less than the analog input is applied to the
MC14512 as in the D to A conversion. The word is increm-
ented at rates sufficient to allow steady state to be reached
between incrementations (i.e. 3.0 ms). The output of the
MC1710 will change when the digital input represents the
first digitized level above the analog input. This word is the
digital representation of the analog word.
A
B
C
MC14512
Z
MC1710
R
C
ANALOG
OUTPUT
STOP
WORD
INCREMENTATION
ANALOG
INPUT
Figure 5. Digital to Analog and Analog to Digital Converter
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7
MC14532B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
G
H
J
K
L
M
S
C
L
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
0.040
0.70
SEATING
PLANE
–T–
0.100 BSC
0.050 BSC
0.008 0.015
2.54 BSC
1.27 BSC
K
M
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295 0.305
10
0.020 0.040
0.130
2.80
7.50
0
G
D 16 PL
0
0.51
1.01
M
M
0.25 (0.010)
T A
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8
MC14532B
PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00 0.386
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
R X 45
K
C
G
J
K
M
P
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
D
16 PL
7
0
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
R
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9
MC14532B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE O
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
16
9
8
Q
1
H
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
A
DIM MIN
MAX
MIN
–––
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
1
–––
0.05
0.35
0.18
9.90
5.10
2.05
A
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
0
0.70
–––
8.20 0.291
0.85 0.020
1.50 0.043
10
0.90 0.028
0.78 –––
0.323
0.033
0.059
10
0.035
0.031
E
L
L
E
M
Q
0
1
Z
http://onsemi.com
10
MC14532B
Notes
http://onsemi.com
11
MC14532B
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MC14532B/D
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