MC14532BD [MOTOROLA]
8-Bit Priority Encoder; 8位优先编码器
| 型号： | MC14532BD |
| 厂家： | 
MOTOROLA |
| 描述： | 8-Bit Priority Encoder |
| 文件： | 总8页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14532B is constructed with complementary MOS (CMOS)
enhancement mode devices. The primary function of a priority encoder is to
provide a binary address for the active input with the highest priority. Eight
data inputs (D0 thru D7) and an enable input (E are provided. Five outputs
in)
are available, three are address outputs (Q0 thru Q2), one group select (GS)
P SUFFIX
PLASTIC
CASE 648
and one enable output (E ).
out
•
•
•
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–Power
Schottky TTL Load over the Rated Temperature Range
D SUFFIX
SOIC
CASE 751B
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
ORDERING INFORMATION
V
DD
– 0.5 to + 18.0
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
V , V
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
in out
I , I
Input or Output Current (DC or Transient),
per Pin
± 10
mA
in out
T
A
= – 55° to 125°C for all packages.
P
Power Dissipation, per Package†
Storage Temperature
500
mW
C
D
T
stg
– 65 to + 150
260
PIN ASSIGNMENT
T
Lead Temperature (8–Second Soldering)
C
L
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
D4
D5
D6
D7
1
2
16
15
V
DD
E
out
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
3
4
5
6
7
8
14
13
12
11
10
9
GS
D3
D2
D1
D0
Q0
TRUTH TABLE
E
in
Input
Output
Q2
E
in
D7 D6 D5 D4 D3 D2 D1 D0 GS Q2 Q1 Q0
E
out
Q1
SS
0
1
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
0
0
0
0
0
0
0
0
0
1
V
1
1
1
1
1
0
0
0
X
1
0
0
X
X
1
0
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
X
1
0
0
X
X
1
0
X
X
X
1
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
0
0
0
0
X = Don’t Care
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V and
in
V
out
should be constrained to the range V
SS
≤ (V or V ) ≤ V .
in out DD
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V or V ). Unused outputs must be left open.
SS DD
REV 3
1/94
Motorola, Inc. 1995
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
Typ #
125 C
V
Vdc
DD
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V
DD
or 0
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
O
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V
(V
(V
(V
= 2.5 Vdc)
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
OH
OH
OH
15
(V
OL
(V
OL
(V
OL
= 0.4 Vdc)
= 0.5 Vdc)
= 1.5 Vdc)
I
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
Input Current
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
Input Capacitance
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
Total Supply Current**†
I
T
5.0
10
15
I
I
I
= (1.74 µA/kHz) f + I
= (3.65 µA/kHz) f + I
= (5.73 µA/kHz) f + I
T
T
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25 C.
†To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V
– V ) in volts, f in kHz is input frequency, and k = 0.005.
SS
T
L
DD
MC14532B
2
MOTOROLA CMOS LOGIC DATA
SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C)
L
A
Characteristic
Symbol
V
DD
Min
Typ #
Max
Unit
Output Rise and Fall Time
t
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
= (0.75 ns/pF) C + 12.5 ns
L
= (0.55 ns/pF) C + 9.5 ns
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
THL
, t
TLH THL
, t
TLH THL
L
Propagation Delay Time — E to E
in out
t
t
t
t
t
,
ns
ns
ns
ns
ns
PLH
t
t
t
, t
= (1.7 ns/pF) C + 120 ns
t
5.0
10
15
—
—
—
205
110
80
410
220
160
PLH PHL
PLH PHL
, t
PLH PHL
L
L
PHL
, t
= (0.66 ns/pF) C + 77 ns
= (0.5 ns/pF) C + 55 ns
L
Propagation Delay Time — E to GS
in
,
PLH
t
t
t
, t
= (1.7 ns/pF) C + 90 ns
t
5.0
10
15
—
—
—
175
90
65
350
180
130
PLH PHL
L
PHL
, t
= (0.66 ns/pF) C 57 ns
L
PLH PHL
, t
PLH PHL
= (0.5 ns/pF) C + 40 ns
L
Propagation Delay Time — E to Q
in
,
PHL
PLH
n
t
t
t
, t
= (1.7 ns/pF) C + 195 ns
t
5.0
10
15
—
—
—
280
140
100
560
280
200
PLH PHL
PLH PHL
, t
PLH PHL
L
L
, t
= (0.66 ns/pF) C + 107 ns
= (0.5 ns/pF) C + 75 ns
L
Propagation Delay Time — D to Q
,
PLH
PHL
n
n
t
t
t
, t
= (1.7 ns/pF) C + 265 ns
t
5.0
10
15
—
—
—
300
170
110
600
340
220
PLH PHL
L
, t
= (0.66 ns/pF) C + 137 ns
PLH PHL
L
, t
PLH PHL
= (0.5 ns/pF) C + 85 ns
L
Propagation Delay Time — D to GS
,
PLH
PHL
n
L
t
t
t
, t
= (1.7 ns/pF) C + 195 ns
t
5.0
10
15
—
—
—
280
140
100
560
280
200
PLH PHL
, t
= (0.66 ns/pF) C + 107 ns
PLH PHL
L
, t
PLH PHL
= (0.5 ns/pF) C + 75 ns
L
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
V
out
E
in
D0
D1
E
out
Q0
Q1
Q2
D2
D3
D4
D5
D6
D7
SWITCH
MATRIX
V
DD
I
D
GS
500 µF
I
0.01 µF
D
EXTERNAL
POWER
SUPPLY
E
E
in
out
C
L
D0
D1
Q0
V
V
= V
DD
V
= – V
DD
out DD
GS
DS
GS
= V
C
L
D2
D3
D4
D5
D6
D7
= V
V
– V
out
DS
Output
Under
Test
Sink Current
Source Current
Q1
Q2
C
L
D0 thru D7
E
D0 thru D6 D7
E
in
in
E
out
X
X
X
X
X
0
0
0
0
0
0
0
1
1
1
1
1
C
L
PULSE
GENERATOR
Q0
Q1
Q2
GS
0
0
0
0
1
1
1
1
GS
SS
(f )
C
o
L
V
Figure 1. Typical Sink and Source
Current Characteristics
Figure 2. Typical Power Dissipation Test Circuit
MOTOROLA CMOS LOGIC DATA
MC14532B
3
V
DD
E
E
in
out
D0
D1
C
L
Q0
D2
D3
D4
D5
D6
D7
C
PROGRAMMABLE
PULSE
GENERATOR
L
Q1
Q2
C
L
C
L
GS
C
L
V
SS
NOTE: Input rise and fall times are 20 ns
PIN
NO.
50%
D0
10
50%
D1
D2
11
12
50%
50%
D3
D4
D5
13
1
50%
50%
2
50%
D6
D7
3
4
50%
50%
E
5
in
t
t
PHL
PLH
90%
50%
10%
E
15
out
t
THL
t
t
PHL
90%
50%
TLH
t
PLH
10%
GS
Q0
Q1
14
9
t
t
t
t
t
TLH
PLH
PLH
PLH
PLH
THL
t
t
t
t
t
PHL
PHL
PHL
PHL
90%
50%
10%
t
PLH
t
PLH
t
t
TLH
THL
t
t
PHL
PHL
90%
50%
10%
7
t
t
TLH
THL
t
t
PLH
PHL
90%
50%
10%
Q2
6
t
t
TLH
THL
Figure 3. AC Test Circuit and Waveforms
MC14532B
MOTOROLA CMOS LOGIC DATA
4
LOGIC DIAGRAM
(Positive Logic)
LOGIC EQUATIONS
E
= E
in
D0 D1 D2 D3 D4 D5 D6 D7
(D1 D2 D4 D6 + D3 D4 D6 + D5 D6 + D7)
(D2 D4 D5 + D3 D4 D5 + D6 + D7)
(D4 + D5 + D6 + D7)
out
Q0 = E
Q1 = E
Q2 = E
in
in
10
11
in
D0
D1
GS = E
in
(D0 + D1 + D2 + D3 + D4 + 05 + D6 + D7)
9
Q0
12
13
1
D2
D3
D4
D5
7
Q1
2
3
4
D6
D7
6
Q2
5
E
in
14
GS
15
E
out
MOTOROLA CMOS LOGIC DATA
MC14532B
5
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6
D7 D6
D5 D4
D5 D4
D3 D2
D3 D2
D1 D0
D1 D0
D7 D6
D5 D4
D3 D2
D1 D0
E
= “1”
out
V
E
E
E
E
out
DD
in
out
in
WITH D = “0”
in
GS
Q2 Q1
Q0
Q2 Q1
Q0
3/4 MC14071B
Q3
Q2
Q1
Q0
Figure 4. Two MC14532B’s Cascaded for 4–Bit Output
V
V
SS
DD
CLOCK
INPUT
C
E
R
C
E
R
1/2 MC14520B
1/2 MC14520B
DIGITAL TO ANALOG CONVERSION
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
The digital eight–bit word to be converted is applied to
the inputs of the MC14512 with the most significant bit at
X7 and the least significant bit at X0. A clock input of up to
2.5 MHz (at V
= 10 V) is applied to the MC14520B.
DD
A compromise between I
for the MC1710 and ∆R
bias
between N and P–channel outputs gives a value of R of
33 k ohms. In order to filter out the switching frequencies,
RC should be about 1.0 ms (if R = 33 k ohms,
DIGITAL INPUT/OUTPUT
C
0.03 µF). The analog 3.0 dB bandwidth would then be
D0 D1 D2 D3 D4 D5 D6 D7
8–BIT WORD
TO BE CONVERTED
dc to 1.0 kHz.
V
E
DD
in
Q2 Q1 Q0
ANALOG TO DIGITAL CONVERSION
X7 X6 X5 X4 X3 X2 X1 X0
A
B
C
An analog signal is applied to the analog input of the
MC1710. A digital eight–bit word known to represent a digi-
tized level less than the analog input is applied to the
MC14512 as in the D to A conversion. The word is increm-
ented at rates sufficient to allow steady state to be reached
between incrementations (i.e. 3.0 ms). The output of the
MC1710 will change when the digital input represents the
first digitized level above the analog input. This word is the
digital representation of the analog word.
MC14512
Z
MC1710
R
ANALOG
OUTPUT
STOP
WORD
INCREMENTATION
C
ANALOG
INPUT
Figure 5. Digital to Analog and Analog to Digital Converter
MC14532B
6
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
16
1
9
8
–B–
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
0.785
0.295
0.200
0.020
MIN
19.05
6.10
–––
MAX
19.93
7.49
5.08
0.50
0.750
0.240
–––
–T–
SEATING
PLANE
0.015
0.39
K
N
E
0.050 BSC
1.27 BSC
F
0.055
0.065
1.40
1.65
G
H
K
L
M
N
0.100 BSC
2.54 BSC
M
E
0.008
0.125
0.015
0.170
0.21
3.18
0.38
4.31
F
J
16 PL
0.25 (0.010)
G
0.300 BSC
7.62 BSC
M
S
T
B
0
15
0
15
D 16 PL
0.25 (0.010)
0.020
0.040
0.51
1.01
M
S
T
A
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
PLANE
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
0.25 (0.010)
M
S
0.020
0.040
0.51
1.01
M
M
T
A
MOTOROLA CMOS LOGIC DATA
MC14532B
7
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
0.386
0.150
0.054
0.014
0.016
R X 45
K
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
D
16 PL
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,
Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
are registered
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609
INTERNET: http://Design–NET.com
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MC14532B/D
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相关型号：
MC14534BAL
4000/14000/40000 SERIES, ASYN POSITIVE EDGE TRIGGERED 20-BIT UP DECADE COUNTER, CDIP24, 623-05
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MC14534BALD
Decade Counter, 4000/14000/40000 Series, Asynchronous, Positive Edge Triggered, 20-Bit, Up Direction, CMOS, CDIP24, 623-05
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