LV8111VB-AH [ONSEMI]
3-phase Brushless Motor Driver;
| 型号： | LV8111VB-AH |
| 厂家： | 
ONSEMI |
| 描述： | 3-phase Brushless Motor Driver |
| 文件： | 总15页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LV8111VB
Bi-CMOS LSI
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3-phase Brushless Motor Driver
for Polygon Mirror Motor
Overview
The LV8111VB is a 3-phase brushless motor driver for polygon mirror
motor driving of LBP.
A circuit needed to drive of polygon mirror motor can be composed of
a single-chip. Also, the output transistor is made DMOS by using
BiDC process, and by adopting the synchronous rectification method,
the lower power consumption (Heat generation) is achieved.
Feature
3-phase bipolar drive
SSOP44K(275mil) Exposed Pad
Direct PWM drive + synchronous rectification
I max1 = 2.5A
O
I max2 = 3.0A (t 0.1ms)
O
Output current control circuit
PLL speed control circuit
Phase lock detection output
(with mask function)
Current limiter, constraint protection, thermal
shutdown, under-voltage protection circuit
Circuit to switch slowing down method while stopped
(Free run or Short-circuit brake)
Constraint protection detection signal switching circuit (FG or LD)
Forward / Reverse switching circuit
Compatible with Hall FG
Hall bias pin (Bias current cut in a stopped state)
5V regulator output
SDCC function (Speed Detection Current Control)
Typical Applications
Laser beam printer (LBP)
Plain paper copier (PPC)
Multi function printer (MFP)
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
December 2014 - Rev. 1
1
Publication Order Number :
LV8111VB/D
LV8111VB
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter
Supply voltage
Symbol
max
Conditions
Ratings
Unit
V
V
V
pin
CC
37
42
CC
VG max
VG pin
*1
V
Output current
I
I
max1
max2
2.5
A
O
O
t 0.1ms *1
3.0
A
Allowable Power dissipation
Operation temperature
Storage temperature
Pd max
Topr
Mounted on a specified board *2
1.7
W
C
C
C
-25 to +80
-55 to +150
150
Tstg
Junction temperature
Tj max
*1. Tj max = 150C must not be exceeded.
*2. Specified board: 114.3mm × 76.1mm × 1.6mm, glass epoxy board.
Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Recommended Operating Conditions at Ta = 25C
Parameter
Symbol
Conditions
Ratings
Unit
V
Supply voltage range
V
I
10 to 35
0 to -30
0 to 5.5
0 to 15
0 to 5.5
0 to 15
0 to -30
CC
5V constant voltage output current
LD pin applied voltage
LD pin output current
mA
V
REG
V
LD
I
mA
V
LD
FG pin applied voltage
FG pin output current
V
I
FG
mA
mA
FG
HB pin output current
I
HB
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Electrical Characteristics at Ta 25C, V
= 24V
CC
Ratings
typ
Parameter
Symbol
1
Conditions
Unit
min
max
6.5
Current drain
I
I
5.5
mA
mA
CC
2
In a stop state
1.0
1.5
CC
5V Constant Voltage Output
Output voltage
VREG
4.65
5.0
20
25
0
5.35
100
60
V
mV
Line regulation
VREG1
VREG2
VREG3
V
= 10 to 35V
CC
= -5 to -20mA
Load regulation
I
mV
O
Temperature coefficient
Output Block
Design target value *
mV/C
Output ON resistance
R
I
= 1A , Sum of the lower and upper side
O
1.5
1.9
ON
outputs
Output leakage current
I
leak
1
Design target value *
10
1.35
1.35
A
V
O
Lower side Diode forward voltage
Upper side Diode forward voltage
Charge Pump Output (VG pin)
Output voltage
V
I
I
= -1A
= 1A
1.0
1.0
D
D
D
V
2
V
D
VG
OUT
V
+4.9
V
CC
CP1 pin
Output ON resistance (High level)
Output ON resistance (Low level)
V
(CP1)
OH
I
I
= -2mA, Design target value *
= 2mA
500
300
700
400
CP1
CP1
V (CP1)
OL
* Design target value, Do not measurement.
Continued on next page.
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2
LV8111VB
Continued from preceding page.
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
Hall Amplifier Block
Input bias current
I
(HA)
-2
0.5
80
-0.5
A
V
HB
Common mode input voltage range
Hall input sensitivity
V
VREG-2.0
42
ICM
mVp-p
mV
Hysteresis
V (HA)
IN
15
24
12
Input voltage L H
V
V
mV
SLH
SHL
Input voltage H L
-12
mV
Hall Bias (HB pin) P-channel Output
Output voltage ON resistance
Output leakage current
FG Amplifier Schmitt Block (IN1)
Input amplifier gain
V
(HB)
I
= -20mA
20
30
10
OL
HB
I (HB)
L
V
= 0V
A
O
G
Design target value *
5
0
times
mV
FG
Input hysteresis (H L)
Input hysteresis (L H)
Hysteresis
V
V
V
(FGS) Input referred, Design target value *
(FGS) Input referred, Design target value *
Input referred, Design target value *
SHL
SLH
FGL
10
10
mV
mV
FGFIL pin
High level output voltage
Low level output voltage
External capacitor charge current
External capacitor discharge current
Amplitude
V
(FGFIL)
OH
2.7
3.0
0.85
-4
3.3
0.95
-3
V
V
V
(FGFIL)
0.75
-5
OL
I
I
1
2
V
V
1 = 1.5V
2 = 1.5V
A
A
Vp-p
CHG
CHG
CHG
3
4
5
CHG
V(FGFIL)
1.95
2.15
2.35
FG Output
Output ON resistance
Output leakage current
PWM Oscillator
V
(FG)
I
= 7mA
20
30
10
OL
FG
I (FG)
V
= 5.5V
O
A
L
High level output voltage
Low level output voltage
External capacitor charge current
Oscillation frequency
Amplitude
V
(PWM)
OH
2.95
1.3
-90
180
1.5
15
3.2
1.5
-70
225
1.7
3.45
1.7
V
V
V
(PWM)
OL
I
(PWM)
V
= 2V
PWM
-50
270
1.9
A
CHG
f(PWM)
C = 150pF
kHz
Vp-p
kHz
V(PWM)
Recommended operation frequency
range
f
300
OPR
CSD Oscillation Circuit
High level output voltage
Low level output voltage
Amplitude
V
(CSD)
OH
2.7
0.8
1.75
-14
8
3.0
1.0
2.0
-10
11
3.3
1.2
2.25
-6
V
V
V
(CSD)
OL
V(CSD)
Vp-p
A
A
Hz
External capacitor charge current
External capacitor discharge current
Oscillation frequency
I
I
1(CSD)
2(CSD)
V
V
1 = 2.0V
2 = 2.0V
CHG
CHG
CHG
14
CHG
f(CSD)
C = 0.068F,Design target value *
30
40
50
Phase comparing output
Output ON resistance (high level)
Output ON resistance (low level)
Phase Lock Detection Output
Output ON resistance
V
V
I
I
= -100A
= 100A
500
500
700
700
PDH
OH
OL
PDL
V
(LD)
I
= 10mA
= 5.5V
O
20
30
10
OL
LD
Output leakage current
Error Amplifier Block
Input offset voltage
I (LD)
V
A
L
V
(ER)
Design target value *
-10
-1
+10
+1
mV
A
V
IO
Input bias current
I (ER)
B
High level output voltage
Low level output voltage
DC bias level
V
(ER)
OH
I
I
= -100A
= 100A
EI+0.7
EI-1.75
-5%
EI+0.85
EI-1.6
EI+1.0
EI-1.45
5%
EI
EI
V (ER)
OL
V
V (ER)
VREG/2
V
B
* Design target value, Do not measurement.
Continued on next page.
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3
LV8111VB
Continued from preceding page.
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
Current Control Circuit
Drive gain
GDF
While phase locked
0.5
0.55
0.6
times
V
Current Limiter Circuit (pins RF and RFS)
Limiter voltage
V
0.465
0.515
0.565
RF
Under-voltage Protection
Operation voltage
VSD
8.3
0.2
8.7
9.1
0.5
V
V
Hysteresis
VSD
0.35
CLD Circuit
External capacitor charge current
Operation voltage
I
V
= 0V
-4.5
-3.0
3.5
-1.5
A
CLD
(CLD)
CLD
V
3.25
3.75
V
H
Thermal Shutdown Operation
Thermal shutdown operation
temperature
TSD
Design target value (Junction temperature)
Design target value (Junction temperature)
150
175
30
C
C
Hysteresis
TSD
CLK pin
External input frequency
High level input voltage
Low level input voltage
Input open voltage
Hysteresis
f (CLK)
I
0.1
10
VREG
1.0
kHz
V
V
V
V
V
(CLK)
2.0
IH
(CLK)
0
VREG-0.5
0.2
V
IL
(CLK)
VREG
0.4
V
IO
(CLK)
IS
0.3
0
V
High level input current
Low level input current
CSDSEL pin
I
I
(CLK)
IH
V
V
= VREG
= 0V
-10
+10
A
A
CLK
(CLK)
-110
-85
-60
IL
CLK
High level input voltage
Low level input voltage
Input open voltage
High level input current
Low level input current
S/S pin
V
V
V
(CSD)
2.0
0
VREG
1.0
V
V
IH
(CSD)
IL
(CSD)
VREG-0.5
-10
VREG
+10
V
IO
I
I
(CSD)
IH
V
V
= VREG
= 0V
0
A
A
CSDSEL
(CSD)
-110
-85
-60
IL
CSDSEL
High level input voltage
Low level input voltage
Input open voltage
Hysteresis
V
V
V
V
(SS)
2.0
VREG
1.0
V
V
IH
(SS)
(SS)
0
VREG-0.5
0.2
IL
VREG
0.4
V
IO
(SS)
IS
0.3
0
V
High level input current
Low level input current
BRSEL pin
I
I
(SS)
IH
V
V
= VREG
-10
+10
A
A
S/S
(SS)
IL
=0V
-110
-85
-60
S/S
High level input voltage
Low level input voltage
Input open voltage
High level input current
Low level input current
F/R pin
V
V
V
(BRSEL)
2.0
0
VREG
1.0
V
V
IH
(BRSEL)
(BRSEL)
IL
VREG-0.5
-10
VREG
+10
V
IO
I
I
(BRSEL)
IH
V
V
= VREG
= 0V
0
A
A
BRSEL
(BRSEL)
-110
-85
-60
IL
BRSEL
High level input voltage
Low level input voltage
Input open voltage
High level input current
Low level input current
V
V
V
(FR)
2.0
0
VREG
1.0
V
V
IH
(FR)
(FR)
IL
VREG-0.5
-10
VREG
+10
V
IO
I
I
(FR)
IH
V
V
= VREG
0
A
A
F/R
F/R
(FR)
IL
= 0V
-110
-85
-60
* Design target value, Do not measurement.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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4
LV8111VB
Package Dimensions
unit : mm
SSOP44K (275mil) Exposed Pad
CASE 940AF
ISSUE A
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5
LV8111VB
SOLDERING FOOTPRINT*
(Unit: mm)
(4.7)
0.65
0.32
NOTES:
1. The measurements are for reference only, and unable to guarantee.
2. Please take appropriate action to design the actual Exposed Die Pad and Fin portion.
3. After setting, verification on the product must be done.
(Although there are no recommended design for Exposed Die Pad and Fin portion Metal mask and shape
for Through-Hole pitch (Pitch & Via etc), checking the soldered joint condition and reliability verification of
soldered joint will be needed. Void gradient insufficient thickness of soldered joint or bond degradation
could lead IC destruction because thermal conduction to substrate becomes poor.)
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor
Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
GENERIC
MARKING DIAGRAM*
XXXXXXXXXX
YMDDD
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
may or may not be present.
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6
LV8111VB
Pd max -- Ta
2.0
1.7
1.5
1.0
0.5
0
0.95
-25
0
25
50
75 80
100
Ambient temperature, Ta -- C
Pin Assignment
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
LV8111VB
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
Top view
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7
LV8111VB
Block Diagram and Application Circuit Example
PWM
CSDSEL
CSDSEL
PD
EI
CSD
BRSEL
S/S
CSD
OSC
PWM
OSC
COUNT
LOGIC
LOGIC
VREG
BRSEL
S/S
EO
TOC
CONT
AMP
COMP
FC
PH
F/R
F/R
PEAK
HOLD
TSD
LD output
LD
LD
CLD
LD
MASK
VREG
VREG
V
CC
PLL
LVSD
V
V
1
2
CC
CC
CLK input
FG output
CLK
FG
CLK
CONTROL
CIRCUIT
VG
FG
CHARGE
PUMP
CP1
CP2
FGFIL
FILTER
OUT1
OUT2
DRIVER
CURR
LIM
HALL HYS AMP
HB
OUT3
SUB
+
−
+
−
+
−
IN3
IN1
IN1
IN2
IN2
IN3
HB
RFS
RF
GND GND2
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8
LV8111VB
Pin Function
Pin No. Pin name
Function
Equivalent circuit
1
CLK
Clock input pin (10kHz maximum)
VREG
55kΩ
10kΩ
5kΩ
1
2
LD
Phase lock detection output pin.
Goes ON during PLL-phase lock.
Open drain output.
VREG
2
3
S/S
Start/Stop input pin.
VREG
Start with low-level input.
Stop with high-level input or open input
55kΩ
10kΩ
5kΩ
3
4
5
6
VREG
5V regulator output pin.
V
CC
(the control circuit power supply)
50Ω
Connect a capacitor between this pin and GND for
stabilization.
4
BRSEL
Brake selection pin.
VREG
By low-level, short-circuit braking when the S/S pin is in a
stopped state.
(Brake for the inspection process)
55kΩ
5kΩ
5
CSDSEL
Motor constraint protection detection signal selection pin.
Select FG with low,
VREG
and LD with high or in an open state.
55kΩ
5kΩ
6
Continued on next page.
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9
LV8111VB
Continued from preceding page.
Pin No. Pin name
Function
Equivalent circuit
7
8
9
F/R
Forward / Reverse selection pin.
VREG
55kΩ
5kΩ
7
CLD
Phase lock signal mask time setting pin.
VREG
Connect a capacitor between this pin and GND.
When it is not necessary to mask, this pin must be left open.
500Ω
8
2kΩ
CSD
Pin for both the constraint protection circuit operation time
setting and the initial reset pulse setting.
VREG
Connect a capacitor between this pin and GND.
If the motor constraint protection circuit is not used,
a capacitor and a resistor must be connected in parallel
between the CSD pin and GND.
500Ω
9
10
FG
FG Schmitt output pin.
Open drain output.
VREG
10
12
PWM
Pin to set the oscillation frequency of PWM.
Connect a capacitor between this pin and GND.
VREG
200Ω
12
2kΩ
14
FC
Frequency characteristics correction pin of the current
control circuit.
VREG
Connect a capacitor between this pin and GND.
500Ω
14
110kΩ
Continued on next page.
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10
LV8111VB
Continued from preceding page.
Pin No. Pin name
Function
Equivalent circuit
15
FGFIL
FG filter pin.
VREG
When the noise of the FG signal is a problem, connect a
capacitor between this pin and GND.
15kΩ
500Ω
15
16
PH
Pin to stabilize the RF waveform.
VREG
Connect a capacitor between this pin and GND.
500Ω
16
10kΩ
17
PD
Phase comparison output pin.
VREG
The phase error is output by using the duty changes of the
pulse.
500Ω
17
18
EI
Error amplifier input pin.
VREG
500Ω
18
19
20
21
EO
Error amplifier output pin.
VREG
19
100kΩ
TOC
Torque command voltage input pin.
VREG
Normally, this pin must be connected with the EO pin.
On-duty of upper-side output Tr increases when the TOC
voltage decreases.
20
GND
Ground pin of the control circuit block.
Continued on next page.
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LV8111VB
Continued from preceding page.
Pin No. Pin name
Function
Hall element bias current pin.
Equivalent circuit
22
HB
VREG
Goes ON when the S/S pin is in a start state.
Goes OFF when the S/S pin is in a stopped state.
22
+
23
24
25
26
27
28
IN1
IN1
IN2
IN2
IN3
IN3
Hall amplifier input pin.
VREG
+
+
A high-level state of logic is recognized when IN > IN .
Reverse case is a low-level state.
+
The input amplitude of 100mVp-p or more (differential) is
desirable in the Hall inputs.
500Ω
500Ω
When the noise of the Hall signal is a problem, connect the
24 26 28
23 25 27
+
capacitors between IN and IN .
29
30
SUB
Frame ground pin. Connect this pin with the GND2 pin.
Ground pin of the output circuit block.
GND2
32
34
36
OUT3
OUT2
OUT1
Output pin.
V
CC
As for PWM, a duty control is executed on the upper side
FET.
32 34 36
38
39
RF
Source pin of output MOSFET (lower).
38
Connect low resister (Rf) between this pin and GND.
RFS
Output current detection pin.
Connect this pin to the RF pin.
VREG
5kΩ
39
40
V
V
2
1
Power supply pin for output.
Connect a capacitor between this pin and GND for
stabilization.
CC
41
42
Power supply pin for control.
CC
VG
Charge pump output pin (power supply for the upper side
FET gate).
V
CC
Connect a capacitor between this pin and V
.
CC
500Ω
43
100Ω
43
44
CP1
CP2
Pin to connect a capacitor for charge pump.
Connect a capacitor between CP1 and CP2.
42
44
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12
LV8111VB
+
3-phase Logic Truth Table (IN = “H” indicates the state where in IN > IN )
F/R = H
F/R = L
Output
OUT2
IN1
IN2
IN3
IN1
IN2
IN3
OUT1
OUT3
H
H
H
L
L
L
H
L
L
L
H
H
L
L
H
H
H
L
L
L
H
M
L
M
H
H
M
L
H
H
H
L
L
L
M
H
H
M
L
H
H
H
L
L
L
H
H
L
M
H
L
H
L
L
S/S Pin
BRSEL Pin
Input state
High or Open
Low
Input state
Mode
Stop
Start
While stopped
High or Open
Low
Free run
Short-circuit brake
CSDSEL Pin
Input state
Mode
High or Open
Low
LD standard
FG standard
LV8111VB Description
1. Speed Control Circuit
This IC can realize a high efficiency, low-jitter, a stable rotation by adopting the PLL speed control method.
This PLL circuit compares the phase difference of the edge between the CLK signal and the FG signal and controls by
using the output of error. The FG servo frequency under control becomes congruent with the CLK frequency.
f
(Servo) = f
CLK
FG
2. Output Drive Circuit
This IC adopts the direct PWM drive method to reduce power loss in the output. The driving force of the motor is
adjusted by changing the on-duty of the output transistor. The PWM switching of the output is performed by the
upper-side output transistor.
Also, this IC has a parasitic diode of the output DMOS as a regeneration route when the PWM switching is off.
But, this IC is cut down the fever than the diode regeneration by performing synchronous rectification.
3. Current Limiter Circuit
This IC limits the (peak) current at the value
I = V / Rf (V = 0.515V (typical), Rf : current detection resister).
RF RF
The current limitation operation consists of reducing the PWM output on duty to suppress the current.
To prevent malfunction of the current limitation operation when the reverse recovery current of diode is detected, the
operation has a delay (approximately 300ns). Since the current change at the motor start-up is fast when the motor coil
is lower resistance or smaller inductance, the current more than the setting value may flow during this delay time.
In this case, it is necessary to set the limiter value considering the current that increased by the delay.
4. Power Saving Circuit
This IC becomes the power saving state of decreasing the consumption current in the stop state. The bias current of the
majority circuits is cut in the power saving state. Also, 5V regulator output is output in the power saving state.
5. Reference Clock
Note that externally-applied clock signal has no noise of chattering. The input circuit has a hysteresis.
But, if noise is a problem, that noise must be excluded by inserting capacitor.
When the IC is switched to the start state if the reference clock is no input, the drive is turned off after a few rotations
if the motor constraint protection circuit is used. (Clock disconnection protection)
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13
LV8111VB
6. PWM Frequency
The PWM frequency is determined by using a capacitor C (F) connected to the PWM pin.
…
…
f
f
1 / (29500 C ) 150pF or more
PWM
PWM
1 / (32000 C ) 100pF or more, less than 150pF
The frequency is oscillated at about 225kHz when a capacitor of 150pF is connected.
The GND of a capacitor must be placed as close to the control block GND (GND pin) of the IC as possible to reduce
influence of the output.
7. Hall Effect Sensor Input Signals
The signal input of the amplitude of hysteresis of 42mV max or more is required in the Hall effect sensor inputs.
Also, an input amplitude of over 100mVp-p is desirable in the Hall effect sensor inputs in view of influence of noise.
If the output waveform (when the phase changes ) is distorted by noise, that noise must be excluded by inputting
capacitors across the inputs.
8. FG Signal
The Hall signal of IN1 is used as the FG signal in the IC. If noise is a problem, the noise of the FG signal can be
excluded by inserting a capacitor between the FGFIL pin and GND. But note that normal operation becomes
impossible if the value of the capacitor is overlarge. Also, note that the trouble of noise occurs easily when the
position of GND of the capacitor is incorrect.
9. Constraint Protection Circuit
This IC has an on-chip constraint protection circuit to protect the IC and the motor in motor constraint mode. When
the CSDSEL pin is set to the high level or open input, if the LD output remains high (unlocked statement) for a fixed
period in the start state, this circuit operates. In the low level setting case, if the FG signal is not switched for a fixed
period in the start state, this circuit operates. Also, the upper-side output transistor is turned off while the constraint
protection circuit is operating. This time is set by the capacitance of the capacitor connected to the CSD pin.
The set time (in seconds) is 102 C (F)
When a capacitor of 0.068F is connected, the protection time becomes about 7.0 seconds.
The set time must be set well in advance for the motor start-up time. When the motor is decelerated by switching the
clock frequency, this protection circuit is not operated. To release the constraint protection state, put the S/S pin into
the start again after the stop state, or turn on the power supply again after the turn off state. The CSD pin has a function
as the power-on reset pin also. If the CSD pin is connected to GND, the logic circuit goes to the reset state and the
speed cannot be controlled.
Therefore, if the constraint protection circuit is not used, a resistor of about 220k and a capacitor of about 4700pF
must be connected in parallel between the CSD pin and GND.
10. Phase Lock Signal
(1) Phase lock range
This IC has no the speed system counter. The speed error range in the phase lock state is indeterminable only by the
characteristics of the IC. ( because the accelerations of the change in FG frequency influences.)
When it is necessary to specify for the speed error as a motor, the value obtained while the motor is actually operating
must be measured. Since the speed error is likely to occur when the acceleration of FG is larger, the speed error will
be the largest when the IC goes into the lock state at motor start-up, or the unlock state by switching the clock.
(2) Phase lock signal mask function
This function can mask the short lock signal that occurred by the hunting when it goes into the lock state. Therefore,
the IC will be able to output the stable lock signal. But the mask time causes the delay of the lock signal output. The
mask time is set by the capacitance of the capacitor connected between the CLD pin and GND.
The mask time (seconds) is 1.8 C (F)
When a 0.1F capacitor is connected, the mask time becomes about 180ms.
Set the enough mask time if it must be masked completely.
When there is no need for masking, the CLD pin must be left open.
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LV8111VB
11. Power Supply Stabilization
Since this IC adopts the method of the switching drive for the application that flows large output current, the power
supply line is relatively fluctuated. Therefore, the sufficient capacitors to stabilize the power supply voltage must be
connected between the V
pin and GND as close to the pin as possible. The ground-side of the capacitors must be
CC
connected to the GND2 pin that is GND of the output circuit block. If it is impossible to connect a capacitor
(electrolytic capacitor) near the pin, the ceramic capacitor of about 0.1F must be connected as close to the pin as
possible.
Since the power supply line is more fluctuated when the diodes are inserted in the power supply line to prevent IC
destruction due to the reverse connection of the power supply, choose even larger capacitors.
12. VREG Stabilization
To stabilize the VREG voltage that is the power supply of the control circuit, connect a capacitor of 0.1F or more.
The ground-side of the capacitor must be connected as close to the control block GND (GND pin) of the IC as
possible.
13. Error Amplifier
External components of the error amplifier block must be placed as close to the IC as possible to reduce influence of
noise.
Also, these components must be placed as far as possible from the motor.
14. Metal of IC’s Backside
The heat radiation can be efficiently diffused by soldering the metal of IC’s backside to the printed circuit board.
15. SDCC (Speed Detection Current Control)
The SDCC function controls the current limiter value by sensing the motor speed.
When the rotation speed exceeds 95% of the target speed, this function decreases the current limiter value to 75% and
reduces the acceleration of the motor. Therefore, it stabilizes the phase lock pull-in and improves the variance of the
motor start-up time.
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
2000 / Tape & Reel
SSOP44K (275mil) EP
(Pb-Free / Halogen Free)
LV8111VB-AH
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