LC87F6D64AU-QFP-E [ONSEMI]
8-bit Microcontroller with 64K-byte Flash ROM and 2048-byte RAM, 60-FTRAY;
| 型号： | LC87F6D64AU-QFP-E |
| 厂家： | 
ONSEMI |
| 描述： | 8-bit Microcontroller with 64K-byte Flash ROM and 2048-byte RAM, 60-FTRAY 时钟 微控制器 外围集成电路 |
| 文件： | 总19页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA1007
LC87F6D64A
CMOS IC
FROM 64K byte, RAM 2048 byte on-chip
http://onsemi.com
8-bit 1-chip Microcontroller
Overview
The LC87F6D64A is 8-bit microcomputer with the following on-chip functional blocks:
• CPU: operable at a minimum bus cycle time of 100ns
• 64K-byte flash ROM (re-writeable on board/On-chip debugger)
• On-chip RAM: 2048 byte
• VFD automatic display controller/driver
• 16-bit timer/counter (can be divided into two 8-bit timers)
• two 8-bit timer with prescaler
• timer for use as date/time clock
• Day-Minute-Second Counter (DMSC)
• System clock divider function
• Synchronous serial I/O port (with automatic block transmit /receive function)
• Asynchronous/synchronous serial I/O port
• Remote control receive function
• 8-channel×8-bit AD converter
• 14-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Features
Flash ROM
• Single 5V power supply, writeable on-board.
• Block erase in 128 byte units
• 65536 × 8 bits
RAM
• 2048 × 9 bits
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
30508HKIM 20071127-S00004 No.A1007-1/19
May, 2013
Ver.1.21
LC87F6D64A
Minimum Bus Cycle Time
• 100ns (10MHz) V =3.0 to 5.5V
DD
DD
• 150ns (4MHz)
V
=2.5 to 5.5V
Note: The bus cycle time indicates ROM read time.
Minimum Instruction Cycle Time (tCYC)
• 300ns (10MHz) V =3.0 to 5.5V
DD
• 750ns (4MHz)
V
=2.5 to 5.5V
DD
Ports
• Input/output ports
Data direction programmable for each bit individually: 10 (P1n, P7n)
Data direction programmable in nibble units: 8 (P0n)
(When N-channel open drain output is selected, data can be input in bit units.)
• VFD output ports
Large current outputs for digits:
Large current outputs for digits/segments:
Digit/segment outputs:
Segment outputs:
9 (S0/T0 to S8/T8)
7 (S9/T9 to S15/T15)
8 (S16 to S23)
30 (S24 to S53)
• Oscillator pins:
• Reset pin:
2 (CF1/XT1, CF2/XT2)
1 ( )
RES
• Power supply:
• VFD power supply:
4 (V 1, V 1 to V 3)
1 (VP)
SS DD DD
VFD Automatic Display Controller
• Programmable segment/digit output pattern
Output can be switched between digit/segment waveform output
(pins 9 to 23 can be used for output of digit waveforms).
parallel-drive available for large current VFD.
• 16-step dimmer function available
Timers
• Timer 0: 16-bit timer/counter with capture register
Mode 0: 2 channel 8-bit timer with programmable 8-bit prescaler and 8-bit capture register
Mode 1: 8-bit timer with 8-bit programmable prescaler and 8-bit capture register
+ 8-bit counter with 8-bit capture register
Mode 2: 16-bit timer with 8-bit programmable prescaler and 16-bit capture register
Mode 3: 16-bit counter with 16-bit capture register
• Timer 4: 8-bit timer with 6-bit prescaler
• Timer 5: 8-bit timer with 6-bit prescaler
• Base Timer
1) The clock signal can be selected from any of the following.
Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0
2) Interrupts can be selected to occur at one of five different times.
• Day and time counter
1) Using with a base timer, it can be used as 65000 day + minute + second counter.
SIO
• SIO 0: 8-bit synchronous serial interface
1) LSB first /MSB first function available
2) Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 tCYC)
3) Consecutive automatic data communication
(1 to 256 bits (communication available for each bit) (stop and reopening available for each byte))
• SIO 1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
No.A1007-2/19
LC87F6D64A
AD Converter: 8 bits × 8 channels
Remote Control Receiver Circuit (sharing pins with P70/INT0/RMIN)
• Noise rejection function
(Units of noise rejection filter: about 120μs, when selecting a 32.768kHz crystal oscillator as a clock.)
• Supporting reception formats with a guide-pulse of half-clock/clock/none.
• Determines a end of reception by detecting a no-signal periods (No carrier).
(Supports same reception format with a different bit length.)
• X’tal HOLD mode release function
Watchdog Timer
• The watching timer period is set using an external RC.
• Watchdog timer can produce interrupt, system reset.
Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
Interrupts: 14 sources, 10 vector interrupts
• Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling,
an equal or lower priority interrupt request is refused.
• If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.
In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
1
Vector
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Selectable Level
X or L
Interrupt Signal
INT0
INT1
2
X or L
3
H or L
INT2/T0L/remote control receiver
INT3/Base timer 0/1
T0H
4
H or L
5
H or L
6
H or L
7
H or L
SIO0
8
H or L
SIO1
9
H or L
ADC
10
H or L
Port0/T4/T5
• Priority Level: X>H>L
• For equal priority levels, vector with lowest address takes precedence.
Subroutine Stack Levels: 1024 levels maximum (Stack is located in RAM.)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
• 24 bits × 16 bits
• 16 bits ÷ 8 bits
• 24 bits ÷ 16 bits
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
Oscillation Circuits
• On-chip RC oscillation circuit for system clock use.
• On-chip CF oscillation circuit* for system clock use. (Rf built in)
• On-chip Crystal oscillation circuit* low speed system clock use. (Rf built in)
• Frequency variable RC oscillation circuit (internal) for system clock.
1) Adjustable in 4% (typ) step from a selected center frequency.
2) Measures oscillation clock using a input signal from XT1 as a reference.
* The CF oscillation terminal and the crystal oscillation terminal cannot be used at the same time because of
commonness.
No.A1007-3/19
LC87F6D64A
System Clock Divider Function
• Able to reduce current consumption
Available minimum instruction cycle time: 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, 76.8μs.
(Using 10MHz main clock)
Standby Function
• HALT mode
HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits still operate
but VFD display and some serial transfer operations stop.
1) Oscillation circuits are not stopped automatically.
2) Release occurs on system reset or by interrupt.
• HOLD mode
HOLD mode is used to reduce power consumption. Both program execution and peripheral circuits are stopped.
1) The CF, RC, X’tal and frequency variable RC oscillators automatically stop operation.
2) Release occurs on any of the following conditions.
(1) input to the reset pin goes “Low”
(2) a specified level is input to at least one of INT0, INT1, INT2
(3) an interrupt condition arises at port 0
• X’tal HOLD mode.
X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base-timer are stopped.
1) The CF, RC, frequency variable RC oscillation circuits stop automatically.
2) Crystal oscillator is maintained in its state at HOLD mode inception.
3) Release occurs on any of the following conditions.
(1) input to the reset pin goes “Low”
(2) Setting at least one of the INT0, INT1 and INT2 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
(5) Having an interrupt source established in the remote control receiver circuit
On-chip Debugger
• Supports software debugging with the IC mounted on the target board.
Package Form
• QFP80(14×14): Lead-free type
Development Tools
• On-chip debugger: TCB87- type-B + LC87F6D64A
No.A1007-4/19
LC87F6D64A
Package Dimensions
unit : mm (typ)
3255
17.2
14.0
60
41
61
40
21
80
20
1
0.25
0.15
0.65
(0.83)
QFP80(14X14)
Pin Assignment
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
S38
S39
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
S17
S16
V
3
DD
V
VP1
2
DD
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S15/T15
S14/T14
S13/T13
S12/T12
S11/T11
S10/T10
S9/T9
S8/T8
S7/T7
S6/T6
S5/T5
LC87F6D64A
S4/T4
S3/T3
S2/T2
S1/T1
P10/SO0
P11/SI0/SB0
P12/SCK0
S0/T0
Top view
QFP80(14×14) “Lead-free Type”
No.A1007-5/19
LC87F6D64A
System Block Diagram
Interrupt control
Standby control
IR
PLA
Flash ROM
CF
X’tal
VMRC
RC
PC
SIO0
SIO1
Bus interface
Port 0
ACC
B register
Port 1
ADC
C register
Timer 0
ALU
Remote control
receiver circuit
Base timer
VFD Controller
Timer 4
DMSC
PSW
RAR
INT0 to 3
Noise Rejection Filter
Timer 5
RAM
Stack pointer
Watchdog timer
On-chip debugger
No.A1007-6/19
LC87F6D64A
Pin Description
Pin name
I/O
Function
Option
No
V
1
-
-
• Power supply (-)
• Power supply (+)
SS
V
V
V
1
2
3
No
DD
DD
DD
VP
-
• VFD Power supply (-)
• 8bit input/output port
No
PORT0
I/O
Yes
• Data direction programmable in nibble units
• Use of pull-up resistor can be specified in nibble units
• Input for HOLD release
P00 to P07
• Input for port 0 interrupt
• Other functions
P04: clock output (system clock/can selected from sub clock)
On-chip debugger pins: DBGP0 to DBGP2 (P05 to P07)
• 8bit input/output port
PORT1
I/O
Yes
• Data direction programmable for each bit
• Use of pull-up resistor can be specified for each bit
• Other pin functions
P10 to P17
P10: SIO0 data output
P11: SIO0 data input/bus input/output
P12: SIO0 clock input/output
P13: SIO1 data output
P14: SIO1 data input/bus input/output
P15: SIO1 clock input/output
P16: INT2
P17: INT3/Buzzer output
The following types of interrupt detection are possible:
Rising/
Rising
Falling
H level
L level
Falling
enable
enable
INT2
INT3
enable
enable
enable
enable
disable
disable
disable
disable
PORT7
• 2bit input/output port
• Data direction can be specified for each bit
P70 to P71
• Use of pull-up resistor can be specified for each bit
• Other functions
P70: INT0 input/HOLD release input/Timer 0L capture input/
output for watchdog timer/Remote control receiver input
P71: INT1 input/HOLD release input/Timer 0H capture input
The following types of interrupt detection are possible:
Rising/
Rising
Falling
H level
L level
Falling
disable
disable
INT0
INT1
enable
enable
enable
enable
enable
enable
enable
enable
S0/T0 to S8/T8
S9/T9 to S15/T15
S16 to S53
RES
O
O
O
I
• Large current output for VFD display controller digit (can be used for segment)
• Large current output for VFD display controller segment/digit
• Output for VFD display controller segment
No
No
No
No
No
Reset terminal
CF1/XT1
I
<ceramic oscillator selected>
• Input terminal for ceramic oscillator
< crystal oscillator selected>
• Input for 32.768kHz crystal oscillation
When not in use, connect to V 1.
DD
CF2/XT2
O
<ceramic oscillator selected>
No
• Output terminal for ceramic oscillator
< crystal oscillator selected>
• Output for 32.768kHz crystal oscillation
When not in use, set to oscillation mode and leave open circuit.
No.A1007-7/19
LC87F6D64A
Port Output Types
Output configuration and pull-up/pull-down resistor options are shown in the following table.
Input/output is possible even when port is set to output mode.
Option Selected in
Terminal
Options
Output Format
Pull-up Resistor
Pull-down Resistor
Units of
each bit
P00 to P07
1
2
CMOS
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
-
-
(Note 1)
Nch-open drain
CMOS
-
P10 to P17
each bit
1
-
2
Nch-open drain
Nch-open drain
CMOS
-
P70
P71
-
-
-
None
None
None
-
-
S0/T0 to S15/T15
S16 to S53
High voltage Pch-open drain
Fixed
Note 1: Programmable pull-up resisters of Port 0 can be attached in nibble units (P00 to P03, P04 to P07).
* Note: Connect as follows to reduce noise on V
and increase the back-up time.
DD
V
1 must be connected together and grounded.
SS
LSI
V
1
DD
Power
supply
Back-up capacitors
V
V
2
3
DD
VFD
powers
DD
V
1
SS
No.A1007-8/19
LC87F6D64A
Absolute Maximum Ratings at Ta = 25°C, V 1 = 0V
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
1, V 2, V 3
DD
Conditions
V
[V]
min
-0.3
unit
DD
Supply voltage
Input voltage
V
max
V
V
1=V 2=V 3
+6.5
+0.3
+0.3
DD
DD
DD
DD DD DD
V (1)
I
CF1/XT1,
VP
RES
-0.3
-45
V
V
DD
V (2)
I
V
V
DD
DD
Output voltage
V
(1)
S0/T0 to S15/T15
S16 to S53
O
V
-45
DD
V
V
V
+0.3
+0.3
+0.3
DD
DD
DD
V
V
(2)
(1)
CF2/XT2
-0.3
-0.3
O
Input/Output
voltage
Ports 0, 1, 7
IO
Peak output
current
IOPH(1)
Ports 0, 1
• CMOS output selected
• Current at each pin
Current at each pin
-10
IOPH(2)
IOPH(3)
IOPH(4)
IOMH(1)
Port 71
-5
-30
-15
S0/T0 to S15/T15
S16 to S53
Ports 0, 1
Current at each pin
Current at each pin
Average
• CMOS output selected
• Current at each pin
Current at each pin
-7.5
output current
IOMH(2)
IOMH(3)
IOMH(4)
ΣIOAH(1)
ΣIOAH(2)
ΣIOAH(3)
ΣIOAH(4)
ΣIOAH(5)
ΣIOAH(6)
ΣIOAH(7)
Port 71
-3
-15
-10
-30
-30
-30
-5
S0/T0 to S15/T15
S16 to S53
Port 0
Current at each pin
Current at each pin
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total output
current
Port 1
Ports 0, 1
Port 71
S0/T0 to S15/T15
S16 to S33
-60
-60
mA
S0/T0 to S15/T15
S16 to S33
-60
ΣIOAH(8)
ΣIOAH(9)
ΣIOAH(10)
ΣIOAH(11)
IOPL(1)
S34 to S39
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Current at each pin
Current at each pin
Current at each pin
Current at each pin
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Ta=-40 to +85°C
-60
-60
-60
-60
S40 to S47
S48 to S53
S34 to S53
Ports 0, 1
Port 7
Peak output
current
20
10
15
7.5
50
50
20
80
IOPL(2)
Total output
current
IPML(1)
Ports 0, 1
Port 7
IOML(2)
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
Pd max
Total output
current
Port 0
Port 1
Port 7
Ports 0, 1, 7
QFP80(14×14)
Maximum power
dissipation
Operating
temperature
range
mW
Topr
Tstg
-40
-55
+85
°C
Storage
temperature
range
+125
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A1007-9/19
LC87F6D64A
Allowable Operating Conditions at Ta = -40°C to +85°C, V 1 = 0V
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
1=V 2=V 3
DD
Conditions
V
[V]
min
3.0
unit
DD
Operating
supply voltage
range
V
V
(1)
V
0.300μs≤tCYC≤200μs
0.735μs≤tCYC≤200μs
5.5
DD
DD
DD
(2)
DD
2.5
2.0
5.5
(Note 2-1)
Hold voltage
VHD
VP
V
1
RAM and the register data are
kept in HOLD mode.
DD
5.5
Pull-down
supply voltage
Input high
voltage
VP
-35
DD
V
V
DD
V
V
(1)
Ports 0, 1
Output disable
Output disable
0.3V
IH
IH
IH
2.5 to 5.5
DD
+0.7
V
(2)
Port 70
2.5 to 5.5
2.5 to 5.5
0.9V
DD
V
V
DD
Watchdog timer
V
V
(3)
XT1/CF1,
RES
0.75V
DD
DD
Input low
voltage
(1)
Ports 0, 1
Port 71
Output disable
Output disable
IL
0.1V
DD
2.5 to 5.5
V
SS
Port 70
+0.4
port input/interrupt
Port 70
V
V
(2)
(3)
0.8V
DD
IL
2.5 to 5.5
V
V
SS
Watchdog timer
-1.0
XT1/CF1,
RES
2.5 to 5.5
3.0 to 5.5
2.5 to 5.5
3.0 to 5.5
0.25V
DD
IL
SS
Operation
cycle time
tCYC
0.300
0.735
0.1
200
μs
200
10
External
FEXCF(1)
CF1
• CF2 open circuit
system clock
frequency
• system clock divider set to 1/1
• external clock DUTY=50 5%
• CF2 open circuit
2.5 to 5.5
3.0 to 5.5
2.5 to 5.5
0.1
0.2
0.2
4
20
8
MHz
• system clock divider set to 1/2
• external clock DUTY=50 5%
• 10MHz ceramic resonator
oscillation
Oscillation
stabilizing
time period
(Note 2-2)
FmCF(1)
FmCF(2)
CF1, CF2
CF1, CF2
3.0 to 5.5
2.5 to 5.5
10
• Refer to figure 1
• 4MHz ceramic resonator
oscillation
4
MHz
• Refer to figure 1
FmRC
RC oscillation
2.5 to 5.5
2.5 to 5.5
0.3
1.0
4
2.0
FmVMRC
Frequency variable RC oscillation
circuit
FsX’tal
XT1, XT2
32.768kHz crystal resonator
oscillation
2.5 to 5.5
32.768
kHz
Refer to figure 2
Note 2-1: Re-writeable on board V ≥4.5V.
DD
Note 2-2: The oscillation constant is shown in table 1 and table 2.
The CF oscillation terminal and the crystal oscillation terminal cannot be used at the same time
because of commonness.
No.A1007-10/19
LC87F6D64A
Electrical Characteristics at Ta = -40°C to +85°C, V 1 = 0V
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
DD
Input high current
I
(1)
Ports 0, 1, 7
• Output disable
• Pull-up resister OFF.
• V =V
IH
2.5 to 5.5
1
IN DD
(including OFF state leak current
of the output Tr.)
I
I
I
(2)
(3)
V
V
=V
RES
2.5 to 5.5
2.5 to 5.5
1
1
IH
IN DD
CF1/XT1
Ports 0, 1, 7
=V
IH
IN DD
μA
Input low current
(1)
• Output disable
IL
• Pull-up resister OFF.
• V =V
IN SS
2.5 to 5.5
-1
(including OFF state leak current
of the output Tr.)
I
I
(2)
(3)
V
V
I
=V
RES
2.5 to 5.5
2.5 to 5.5
4.5 to 5.5
3.0 to 5.5
2.5 to 5.5
2.5 to 5.5
4.5 to 5.5
3.0 to 5.5
-1
-1
-1
-1
IL
IN SS
CF1/XT1
=V
IL
IN SS
Output high
voltage
V
V
V
V
V
V
V
(1)
Port 0: CMOS
output option
Ports 1
=-1.0mA
V
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
DD
(2)
(3)
(4)
(5)
(6)
(7)
I
I
I
I
I
=-0.5mA
=-0.1mA
=-0.4mA
=-20.0mA
=-10.0mA
V
DD
V
-0.5
-1
DD
V
Port 71
DD
S0/T0 to S15/T15
V
V
-1.8
DD
-1.8
DD
• I =-1.0mA
OH
• I
at any single pin is
2.5 to 5.5
V
-1
OH
DD
not over 1mA.
V
V
V
V
(8)
S16 to S53
I
=-5.0mA
OH
4.5 to 5.5
3.0 to 5.5
V
V
-1.8
-1.8
OH
OH
OH
DD
(9)
I
=-2.5mA
OH
DD
(10)
• I =-1.0mA
OH
• I
at any single pin is
2.5 to 5.5
V
-1
OH
DD
not over 1mA.
=10mA
OL
Output low
voltage
V
V
V
V
(1)
(2)
(3)
(4)
Ports 0, 1
I
I
I
I
4.5 to 5.5
3.0 to 5.5
2.5 to 5.5
1.5
1.5
0.4
OL
OL
OL
OL
=5mA
OL
OL
OL
=1.6mA
=1mA
Port 7
2.5 to 5.5
0.4
Pull-up resistor
Rpu
Ports 0, 1, 7
V
=0.9V
4.5 to 5.5
2.5 to 4.5
15
25
40
70
OH
DD
kΩ
μA
70
150
Output off-leak
current
IOFF(1)
IOFF(2)
Rpd
S0/T0 to S15/T15,
S16 to S53
• Output P-ch Tr. OFF
• V =V
2.5 to 5.5
2.5 to 5.5
-1
OUT SS
• Output P-ch Tr. OFF
• V =V -40V
-30
OUT DD
• Output P-ch Tr. OFF
• V =3V
Pull-down resistor
• S0/T0 to S15/T15
• S16 to S53
5.0
60
100
200
kΩ
OUT
• Vp=-30V
Hysteresis
voltage
VHYS(1)
CP
• Ports 0, 1, 7
2.5 to 5.5
0.1V
V
DD
10
•
RES
Pin capacitance
All pins
• f=1MHz
• All other terminals connected
2.5 to 5.5
pF
to V
.
SS
• Ta=25°C
No.A1007-11/19
LC87F6D64A
Serial I/O Characteristics at Ta = -40°C to +85°C, V 1 = 0V
SS
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Pin/
Parameter
Frequency
Symbol
tSCK(1)
Conditions
Remarks
V
[V]
min
typ
max
unit
DD
SCK0(P12)
See Fig. 6.
2
1
1
Low level
tSCKL(1)
tSCKH(1)
tSCKHA(1)
pulse width
High level
pulse width
2.5 to 5.5
tCYC
• Continuous data
transmission/reception mode
• See Fig. 6.
4
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
• See Fig. 6.
4/3
Low level
tSCKL(2)
tSCKH(2)
tSCKHA(2)
1/2
1/2
pulse width
High level
pulse width
tSCK
tCYC
2.5 to 5.5
• Continuous data
tSCKH(2)
+(10/3)
tCYC
transmission/reception mode
• CMOS output selected
• See Fig. 6.
tSCKH(2)
+2tCYC
Data setup time
Data hold time
tsDI(1)
thDI(1)
tdD0(1)
tdD0(2)
tdD0(3)
SB0(P11),
SI0(P11)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 6.
2.5 to 5.5
2.5 to 5.5
2.5 to 5.5
2.5 to 5.5
0.03
0.03
Output delay
time
SO0(P10),
SB0(P11)
• Continuous data
(1/3)tCYC
+0.05
transmission/reception mode
• (Note 4-1-3)
µs
• Synchronous 8-bit mode
• (Note 4-1-3)
1tCYC
+0.05
(Note 4-1-3)
(1/3)tCYC
+0.05
2.5 to 5.5
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A1007-12/19
LC87F6D64A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Pin/
Parameter
Frequency
Symbol
tSCK(3)
Conditions
See Fig. 6.
Remarks
V
[V]
min
typ
max
unit
DD
SCK1(P15)
2
1
1
2
Low level
tSCKL(3)
tSCKH(3)
tSCK(4)
tSCKL(4)
tSCKH(4)
tsDI(2)
2.5 to 5.5
pulse width
High level
pulse width
Frequency
tCYC
SCK1(P15)
• CMOS output selected
• See Fig. 6.
Low level
pulse width
2.5 to 5.5
1/2
1/2
tSCK
High level
pulse width
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with
respect to rising edge of
SIOCLK.
2.5 to 5.5
2.5 to 5.5
0.03
0.03
• See Fig. 6.
Data hold time
thDI(2)
tdD0(4)
Output delay time
SO1(P13),
SB1(P14)
• Must be specified with
respect to falling edge of
SIOCLK.
μs
• Must be specified as the
time to the beginning of
output state change in
open drain output mode.
• See Fig. 6.
(1/3)tCYC
+0.05
2.5 to 5.5
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Pulse Input Conditions at Ta = -40°C to +85°C, V 1 = 0V
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
tCYC
μs
DD
High/low level
pulse width
tPIH(1)
tPIL(1)
INT0(P70),
• Interrupt acceptable
INT1(P71),
• Events to timer 0, 1 can be input.
2.5 to 5.5
2.5 to 5.5
2.5 to 5.5
1
2
INT2(P16)
tPIH(2)
tPIL(2)
INT3(P17)
• Interrupt acceptable
(Noise rejection ratio
set to 1/1.)
• Events to timer 0 can be input.
tPIH(3)
tPIL(3)
INT3(P17)
• Interrupt acceptable
(Noise rejection ratio
set to 1/32.)
INT3(P17)
• Events to timer 0 can be input.
64
tPIH(4)
tPIL(4)
• Interrupt acceptable
(Noise rejection ratio
set to 1/128.)
RES
• Events to timer 0 can be input.
2.5 to 5.5
2.5 to 5.5
256
200
tPIL(5)
Reset possible
No.A1007-13/19
LC87F6D64A
AD Converter Characteristics at Ta = -40°C to +85°C, V 1 = 0V
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
bit
DD
Resolution
N
AN0(P00) to
AN7(P07)
3.0 to 5.5
3.0 to 5.5
8
Absolute
ET
(Note 6-1)
1.5
LSB
precision
Conversion time
tCAD
AD conversion time=32×tCYC
(ADCR2=0)
15.62
(tCYC=
0.488μs)
23.52
97.92
(tCYC=
3.06μs)
97.92
4.5 to 5.5
3.0 to 5.5
4.5 to 5.5
(Note 6-2)
(tCYC=
0.735μs)
18.82
(tCYC=
3.06μs)
97.92
μs
AD conversion time=64×tCYC
(ADCR2=1)
(tCYC=
0.294μs)
47.04
(tCYC=
1.53μs)
97.92
(Note 6-2)
3.0 to 5.5
3.0 to 5.5
(tCYC=
0.735μs)
(tCYC=
1.53μs)
Analog input
voltage range
Analog port
input current
VAIN
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
3.0 to 5.5
3.0 to 5.5
1
μA
VAIN=V
SS
-1
Note 6-1: Absolute precision not including quantizing error ( 1/2 LSB).
Note 6-2: Conversion time means time from executing AD conversion instruction to loading complete digital value to
register.
Consumption Current Characteristics at Ta = -40°C to +85°C, V 1 = 0V
SS
Specification
typ max
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
unit
DD
Current
IDDOP(1)
V
1
• FmCF=10Hz for ceramic resonator
oscillation
DD
4.5 to 5.5
3.0 to 4.5
8.0
24
dissipation
during basic
operation
=V
=V
2
3
DD
DD
• System clock: 10MHz
• Internal RC oscillation stopped.
• 1/1 frequency division ratio
• CF1=15MHz for external clock
• System clock: CF1 oscillation
• Internal RC oscillation stopped.
• 1/2 frequency division ratio
• FmCF=4MHz for ceramic resonator
oscillation
6.1
19
(Note 7-1)
IDDOP(2)
IDDOP(3)
4.5 to 5.5
3.0 to 4.5
4.5 to 5.5
10.5
9.5
32
28
mA
3.8
9.5
• System clock: 4MHz
• Internal RC oscillation stopped.
• 1/1 frequency division ratio
• FmCF=0Hz (No oscillation)
• System clock: RC oscillation
• Divider set to 1/2
3.0 to 4.5
3.1
7.8
IDDOP(4)
IDDOP(5)
4.5 to 5.5
2.5 to 4.5
0.72
0.53
3
2
• FsX’tal=32.768kHz for crystal oscillation
• System clock: 32.768KHz
• Internal RC oscillation stopped.
• 1/2 frequency division ratio
4.5 to 5.5
2.5 to 4.5
39
25
220
150
μA
Note 7-1: The currents of the output transistors and the pull-up MOS transistors are ignored.
Continued on next page.
No.A1007-14/19
LC87F6D64A
Continued from preceding page.
Specification
typ max
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
unit
DD
Current
IDDHALT(1)
V
1
HALT mode
DD
dissipation
HALT mode
(Note 7-1)
=V
=V
2
3
• FmCF=10MHz for Ceramic resonator
oscillation
4.5 to 5.5
3.0 to 4.5
3.0
9
DD
DD
• System clock : 10MHz
• Internal RC oscillation stopped.
• Divider: 1/1
2.1
6.3
IDDHALT(2)
IDDHALT(3)
HALT mode
4.5 to 5.5
3.0 to 4.5
4.2
2.5
12.5
7.8
• CF1=15MHz for external clock
• System clock : CF1 oscillation
• Internal RC oscillation stopped.
• Divider 1/2
mA
HALT mode
• FmCF=4MHz for Ceramic resonator
oscillation
4.5 to 5.5
2.5 to 4.5
1.4
1.0
3.5
2.5
• System clock : 4MHz
• Internal RC oscillation stopped.
• Divider: 1/1
IDDHALT(4)
IDDHALT(5)
HALT mode
4.5 to 5.5
2.5 to 4.5
4.5 to 5.5
420
280
24
1600
1100
80
• FmCF=0Hz (When oscillation stops.)
• System clock : RC oscillation
• Divider: 1/2
HALT mode
• FsX’tal=32.768kHz for crystal oscillation
• Internal RC oscillation stopped.
• System clock : 32.768kHz
• Divider: 1/2
2.5 to 4.5
14
60
μA
Current
IDDHOLD(1)
IDDHOLD(2)
V
V
1
HOLD mode
DD
4.5 to 5.5
2.5 to 4.5
0.10
0.02
20
15
dissipation
HOLD mode
Current
• CF1=V or open circuit
DD
(when using external clock)
1
Date/time clock HOLD mode
DD
4.5 to 5.5
2.5 to 4.5
21
11
65
50
dissipation
Date/time
clock
• CF1=V or open circuit
DD
(when using external clock)
• FsX’tal=32.768kHz for crystal oscillation
HOLD mode
Note 7-1: The currents of the output transistors and the pull-up MOS transistors are ignored.
F-ROM Programming Characteristics at Ta = +10°C to +55°C, V 1 = 0V
SS
Specification
Pin/
Parameter
Symbol
Conditions
Remarks
V
[V]
min
typ
max
10
unit
DD
On-board writing
current
IDDFW(1)
V
1
• The current dissipation of the
microcomputer is excluded.
• Erase time
DD
4.5 to 5.5
4.5 to 5.5
5
mA
Writing time
tFW(1)
tFW(2)
20
40
30
60
ms
• Writing time
μs
No.A1007-15/19
LC87F6D64A
Characteristics of a Sample Main System Clock Oscillation Circuit
The characteristics in the table bellow is based on the following conditions:
1. Use the standard evaluation board Our company has provided.
2. Use the peripheral parts with indicated value externally.
3. The peripheral parts value is a recommended value of oscillator manufacturer.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Oscillation
Operating
Circuit Parameters
Stabilizing Time
Supply
Frequency
Manufacturer
Oscillator
Notes
Voltage Range
[V]
C1
C2
Rd1
typ
max
[ms]
[pF]
10
[pF]
[Ω]
1k
[ms]
CSTCE10M0G52-R0
CSTLS10M0G53-B0
CSTCR4M00G53-R0
CSTLS4M00G53-B0
10
15
15
15
2.8 to 5.5
3.0 to 5.5
2.3 to 5.5
2.3 to 5.5
0.029
0.028
0.034
0.030
10MHz
4MHz
MURATA
MURATA
15
1k
15
2.2k
2.2k
15
The oscillation stabilizing time is a period until the oscillation becomes stable after V
minimum operating voltage. (Refer to Figure 4)
becomes higher than
DD
Characteristics of a Sample Subsystem Clock Oscillator Circuit
The characteristics in the table bellow is based on the following conditions:
1. Use the standard evaluation board Our company has provided.
2. Use the peripheral parts with indicated value externally.
3. The peripheral parts value is a recommended value of oscillator manufacturer
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Oscillation
Operating
Supply Voltage
Range
Circuit Parameters
Stabilizing Time
Frequency
Manufacturer
Oscillator
Notes
C3
C4
Rf
Rd2
typ
[s]
max
[s]
[V]
[pF]
[pF]
[Ω]
[Ω]
The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which
starts the sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure 4)
Notes: Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the
oscillation pins as possible with the shortest possible pattern length.
CF1
XT1
CF2
XT2
Rf1
CF
Rf2
Rd1
Rd2
C1
C3
C2
C4
X’tal
Figure 1 Ceramic Oscillation Circuit
Figure 2 Crystal Oscillation Circuit
0.5V
DD
Figure 3 AC Timing Measurement Point
No.A1007-16/19
LC87F6D64A
V
V
DD
DD
limit
Power supply
RES
0V
Reset time
Internal RC
oscillation
tmsCF
CF1, CF2
XT1, XT2
tmsX’tal
Operating
mode
Unfixed
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
Witout HOLD
release signal
HOLD release
signal
HOLD reset signal VALID
Internal RC
oscillation
tmsCF
CF1,CF2
tmsX’tal
XT1, XT2
HOLD
HALT
Operating mode
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Time
No.A1007-17/19
LC87F6D64A
V
DD
Note:
Set C
R
RES
, R
RES RES
values such that reset time
exceeds 200μs.
RES
C
RES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM transmission
period (only SIO0)
tSCK
tSCKL
tSCKH
thDI
SIOCLK:
tsDI
DATAIN:
tdDO
DATAOUT:
Data RAM transmission
period (only SIO0)
tSCKL
tSCKHA
SIOCLK:
DATAIN:
tsDI
thDI
tdDO
DATAOUT:
Figure 6 Serial I/O Waveform
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A1007-18/19
LC87F6D64A
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application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
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No.A1007-19/19
PS
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