LC87F74C8A [SANYO]
8-bit 1-chip Microcontroller; 8位单芯片微控制器
| 型号： | LC87F74C8A |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 8-bit 1-chip Microcontroller |
| 文件： | 总21页 (文件大小：576K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN7825
CMOS IC
FROM 128K-byte, RAM 4096-byte on chip
LC87F74C8A
8-bit 1-chip Microcontroller
Overview
The LC87F74C8A is an 8-bit single chip microcontroller with the following on-chip functional blocks :
• CPU : operable at a minimum bus cycle time of 100ns
• 128K-bytes flash ROM (on-board rewritable)
• On-chip RAM : 4096-bytes
• LCD controller/driver
• Two high performance 16-bit timer/counters (can be divided into 8-bit units)
• 16-bit timer/PWM (can be divided into two 8-bit timers)
• Four 8-bit timer with prescalers
• Timer for use as date/time clock
• Synchronous serial I/O port (with automatic block transmit/receive function)
• Asynchronous/synchronous serial I/O port
• 15-channel × 8-bit AD converter
• High-speed clock counter
• System clock divider
• Small signal detector
• 20-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Features
■Flash ROM
• Single 5V power supply, on-board writable
• Block erase in 128-byte units
• 131072 × 8-bits (LC87F74C8A)
■Random access memory (RAM)
• 4096 × 9-bits (LC87F74C8A)
■Minimum bus cycle time
• 100ns (10MHz)
Note : The bus cycle time indicates ROM read time.
Ver.1.02
82202
83004 JO IM No.7825-1/21
LC87F74C8A
■Minimum instruction cycle time
• 300ns (10MHz)
■Ports
• Input/output ports
Data direction programmable for each bit individually : 26 (P1n, P30 to P35, P70 to P73, P8n)
Data direction programmable in nibble units
: 8 (P0n)
(When N-channel open drain output is selected, data can be input in bit units.)
• Input ports
• LCD ports
Segment output
Common output
Bias terminals for LCD driver
Other functions
Input/output ports
Input ports
: 2 (XT1, XT2)
: 48 (S00 to S47)
: 4 (COM0 to COM3)
3 (V1 to V3)
: 48 (PAn, PBn, PDn, PEn, PFn)
: 7 (PLn)
• Oscillator pins
• Reset pin
• Power supply
: 2 (CF1, CF2)
: 1 (
)
RES
: 6 (V 1 to 3, V 1 to 3)
SS DD
■LCD controller
• Seven display modes are available (static, 1/2, 1/3, 1/4 duty × 1/2, 1/3 bias)
• Segment output and common output can be switched to general purpose input/output ports.
■Small signal detection (MIC signals etc)
• Counts pulses with the level which is greater than a preset value
• 2-bit counter
■Timer
• Timer 0 : 16-bit timer/counter with capture register
Mode 0 : 2-channel 8-bit timer with programmable 8-bit prescaler and 8-bit capture register
Mode 1 : 8-bit timer with 8-bit programmable prescaler and 8-bit capture register + 8-bit
Counter with 8-bit capture register
Mode 2 : 16-bit timer with 8-bit programmable prescaler and 16-bit capture register
Mode 3 : 16-bit counter with 16-bit capture register
• Timer 1 : PWM/16-bit timer/counter with toggle output function
Mode 0 : 2-channel 8-bit timer/counter (with toggle output)
Mode 1 : 2-channel 8-bit PWM
Mode 2 : 16-bit timer/counter (with toggle output) Toggle output from lower 8-bits is also possible.
Mode 3 : 16-bit timer (with toggle output) Lower order 8-bits can be used as PWM.
• Timer 4 : 8-bit timer with 6-bit prescaler
• Timer 5 : 8-bit timer with 6-bit prescaler
• Timer 6 : 8-bit timer with 6-bit prescaler
• Timer 7 : 8-bit timer with 6-bit prescaler
• Base Timer
1. The clock signal can be selected from any of the following :
Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0
2. Interrupts of five different time intervals are possible.
■High speed clock counter
• Countable up to 20MHz clock (when using 10MHz main clock)
• Real time output
No.7825-2/21
LC87F74C8A
■Serial interface
• SIO0 : 8-bit synchronous serial interface
1. LSB first/MSB first is selectable
2. Internal 8-bit baud-rate generator (fastest clock period 4/3 tCYC)
3. Consecutive automatic data communication (1 to 256-bits)
• SIO1 : 8-bit asynchronous/synchronous serial interface
Mode 0 : Synchronous 8-bit serial I (2-wire or 3-wire, transmit clock 2 to 512 tCYC)
O
Mode 1 : Asynchronous serial I (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC)
O
Mode 2 : Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC)
Mode 3 : Bus mode 2 (start detection, 8 data bits, stop detection)
■AD converter
• 8-bits × 15-channels
■Remote control receiver circuit (connected to P73/INT3/T0IN terminal)
• Noise rejection function (noise rejection filter’s time constant can be selected from 1/32/128 tCYC)
■Watchdog timer
• The watching time period is determined by an external RC.
• Watchdog timer can produce interrupt or system reset
■Interrupts : 18 sources, 10 vectors
1. Three priority (low, high and highest) multiple interrupts are supported.
During interrupt handling, an equal or lower priority interrupt request is postponed.
2. If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes
precedence. In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
1
Vector
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Selectable Level
X or L
Interrupt Signal
INT0
2
X or L
INT1
3
H or L
INT2/T0L/INT4
4
H or L
INT3/Base timer/INT5
T0H
5
H or L
6
H or L
T1L/T1H
7
H or L
SIO0
8
H or L
SIO1
9
H or L
ADC/MIC/T6/T7
Port 0/T4/T5
10
H or L
• Priority Level : X>H>L
• For equal priority levels, vector with lowest address takes precedence.
■Subroutine stack levels : 2048 levels max. Stack is located in RAM.
■Multiplication and division
• 16-bit × 8-bit
• 24-bit × 16-bit
• 16-bit ÷ 8-bit
• 24-bit ÷ 16-bit
(executed in 5 cycles)
(12 cycles)
(8 cycles)
(12 cycles)
■Oscillation circuits
• On-chip RC oscillation for system clock use.
• CF oscillation for system clock use. (Rf built in, Rd external)
• Crystal oscillation low speed system clock use. (Rf built in, Rd external)
• On-chip frequency variable RC oscillation circuit for system clock use.
No.7825-3/21
LC87F74C8A
■System clock divider
• Low power consumption operation is available
• Minimum instruction cycle time (300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs can be switched
by program (when using 10MHz main clock)
■Standby function
• HALT mode
HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but
peripheral circuits keep operating (some parts of serial transfer operation stop.)
1. Oscillation circuits are not stopped automatically.
2. Released by the system reset or interrupts.
• HOLD mode
HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped.
1. CF, RC and crystal oscillation circuits stop automatically.
2. Released by any of the following conditions.
1. Low level input to the reset pin
2. Specified level input to one of INT0, INT1, INT2, INT4, INT5
3. Port 0 interrupt
• X’tal HOLD mode
X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base timer are stopped.
1. CF and RC oscillation circuits stop automatically.
2. Crystal oscillator operation is kept in its state at HOLD mode inception.
3. Released by any of the following conditions
1. Low level input to the reset pin
2. Specified level input to one of INT0, INT1, INT2, INT4, INT5
3. Port 0 interrupt
4. Base-timer interrupt
■Package
• QIP100E
• TQFP100
■Development tools
• Evaluation chip
• Emulator
: LC876093
: EVA62S + ECB876600 (Evaluation chip board) + SUB877400 +
POD100QFP or POD100SQFP (Type B)
: ICE-B877300 + SUB877400 + POD100QFP or POD100SQFP (Type B)
• Flash ROM write adapter : W87FQ100 or W87FSQ100
■Same package and pin assignment as mask ROM version.
1. LC877400 series options can be set using flash ROM data.
Thus the board used for mass production can be used for debugging and evaluation without modifications.
2. If the program for the mask ROM version is used, the usable ROM/RAM capacity is the same as the mask ROM
version.
No.7825-4/21
LC87F74C8A
Package Dimensions
Package Dimensions
unit : mm
3151A
unit : mm
3274
Pin Assignment
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
V2/PL5/AN13
V1/PL4/AN12
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3
P30/INT4/T1IN
P31/INT4/T1IN
V
3
3
SS
LC87F74C8A
V
DD
P32/INT4/T1IN
P33/INT4/T1IN
P34/INT5/T1IN
P35/INT5/T1IN
P00
P01
P02
P03
P04
P05
Top view
SANYO:QIP100E
No.7825-5/21
LC87F74C8A
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
S47/PF7
V3/PL6/AN14
V2/PL5/AN13
V1/PL4/AN12
COM0/PL0
S23/PC7
S22/PC6
S21/PC5
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
COM1/PL1
COM2/PL2
COM3/PL3
P30/INT4/T1IN
P31/INT4/T1IN
V
V
3
3
SS
DD
LC87F74C8A
P32/INT4/T1IN
P33/INT4/T1IN
P34/INT5/T1IN
P35/INT5/T1IN
P00
S8/PB0
S7/PA7
P01
S6/PA6
P02
S5/PA5
P03
S4/PA4
P04
S3/PA3
P05
S2/PA2
P06
S1/PA1
P07
S0/PA0
P10/SO0
P73/INT3/T0IN
Top view
SANYO:TQFP100
No.7825-6/21
LC87F74C8A
System Block Diagram
Interrupt Control
Stand-by Control
IR
PLA
Flach ROM
CF
RC
PC
MRC
X’tal
Bus Interface
Port 0
ACC
SIO0
B Register
SIO1
Port 1
Port 3
Port 7
Port 8
C Register
ALU
(High-spTeeimd celorck0counter)
Timer 1
Base Timer
LCD Controller
PSW
RAR
ADC
INT0 to 5
Weak Signal Detector
RAM
Noise Rejection Filter
Stack Pointer
Watch Dog Timer
Timer 6
Timer 7
Timer 4
Timer 5
No.7825-7/21
LC87F74C8A
Pin Description
Pin name
I/O
Function
Option
V
V
1, V 2, V
SS
3
SS
-
-
Power supply (-)
Power supply (+)
No
No
SS
DD
1, V 2, V
3
DD DD
Port 0
P00 to P07
I/O
I/O
• 8-bit input/output port
Yes
Yes
• Data direction programmable in nibble units
• Use of pull-up resistor can be specified in nibble units
• Input for HOLD release
• Input for port 0 interrupt
• 8-bit input/output port
Port 1
P10 to P17
• Data direction programmable for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other pin functions
P10 : SIO0 data output
P11 : SIO0 data input or bus input/output
P12 : SIO0 clock input/output
P13 : SIO1 data output
P14 : SIO1 data input or bus input/output
P15 : SIO1 clock input/output
P16 : Timer 1 PWML output
P17 : Timer 1 PWMH output/Buzzer output
• 6-bit input/output port
Port 3
I/O
Yes
P30 to P35
• Data direction can be specified for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other functions
P30 to p33 : INT4 input/HOLD release input/timer 1 event input Timer 0L capture input/Timer 0H
capture input
P34 to P35 : INT5 input/HOLD release input/timer 1 event input Timer 0L capture input/Timer 0H
capture input
• Interrupt detection selection
Rising and
falling
Yes
Rising
Falling
H level
L level
INT4
INT5
Yes
Yes
Yes
Yes
No
No
No
No
Yes
Port 7
I/O
• 4-bit input/output port
No
P70 to P73
• Data direction can be specified for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other functions
P70 : INT0 input/HOLD release input/Timer 0L capture input/output for watchdog timer
P71 : INT1 input/HOLD release input/Timer 0H capture input
P72 : INT2 input/HOLD release input/timer 0 event input/Timer 0L capture input
P73 : INT3 input (noise rejection filter attached) /timer 0 event input/Timer 0H capture input
AD input port : AN8 (P70), AN9 (P71)
• Interrupt detection selection
Rising and
falling
No
No
Yes
Yes
Rising
Falling
H level
L level
INT0
INT1
INT2
INT3
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
No
No
Port 8
I/O
• 8-bit input/output port
No
P80 to P87
• Input/output can be specified for each bit individually
• Other functions :
AD input port : AN0 to AN7
Small signal detector input port : MICIN (P87)
• Segment output for LCD
• Can be used as general purpose input/output port (PA)
• Segment output for LCD
• Can be used as general purpose input/output port (PB)
• Segment output for LCD
S0/PA0 to S7/PA7
I/O
I/O
I/O
No
No
No
S8/PB0 to S15/PB7
S16/PC0 to S23/PC7
• Can be used as general purpose input/output port (PC)
Continued on next page.
No.7825-8/21
LC87F74C8A
Continued from preceding page.
Pin name
I/O
Function
Option
S24/PD0 to S31/PD7
I/O
• Segment output for LCD
• Can be used as general purpose input/output port (PD)
• Segment output for LCD
• Can be used as general purpose input/output port (PE)
• Segment output for LCD
• Can be used as general purpose input/output port (PF)
• Common output for LCD
• Can be used as general purpose input port (PL)
• LCD output bias power supply
• Can be used as general purpose input port (PL)
• Other functions :
No
No
No
No
S32/PE0 to S39/PE7
S40/PF0 to S47/PF7
I/O
I/O
I/O
I/O
COM0/PL0 to
COM3/PL3
V1/PL4 to V3/PL6
No
AD input ports : AN12 to AN14
I
I
Reset terminal
No
No
RES
XT1
• Input for 32.768kHz crystal oscillation
• Other functions :
General purpose input port
AD input port : AN10
• When not in use, connect to V
1
DD
XT2
I/O
• Output for 32.768kHz crystal oscillation
• Other functions :
No
General purpose input port
AD input port : AN11
• When not in use, set to oscillation mode and leave open
Input terminal for ceramic oscillator
CF1
CF2
I
No
No
O
Output terminal for ceramic oscillator
Port output Configuration
Port form and pull-up resistor options are shown in the following table.
Port status can be read even when port is set to output mode.
Option
Terminal
P00 to P07
Option
Output format
Pull-up resistor
applies to :
each bit
1
2
CMOS
Programmable
None
(Note 1)
Nch-open drain
CMOS
P10 to P17
P30 to P35
each bit
each bit
1
Programmable
Programmable
Programmable
None
2
Nch-open drain
CMOS
1
2
Nch-open drain
Nch-open drain
CMOS
P70
–
–
–
–
–
None
None
None
None
None
Programmable
Programmable
None
P71 to P73
P80 to P87
S0/PA0 to S47/PF7
Nch-open drain
CMOS
Programmable
None
COM0/PL0 to
COM3/PL3
Input only
V1/PL4 to V3/PL6
–
–
–
None
None
None
Input only
Input only
None
None
None
XT1
XT2
Output for 32.768kHz crystal oscillation
Note 1 : Attachment of Port 0 programmable pull-up resistors is controllable in nibble units (P00 to 03, P04 to 07).
* Note 1 : Connect as follows to reduce noise on V
.
DD
V
1, V 2 and V 3 must be connected together and grounded.
SS SS SS
* Note 2 : The power supply for the internal memory is V 1 but it uses the V 2 as the power supply for ports.
DD DD
When the V 2 is not backed up, the port level does not become "H" even if the port latch is in the "H" level.
DD
Therefore, when the V 2 is not backed up and the port latch is "H" level, the port level is unstable in the
DD
HOLD mode, and the back up time becomes shorter because the through current runs from V
input buffer.
to GND in the
DD
If V 2 is not backed up, output "L" by the program or pull the port to "L" by the external circuit in the
DD
HOLD mode so that the port level becomes "L" level and unnecessary current consumption is prevented.
No.7825-9/21
LC87F74C8A
Back-up
Capacitors *2
LSI
V
DD
1
Power
Supply
V
V
2
3
DD
DD
V
1 V 2 V 3
SS SS
SS
Absolute Maximum Ratings / Ta = 25°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
-0.3
typ
max
+6.5
unit
V
DD
Supply voltage
V
max
DD
VLCD
V
1, V 2, V
DD
V1/PL4, V2/PL5, V3/PL6
3
V
V
1 = V 2 = V
3
3
DD
DD
DD
DD
DD
DD
DD
Supply voltage
for LCD
1 = V 2 = V
DD
-0.3
-0.3
-0.3
-10
V
DD
Input voltage
V
V
Port L
XT1, XT2, CF1,
• Port 0, 1, 3, 7, 8
• Port A, B, C, D, E, F
Port 0, 1, 3
I
V
V
+0.3
DD
RES
Input/Output
voltage
(1)
IO
+0.3
DD
High
Peak
IOPH(1)
• CMOS output selected
• Current at each pin
Current at each pin
level
output
current
output
current
IOPH(2)
IOPH(3)
ΣIOAH(1)
ΣIOAH(2)
ΣIOAH(3)
ΣIOAH(4)
ΣIOAH(5)
IOPL(1)
Port 71, 72, 73
Port A, B, C, D, E, F
Port 0, 1, 32 to 35
Port 30, 31
-3
-5
Current at each pin
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Current at each pin
Current at each pin
Current at each pin
Current at each pin
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Ta = -20 to +70°C
Total
output
current
-40
-10
-5
Port 7
Port A, B, C
Port D, E, F
Port 0, 1, 32 to 35
Port 30, 31
-25
-25
mA
Low
level
output
current
Peak
output
current
20
30
5
IOPL(2)
IOPL(3)
Port 7, 8
IOPL(4)
Port A, B, C, D, E, F
Port 0, 1, 32 to 35
Port 30, 31
15
60
60
20
40
40
559
404
Total
output
current
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
ΣIOAL(5)
Pd max
Port 7, 8
Port A, B, C
Port D, E, F
QIP100E
Maximum power
consumption
mW
°C
TQFP100
Operating
temperature range
Storage
Topr
Tstg
-20
-55
70
125
temperature range
No.7825-10/21
LC87F74C8A
Recommended Operating Range / Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
5.5
unit
DD
Operating supply
voltage range
V
V
(1)
V
1 = V 2 = V 3
DD DD
0.294µs≤ tCYC≤200µs
0.735µs≤ tCYC≤200µs
4.5
DD
DD
(2)
3.0
5.5
DD
Supply voltage
range in Hold
mode
VHD
V
1
Keep RAM and register
data in HOLD mode.
DD
2.0
5.5
Input high voltage
V
V
(1)
(2)
• Port 0, 3, 8
• Port A, B, C, D, E, F, L
• Port 1
• Port 71, 72, 73
• P70 port input/interrupt
P87 small signal input
Output disable
Output disable
0.3V
DD
IH
3.0 to 5.5
3.0 to 5.5
V
V
DD
DD
+0.7
IH
0.3V
DD
+0.7
V
V
(3)
(4)
Output disable
Output disable
3.0 to 5.5
3.0 to 5.5
3.0 to 5.5
3.0 to 5.5
0.75V
V
V
IH
IH
DD
DD
DD
Port 70
Watchdog timer
XT1, XT2, CF1,
V
0.9V
DD
V
V
(5)
RES
0.75V
V
IH
DD
SS
DD
DD
Input low voltage
(1)
• Port 0, 3, 8
• Port A, B, C, D, E, F, L
• Port 1
• Port 71, 72, 73
• P70 port input/interrupt
Port 87 small signal
input
Port 70
Watchdog timer
XT1, XT2, CF1,
Output disable
Output disable
0.15V
IL
V
+0.4
V
(2)
IL
0.1V
DD
3.0 to 5.5
V
V
SS
+0.4
V
V
V
(3)
(4)
(5)
Output disable
Output disable
IL
IL
IL
3.0 to 5.5
3.0 to 5.5
0.25V
SS
DD
DD
0.8V
V
V
SS
-1.0
RES
3.0 to 5.5
4.5 to 5.5
3.0 to 5.5
0.25V
DD
SS
Operation cycle
time
tCYC
0.294
0.735
200
µs
200
External system
clock frequency
FEXCF(1)
CF1
• CF2 open
• System clock divider :
1/1
• External clock
DUTY = 50 ± 5%
• CF2 open
• System clock divider :
1/2
4.5 to 5.5
3.0 to 5.5
0.1
0.1
10
4
4.5 to 5.5
3.0 to 5.5
0.2
0.2
20
8
Oscillation
frequency range
(Note 1)
FmCF(1)
FmCF(2)
CF1, CF2
CF1, CF2
10MHz ceramic resonator
oscillation
Refer to figure 1
4MHz ceramic resonator
oscillation
MHz
4.5 to 5.5
10
3.0 to 5.5
3.0 to 5.5
3.0 to 5.5
4
1.0
50
Refer to figure 1
RC oscillation
FmRC
0.3
2.0
FmMRC
Frequency variable RC
oscillation source
oscillation
FsX’tal
XT1, XT2
32.768kHz crystal
resonator oscillation
Refer to figure 2
3.0 to 5.5
32.768
kHz
Note 1 : The parts value of oscillation circuit is shown in table 1 and table 2.
No.7825-11/21
LC87F74C8A
Electrical Characteristics / Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Limits
typ
Parameter
Symbol
Pins
Conditions
V
[V]
min
max
unit
DD
High level input
current
I
(1)
• Port 0, 1, 3, 7, 8
• Port A, B, C, D, E, F, L
• Output disabled
• Pull-up resister OFF.
IH
• V = V
(Including OFF state leak
current of the output Tr.)
3.0 to 5.5
1
IN DD
I
I
(2)
(3)
V
= V
RES
3.0 to 5.5
3.0 to 5.5
1
1
IH
IH
IN DD
XT1, XT2
When configured as an
input port
V
V
V
= V
IN
IN
IN
DD
DD
I
I
(4)
(5)
CF1
= V
3.0 to 5.5
3.0 to 5.5
15
15
IH
IH
P87/AN7/MICIN
= VBIS+0.5V
4.2
8.5
small signal input
• Port 0, 1, 3, 7, 8
• Port A, B, C, D, E, F, L
(VBIS : Bias voltage)
• Output disabled
• Pull-up resister OFF.
µA
Low level input
current
I
(1)
IL
• V = V
(Including OFF state leak
current of the output Tr.)
3.0 to 5.5
-1
IN SS
I
I
(2)
(3)
V
= V
RES
3.0 to 5.5
3.0 to 5.5
-1
-1
IL
IL
IN SS
XT1, XT2
When configured as an
input port
V
V
V
= V
IN
IN
IN
SS
I
I
(4)
(5)
CF1
= V
3.0 to 5.5
3.0 to 5.5
-15
-15
-1
IL
IL
SS
P87/AN7/MICIN
small signal input
Port 0, 1, 3, CMOS
output option
= VBIS-0.5V
-8.5
-4.2
(VBIS : Bias voltage)
High level output
voltage
V
V
V
V
V
V
V
V
V
V
V
V
(1)
I
I
I
I
I
I
I
I
I
I
I
I
I
= -1.0mA
= -0.1mA
= -0.4mA
= -1.0mA
= -0.1mA
= 10mA
= 1.6mA
= 30mA
= 1mA
4.5 to 5.5
3.0 to 5.5
3.0 to 5.5
4.5 to 5.5
3.0 to 5.5
4.5 to 5.5
3.0 to 5.5
4.5 to 5.5
4.5 to 5.5
3.0 to 5.5
4.5 to 5.5
3.0 to 5.5
V
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
OL
DD
(2)
(3)
(4)
(5)
V
V
-0.5
-1
DD
V
Port 7
DD
Port A, B, C, D, E, F
V
-1
DD
-0.5
DD
Low level output
voltage
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Port 0, 1, 3
1.5
0.4
1.5
0.4
0.4
1.5
0.4
OL
OL
OL
OL
OL
OL
OL
Port 30, 31
Port 7, 8
V
= 0.5mA
= 8mA
Port A, B, C, D, E, F
S0 to S47
= 1.4mA
LCD output
voltage regulation
VODLS
= 0mA
O
VLCD, 2/3VLCD, 1/3VLCD
level output Refer to figure 8
3.0 to 5.5
0
0
± 0.2
VODLC
COM0 to COM3
I
= 0mA
O
VLCD, 2/3VLCD, 1/2VLCD
1/3VLCD level output
Refer to figure 8
3.0 to 5.5
± 0.2
LCD bias resistor
RLCD(1)
RLCD(2)
Resistance per one bias
resistor
• Resistance per one
bias resistor
Refer to figure 8
3.0 to 5.5
3.0 to 5.5
60
30
Refer to figure 8
kΩ
• 1/2R mode
Resistance of
pull-up MOS Tr.
Rpu
• Port 0, 1, 3, 7
• Port A, B, C, D, E, F
V
= 0.9V
DD
4.5 to 5.5
3.0 to 5.5
15
25
40
70
70
OH
150
Hysterisis voltage
VHIS(1)
VHIS(2)
• Port 1, 7
3.0 to 5.5
3.0 to 5.5
0.1V
DD
•
RES
V
Port 87 small signal
input
0.1V
DD
Continued on next page.
No.7825-12/21
LC87F74C8A
Continued from preceding page.
Limits
typ
Parameter
Symbol
CP
Pins
Conditions
V
[V]
min
max
unit
pF
DD
Pin capacitance
All pins
• All other terminals
connected to V
• f = 1MHz
.
SS
3.0 to 5.5
3.0 to 5.5
10
• Ta = 25°C
Input sensitivity
Vsen
Port 87 small signal
input
0.12V
Vp-p
DD
Serial Input/Output Characteristics / Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
4/3
typ
max
unit
DD
Cycle time
tSCK(1)
SCK0 (P12)
Refer to figure 6
Low level pulse
width
tSCKL(1)
tSCKLA(1)
tSCKH(1)
tSCKHA(1)
tSCK(2)
2/3
2/3
2/3
3
3.0 to 5.5
3.0 to 5.5
3.0 to 5.5
3.0 to 5.5
High level pulse
width
tCYC
Cycle time
SCK1 (P15)
SCK0 (P12)
Refer to figure 6
2
Low level pulse
width
High level pulse
width
tSCKL(2)
1
tSCKH(2)
1
Cycle time
tSCK(3)
• CMOS output
• Refer to figure 6
4/3
Low level pulse
width
tSCKL(3)
tSCKLA(2)
tSCKH(3)
tSCKHA(2)
tSCK(4)
1/2
3/4
1/2
2
tSCK
High level pulse
width
Cycle time
SCK1 (P15)
• CMOS output
• Refer to figure 6
2
tCYC
tSCK
Low level pulse
width
tSCKL(4)
1/2
1/2
High level pulse
width
Data set-up time
tSCKH(4)
tsDI
SI0 (P11),
SI1 (P14),
SB0 (P11),
SB1 (P14)
• Measured with respect to
SI0CLK leading edge.
• Refer to figure 6
4.5 to 5.5
3.0 to 5.5
4.5 to 5.5
3.0 to 5.5
0.03
0.1
Data hold time
thDI
0.03
0.1
µs
Output delay time
tdDO
SO0 (P10),
SO1 (P13),
SB0 (011),
SB1 (P14)
• When Port is open drain :
Time delay form SIOCLK
trailing edge to the SO
data change
1/3 tCYC
+0.05
4.5 to 5.5
3.0 to 5.5
1/3 tCYC
+0.25
• Refer to figure 6
No.7825-13/21
LC87F74C8A
Pulse Input Conditions / Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
DD
High/low level
pulse width
tPIH(1)
tPIL(1)
INT0 (P70),
INT1 (P71),
INT2 (P72)
INT4 (P30 to P33)
INT5 (P34 to P35)
INT3 (P73)
• Condition that interrupt is
accepted
• Condition that event input
to timer 0 is accepted
3.0 to 5.5
1
2
tPIH(2)
tPIL(2)
• Condition that interrupt is
accepted
(Noise rejection ratio is 1/1.)
3.0 to 5.5
3.0 to 5.5
3.0 to 5.5
• Condition that event input
to timer 0 is accepted
• Condition that interrupt is
accepted
tPIH(3)
tPIL(3)
INT3 (P73)
(Noise rejection ratio is 1/32.)
tCYC
64
• Condition that event input
to timer 0 is accepted
• Condition that interrupt is
accepted
• Condition that event input
to timer 0 is accepted
• Condition that signal is
accepted to small signal
detection counter.
tPIH(4)
tPIL(4)
INT3 (P73)
(Noise rejection ratio is
1/128.)
256
tPIL(5)
tPIL(5)
MICIN (P87)
RES
3.0 to 5.5
3.0 to 5.5
1
tPIL(6)
• Condition that reset is
accepted
200
µs
AD Converter Characteristics / Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
bit
DD
Resolution
N
AN0 (P80)
to AN7 (P87)
AN8 (P70)
AN9 (P71)
AN10 (XT1)
AN11 (XT2)
AN12 (V1)
AN13 (V2)
AN14 (V3)
3.0 to 5.5
3.0 to 5.5
8
Absolute precision
Conversion time
ET
(Note 2)
AD conversion time = 32 × tCYC
(ADCR2 = 0) (Note 3)
±1.5
LSB
tCAD
15.62
97.92
(tCYC =
3.06µs)
97.92
(tCYC =
3.06µs)
97.92
(tCYC =
1.53µs)
97.92
4.0 to 5.5
3.0 to 5.5
4.5 to 5.5
(tCYC =
0.488µs)
23.52
(tCYC =
0.735µs)
18.82
(tCYC =
0.294µs)
47.04
µs
AD conversion time = 64 × tCYC
(ADCR2 = 1)
(Note 3)
3.0 to 5.5
3.0 to 5.5
(tCYC =
0.735µs)
(tCYC =
1.53µs)
Analog input
voltage range
Analog port input
current
VAIN
V
V
V
SS
DD
1
IAINH
IAINL
VAIN = V
DD
VAIN = V
SS
3.0 to 5.5
3.0 to 5.5
µA
-1
Note 2 : Absolute precision does not include quantizing error (±1/2 LSB).
Note 3 : Conversion time means time from executing AD conversion instruction to loading complete digital value to
register.
No.7825-14/21
LC87F74C8A
Current Dissipation Characteristics / Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
DD
Current
IDDOP(1)
V
V
V
1 =
2 =
3
• FmCF = 10MHz Ceramic resonator oscillation
• FsX’tal = 32.768kHz crystal oscillation
• System clock : CF 10MHz oscillation
• Frequency variable RC oscillation stopped
• Internal RC oscillation stopped.
• Divider : 1/1
DD
DD
DD
consumption
during normal
operation
4.5 to 5.5
4.5 to 5.5
16
17
35
(Note 4)
IDDOP(2)
• CF1 = 20MHz external clock
• FsX’tal = 32.768kHz crystal oscillation
• System clock : CF1 oscillation
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped
• Divider : 1/2
36
IDDOP(3)
IDDOP(4)
• FmCF = 4MHz Ceramic resonator oscillation
• FsX’tal = 32.768kHz crystal oscillation
• System clock : CF 4MHz oscillation
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped
• Divider : 1/1
4.5 to 5.5
3.0 to 4.5
7
3
21
13
mA
IDDOP(5)
IDDOP(6)
IDDOP(7)
• FmCF = 0Hz (No oscillation)
• FsX’tal = 32.768kHz crystal oscillation
• Frequency variable RC oscillation stopped
• System clock : RC oscillation
• Divider : 1/2
• FmCF = 0Hz (No oscillation)
• FsX’tal = 32.768kHz crystal oscillation
• Internal RC oscillation stopped.
• System clock : 1MHz with frequency variable
RC oscillation
4.5 to 5.5
3.0 to 4.5
1.5
0.8
11
7
4.5 to 5.5
3.0 to 4.5
4.5 to 5.5
3.0 to 4.5
2.5
1.8
80
13
9
IDDOP(8)
IDDOP(9)
• Divider : 1/2
• FmCF = 0Hz (No oscillation)
• FsX’tal = 32.768kHz crystal oscillation
• System clock : 32.768kHz
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped
• Divider : 1/2
450
250
µA
IDDOP(10)
35
Current
IDDHALT(1)
V
V
V
1 =
2 =
3
HALT mode
DD
DD
DD
consumption
during HALT
mode
• FmCF = 10MHz Ceramic resonator oscillation
• FsX’tal = 32.768kHz crystal oscillation
• System clock : CF 10MHz oscillation
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped
• Divider : 1/1
4.5 to 5.5
4.5 to 5.5
4.6
5.1
12
13
(Note 4)
IDDHALT(2)
HALT mode
• CF1 = 20MHz external clock
• FsX’tal = 32.768kHz crystal oscillation
• System clock : CF1 oscillation
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped
• Divider : 1/2
mA
IDDHALT(3)
IDDHALT(4)
HALT mode
• FmCF = 4MHz ceramic resonator oscillation
• FsX’tal = 32.768kHz crystal oscillation
• System clock : CF 4MHz oscillation
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped
• Divider : 1/1
4.5 to 5.5
3.0 to 4.5
2.2
1.0
6
5
Continued on next page.
No.7825-15/21
LC87F74C8A
Continued from preceding page.
Limits
typ
Parameter
Symbol
Pins
Conditions
V
[V]
min
max
unit
DD
Current
IDDHALT(5)
V
V
V
1 =
2 =
3
HALT mode
DD
DD
DD
4.5 to 5.5
3.0 to 4.5
600
1600
consumption
during HALT
mode
• FmCF = 0Hz (Oscillation stop)
• FsX’tal = 32.768kHz crystal oscillation
• System clock : RC oscillation
• Frequency variable RC oscillation stopped
• Divider : 1/2
IDDHALT(6)
IDDHALT(7)
(Note 4)
350
1300
3600
HALT mode
• FmCF = 0Hz (No oscillation)
• FsX’tal = 32.768kHz crystal oscillation
• Internal RC oscillation stopped.
• System clock : 1MHz with frequency variable
RC oscillation
• Divider : 1/2
HALT mode
4.5 to 5.5
3.0 to 4.5
4.5 to 5.5
3.0 to 4.5
1500
µA
IDDHALT(8)
IDDHALT(9)
1250
25
3300
100
60
• FmCF = 0Hz (Oscillation stop)
• FsX’tal = 32.768kHz crystal oscillation
• System clock : 32.768kHz
• Internal RC oscillation stopped.
• Frequency variable RC oscillation stopped
• Divider : 1/2
IDDHALT(10)
12
Current
IDDHOLD(1)
IDDHOLD(2)
IDDHOLD(3)
V
V
1
1
HOLD mode
DD
4.5 to 5.5
3.0 to 4.5
0.1
25
20
consumption
during HOLD
mode
Current
consumption
during
• CF1 = V
(when using external clock)
or open
DD
0.03
µA
Date/time clock
HOLD mode
DD
4.5 to 5.5
20
8
90
50
• CF1 = V
(when using external clock)
or open
DD
IDDHOLD(4)
Date/time clock
HOLD mode
3.0 to 4.5
• FmX’tal = 32.768kHz crystal oscillation
Note 4 : The currents through the output transistors and the pull-up MOS transistors are ignored.
F-ROM Write Characteristics / Ta = +10°C to +55°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Limits
Parameter
Symbol
Pins
Conditions
V
[V]
min
typ
max
unit
DD
On-board write
current
IDDF(1)
V
1
• 128-byte write
• Including erase current
DD
4.5 to 5.5
30
65
mA
Write cycle time
tFW(1)
• 128-byte write
• Including erase current
4.5 to 5.5
6.3
9
mS
• Not including time to prepare 128-byte data
Main System Clock Oscillation Circuit Characteristics
The characteristics in the table bellow is based on the following conditions :
1. Use the standard evaluation board SANYO has provided.
2. Use the peripheral parts with indicated value externally.
3. The peripheral parts value is a recommended value of oscillator manufacturer
Table 1. Main system clock oscillation circuit characteristics using ceramic resonator
Operating
Oscillation
stabilizing time
Circuit parameters
supply voltage
Frequency
Manufacturer
Oscillator
Notes
range
[V]
C1
[pF]
C2
[pF]
Rd1
[Ω]
typ
max
[mS]
[mS]
0.05
0.05
0.05
0.05
CSTCE10M0G52-R0
CSTLS10M0G53-B0
CSTCR4M00G53-R0
CSTLS4M00G53-B0
(10)
(10)
(15)
(15)
(10)
(10)
(15)
(15)
220
220
1k
4.5 to 5.5
4.5 to 5.5
3.0 to 5.5
3.0 to 5.5
0.15
0.15
0.15
0.15
Built-in C1, C2
Built-in C1, C2
Built-in C1, C2
Built-in C1, C2
10MHz
4MHz
Murata
Murata
470
The oscillation stabilizing time is a period until the oscillation becomes stable after V
minimum operating voltage. (Refer to Figure 4)
becomes higher than
DD
No.7825-16/21
LC87F74C8A
Subsystem Clock Oscillation Circuit Characteristics
The characteristics in the table bellow is based on the following conditions :
1. Use the standard evaluation board SANYO has provided.
2. Use the peripheral parts with indicated value externally.
3. The peripheral parts value is a recommended value of oscillator manufacturer
Table 2. Subsystem clock oscillation circuit characteristics using crystal oscillator
Oscillation
stabilizing time
Circuit parameters
Operating supply
voltage range
[V]
Frequency
Manufacturer
Oscillator
Notes
C3
C4
Rf
Rd2
[Ω]
typ
[S]
max
[S]
[pF]
[pF]
[Ω]
SEIKO
EPSON
32.768kHz
MC-306
18
18
OPEN
560k
3.0 to 5.5
1.553
3.00
The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which
starts the sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure 4)
Notes : Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to
the oscillation pins as possible with the shortest possible pattern length.
XT1
XT2
CF1
CF2
Rd1
C2
Rf
Rd2
C4
CF
C1
C3
X’tal
Figure 1 Ceramic oscillation circuit
Figure 2 Crystal oscillation circuit
0.5V
DD
Figure 3 AC timing measurement point
No.7825-17/21
LC87F74C8A
V
V
DD
Power
RES
limit
DD
0V
Reset time
Internal RC
Resonator
tmsCF
CF1, CF2
tmsXtal
XT1, XT2
Operation mode
Unfixed
Reset
Instruction execution mode
Reset time and oscillation stable time
Without HOLD
Release
HOLD release
HOLD release signal VALID
Internal RC
tmsCF
CF1, CF2
tmsXtal
XT1, XT2
Operation mode
HOLD
HALT
HOLD release signal and oscillation stable time
Figure 4 Oscillation stabilizing time
No.7825-18/21
LC87F74C8A
V
DD
R
C
(Note)
Select C
RES
and R
value to assure that at least
RES
RES
200µs reset time is generated after the V
higher than the minimum operating voltage.
becomes
RES
DD
RES
Figure 5 Reset circuit
SIOCLK
DATAIN
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM
transmission period
(only SIO0)
tSCK
tSCKL
tSCKH
SIOCLK
DATAIN
tsDI
thDI
tdDO
DATAOUT
Data RAM
transmission period
(only SIO0)
tSCKLA
tSCKHA
SIOCLK
DATAIN
tsDI
thDI
tdDO
DATAOUT
Figure 6 Serial input/output wave form
No.7825-19/21
LC87F74C8A
tPIL
tPIH
Figure 7 Pulse input timing
V
DD
SW : ON/OFF (programmable)
SW : ON (VLCD = V
RLCD
RLCD
RLCD
RLCD
)
DD
VLCD
RLCD
RLCD
RLCD
RLCD
RLCD
2/3VLCD
1/2VLCD
1/3VLCD
RLCD
GND
Figure 8 LCD bias resistor
No.7825-20/21
LC87F74C8A
No.7825-21/21
PS
相关型号：
LC87F76C8AU-QFP-E
8-bit LCD Driver Microcontroller with 128K-byte Flash ROM and 4096-byte RAM, PQFP80 14x14 / QFP80, 60-FTRAY
ONSEMI
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