LC87F7032A_技术文档

Ordering number : ENA0653

CMOS IC

FROM 32K byte, RAM 1024 byte on-chip

LC87F7032A

8-bit 1-chip Microcontroller

Overview

The LC87F7032A is an 8-bit single chip microcontroller with the following on-chip functional blocks:

• CPU: operable at a minimum bus cycle time of 250ns

• 32K bytes Flash ROM

• On-chip ΡΑΜ: 1024 bytes

• LCD controller/driver

• 16bit timer × 2ch + 8bit timer × 1ch or more

• Synchronous serial I/O port (with automatic block transmit/receive function)

• Asynchronous/synchronous serial I/O port

• System clock divider

• 20-source 10-vectored interrupt system

• 8-bit AD converter × 9-channel

• On chip debugger

All of the above functions are fabricated on a single chip.

Features

Flash ROM

• Block-erasable in 128byte units

• 32768 × 8 bits (LC87F7032A)

RAM

• 1024 × 9-bits (LC87F7032A)

* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by

SANYO Semiconductor Co., Ltd.

Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to

"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,

communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be

intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace

instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety

equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case

of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee

thereof. If you should intend to use our products for applications outside the standard applications of our

customer who is considering such use and/or outside the scope of our intended standard applications, please

consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our

customer shall be solely responsible for the use.

Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate

the performance, characteristics, and functions of the described products in the independent state, and are not

guarantees of the performance, characteristics, and functions of the described products as mounted in the

customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent

device, the customer should always evaluate and test devices mounted in the customer

's products or

equipment.

Ver.1.00

20707HKIM 20061204-S00007 No.A0653-1/21

LC87F7032A

Minimum Bus Cycle Time

• 250ns (4MHz)

Note: Bus cycle time indicates the speed to read ROM.

Minimum Instruction Cycle Time (tCYC)

• 750ns (4MHz)

Ports

• Input/output ports

Data direction programmable for each bit individually 12 (P1n, P70 to P73)

Data direction programmable in nibble units

8 (P0n)

(When N-channel open drain output is selected, data can be input in bit units.)

Other function

3 (DBGP0, DBGP1, DBGP2)

• PWM input/output port1 (PWM)

• LCD ports

Segment output

24 (S00 to S23)

Common output

Bias terminals for LCD driver

Other functions

4 (COM0 to COM3)

5 (V1 to V3, CUP1, CUP2)

Input/output ports

8 (PCn)

• Oscillator pins

• Reset pin

• Power supply

4 (CF1, CF2, XT1, XT2)

1 ( )

RES

4 (V 1 to 2,V 1 to 2)

SS DD

1 (VDC)

LCD Controller

• Seven display modes are available

• Duty 1/3duty, 1/4duty

• Bias 1/2bias, 1/3bias

• Segment output can be switched to general purpose input/output ports.

Timers

• Timer 0: 16-bit timer/counter with capture register

Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register

Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with

8-bit capture register

Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register

Mode 3: 16 bit counter with 16 bit capture register

• Timer1: PWM/16 bit timer/counter with toggle output function

Mode 0: 2 channel 8 bit timer/counter (with toggle output)

Mode 1: 2 channel 8 bit PWM

Mode 2: 16 bit timer/counter (with toggle output) toggle output from lower 8 bits is also possible.

Mode 3: 16 bit timer (with toggle output) lower order 8 bits can be used as PWM.

• Timer4: 8-bit timer with 6-bit prescaler

• Timer5: 8-bit timer with 6-bit prescaler

• Timer6: 8-bit timer with 6-bit prescaler (with toggle output)

• Timer7: 8-bit timer with 6-bit prescaler (with toggle output)

• Base Timer

1) The clock signal can be selected from any of the following:

Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0

2) Interrupts of five different time intervals are possible.

No.A0653-2/21

LC87F7032A

SIO

• SIO0: 8-bit synchronous serial interface

1) LSB first/MSB first is selectable

2) Internal 8 bit baud-rate generator (fastest clock period 4/3 tCYC)

3) Consecutive automatic data communication (1 to 256 bits)

• SIO1: 8 bit asynchronous/synchronous serial interface

Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC)

Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC)

Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC)

Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)

UART

• Full duplex

• 1 stop bit (2-bit in continuous data transmission)

• Built-in baudrate generator

AD Converter

• 8-bit × 9-channels

PWM

• Multifrequency 12-bit PWM × 1-channels

Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)

• Noise rejection function (noise rejection filter’s time constant can be selected from 1/32/128 tCYC)

Watchdog Timer

• Watchdog timer can produce interrupt or system reset.

• Watchdog timer has two types.

Use an external RC circuit

Use the microcontroller’s basetimer

Clock Output Function

1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.

2) Able to output oscillation clock of sub clock.

Interrupts

• 20 sources, 10 vector addresses

1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or

lower priority interrupt request is postponed.

2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes

precedence. In the case of equal priority levels, the vector with the lowest address takes precedence.

No.

1

Vector Address

00003H

Level

X or L

H or L

Interrupt Source

INT0

2

0000BH

00013H

INT1

3

INT2/T0L

4

0001BH

00023H

INT3/base timer

T0H

5

6

0002BH

00033H

T1L/T1H

7

SIO0/UART1 receive

SIO1/UART-send

ADC/T6/T7

8

0003BH

00043H

9

10

0004BH

Port 0/T4/T5/PWM

• Priority levels X > H > L

• For equal priority levels, vector with lowest address takes precedence.

No.A0653-3/21

LC87F7032A

Subroutine Stack Levels

• 512 levels maximum (the stack is allocated in RAM)

High-speed Multiplication/Division Instructions

• 16-bits × 8-bits

• 24-bits × 16-bits

• 16-bits ÷ 8-bits

• 24-bits ÷ 16-bits

(5 tCYC execution time)

(12 tCYC execution time)

(8 tCYC execution time)

(12 tCYC execution time)

Oscillation Circuits

• On-chip RC oscillation for system clock use.

• CF oscillation (4MHz) for system clock use. (Rf built in, Rd external)

• Crystal oscillation (32.768kHz) low speed system clock use. (Rf built in, Rd external)

• On-chip frequency variable RC oscillation circuit for system clock use.

System Clock Divider Function

• Low power consumption operation is available

• Minimum instruction cycle time (750ns, 1.5µs, 3.0µs, 6.0µs, 12µs, 24µs, 48µs, 96µs, 192µs can be switched

by program (when using 4MHz main clock)

Standby Function

• HALT mode:

HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but

peripheral circuits keep operating (some parts of serial transfer operation stop.)

1) Oscillation circuits are not stopped automatically.

2) Released by the system reset or interrupts.

• HOLD mode

HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped.

1) CF, RC and crystal oscillation circuits stop automatically.

2) Released by any of the following conditions.

(1) Low level input to the reset pin

(2) Specified level input to one of INT0, INT1, INT2.

(3) Port 0 interrupt

• X'tal HOLD mode

X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.

All peripheral circuits except the base timer are stopped.

1) CF and RC oscillation circuits stop automatically.

2) Crystal oscillator operation is kept in its state at HOLD mode inception.

3) Released by any of the following conditions

(1) Low level input to the reset pin

(2) Specified level input to one of INT0, INT1, INT2.

(3) Port 0 interrupt

(4) Base-timer interrupt

ROM Correct Function

• ROM correct program is executed by checking the program counter.

• ROM correct program area: 128byte

On-chip Debugger Function

• Software debug is available on the target board.

Package Form

• ΤQFP64J(7×7) :Lead-free type

• QIP64E(14×14) :Lead-free type

Development Tool

• On-chip Debugger: TCB87 TypeB+LC87F7032A

No.A0653-4/21

LC87F7032A

Flash ROM Programming boards

Package

Programming Boards

TQFP64J(7×7)

QIP64E(14×14)

W87F70256TQ7

W87F70256Q

Package Dimensions

unit : mm (typ)

3289

9.0

7.0

48

33

49

32

17

64

1

16

0.125

0.4

0.16

(0.5)

SANYO : TQFP64J(7X7)

Package Dimensions

unit : mm (typ)

3159A

17.2

14.0

48

33

32

49

64

17

1

16

0.8

0.35

0.15

(1.0)

SANYO : QIP64E(14X14)

No.A0653-5/21

LC87F7032A

Pin Assignment

RES

XT1

XT2

VSS1

CF1

CF2

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

S7

S6

S5

S4

S3

S2

S1

S0

COM3

COM2

COM1

COM0

V3

V2

V1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

VDD1

P00/AN0

P01/AN1

P02/AN2

P03/AN3

P04/AN4

LC87F7032A

P05/DBGP0

P06/DBGP1

P07/DBGP2

PWM

VDC

Top view

SANYO: TQFP64J(7×7)

SANYO: QIP64E(14×14)

“Lead-free Type”

No.A0653-6/21

LC87F7032A

System Block Diagram

Interrupt control

Stand-by control

IR

PLA

ROM Correct

Flash ROM

CF

RC

MRC

X’tal

PC

SIO0

SIO1

Bus interface

Port 0

ACC

B register

Timer 0

(High-speed clock counter)

C register

Port 1

Timer 1

ALU

Port 7

Base timer

PSW

RAR

LCD controller

INT0 to 3

Noise rejection filter

ADC

RAM

Timer 4

Timer 5

Timer 6

Timer 7

Stack pointer

Watchdog timer

On-chip debugger

UART

PWM

No.A0653-7/21

LC87F7032A

Pin Description

Pin name

I/O

Function

Option

No

V

1,V

2

-

• Power supply (-)

• Power supply (+)

SS SS

1,V

2

No

DD

VDC

-

No

CUP1,CUP2

PWM

-

• Capacitor connecting terminals for step-up/step-down

• PWM input/output port

No

I/O

No

PORT0

• 8bit input/output port

Yes

P00 to P07

• Data direction programmable in nibble units

• Use of pull-up resistor can be specified in nibble units

• Input for HOLD release

• Input for port 0 interrupt

• Input for AD Converter: AN0(P00) to AN4(P04)

• On chip debugger terminal (P05, P06, P07)

• 8bit input/output port

PORT1

I/O

Yes

P10 to P17

• Data direction programmable for each bit

• Use of pull-up resistor can be specified for each bit individually

• Other pin functions

P10 SIO0 data output

P11 SIO0 data input or bus input/output

P12 SIO0 clock input/output

P13 SIO1 data output

P14 SIO1 data input or bus input/output

P15 SIO1 clock input/output

P16: Timer 1 PWML output

P17: Timer 1 PWMH output/buzzer output

• 4bit Input/output port

PORT7

I/O

No

P70 to P73

• Data direction can be specified for each bit

• Use of pull-up resistor can be specified for each bit individually

• Input for AD Converter (AN5 to AN8)

• Other functions

P70: INT0 input/HOLD release input/timer0L capture input/output for watchdog timer/AN5

P71: INT1 input/HOLD release input/timer0H capture input/AN6

P72: INT2 input/HOLD release input/timer 0 event input/timer0L capture input/AN7

P73: INT3 input (noise rejection filter attached)/timer 0 event input/timer0H capture input/AN8

• Interrupt detection selection

Rising and

Rising

Falling

H level

L level

falling

disable

enable

INT0

INT1

INT2

INT3

enable

disable

enable

disable

S0 to S15

O

• Segment output for LCD

No

S16/PC0 to

S23/PC7

I/O

• Can be used as general purpose input/output port (PC)

• UART terminal (S22, S23 )

COM0 to

COM3

O

• Common output for LCD

No

V1 to V3

I/O

• LCD output bias power supply

• Reset terminal

No

RES

XT1

I

• Input for 32.768kHz crystal oscillation

• When not in use, connect to V

1

DD

XT2

CF1

I/O

I

• Output for 32.768kHz crystal oscillation

No

• When not in use, set to oscillation mode and leave open

• Input terminal for ceramic oscillator

• When not in use, connect to V

1

DD

CF2

O

• Output terminal for ceramic oscillator

• When not in use, leave open

No

No.A0653-8/21

LC87F7032A

Port Output Configuration

Port form and pull-up resistor options are shown in the following table.

Port status can be read even when port is set to output mode.

Terminal

P00 to P07

Option applies to:

each bit

Options

1

Output Form

Pull-up resistor

Programmable

CMOS

(Note 1)

None

2

Nch-open drain

CMOS

P10 to P17

each bit

1

Programmable

None

2

None

1

Nch-open drain

CMOS

P70

-

P71 to P73

-

S16(PC0) to

S23(PC7)

each bit

CMOS

2

P-ch Open Drain

3

N-ch Open Drain

Note 1: Attachment of Port0 programmable pull-up resistors is controllable in nibble units (P00 to 03, P04 to 07).

* 1: Connect as follows to reduce noise on V

.

DD

V

1 and V 2 must be connected together and grounded.

SS SS

* 2: The power supply for the internal memory is V 1. V 1 and V 2 are used as the power supply for ports.

DD DD DD

When V 1 and V 2 are not backed up, the port level does not become “H” even if the port latch is in the “H”

DD DD

level. Therefore, when V 1 and V 2 are not backed up and the port latch is “H” level, the port level is

DD DD

unstable in the HOLD mode, and the back up time becomes shorter because the through current runs from V

GND in the input buffer.

to

DD

If V 1 and V 2 are not backed up, output “L” by the program or pull the port to “L” by the external circuit in

DD DD

the HOLD mode so that the port level becomes “L” level and unnecessary current consumption is prevented.

LSI1

Back up capacitors

V

1

2

DD

Power

supply

V

DD

V1

V2

V3

CUP1

CUP2

VDC

V

1 V

2

SS

No.A0653-9/21

LC87F7032A

Absolute Maximum Ratings at Ta = 25°C, V 1 = V 2 = 0V

SS

Specification

typ max

+4.6

Parameter

Symbol

Pins

Conditions

V

[V]

min

-0.3

unit

DD

Supply voltage

V

max

V

1,V 2,V2

DD

V

1=V 2=V2

DD

DD DD

Supply voltage

For LCD

VLCD

V1

-0.3

1/2 V

DD

V2

V

V3

3/2 V

RES

Input voltage

V

I

XT1,CF1,

V

+0.3

DD

Input/Output voltage

V

(1)

IO

• Ports 0, 1, 7

• Port C, PWM

Ports 0, 1, 7, C,

PWM

-0.3

+0.3

Peak output

current

IOPH(1)

• CMOS output selected

• Current at each pin

-4

Total output

current

ΣIOAH(1)

Port 7, PWM

Total of all pins

-10

ΣIOAH(2)

ΣIOAH(3)

ΣIOAH(4)

IOPL(1)

Port 0

Port 1

Port C

Total of all pins

Current at each pin

-25

-15

mA

Peak output

current

Ports 02 to 07

Ports 1, 7, C, PWM

Ports 00, 01

6

IOPL(2)

Current at each pin

Total of all pins

Ta=-20 to +70°C

15

10

Total output

current

ΣIOAL(1)

ΣIOAL(2)

ΣIOAL(3)

ΣIOAL(4)

Pd max

Port 7, PWM

Port 0

35

Port 1

25

Port C

15

Allowable power

dissipation

TQFP64J(7×7)

QIP64E(14 ×14)

185

410

mW

Operating ambient

temperature

Topr

Tstg

-20

-55

+70

°C

Storage ambient

temperature

+125

No.A0653-10/21

LC87F7032A

Recommended Operating Range at Ta = -20°C to +70°C, V 1 = V 2 = 0V

SS

Specification

Parameter

Symbol

Pins

Conditions

V

[V]

min

typ max

unit

DD

Operating

V

(1)

V

1=V 2=V2

DD

0.75µs≤tCYC≤200µs

3.0

3.6

DD

supply voltage

range

(2)

DD

0.75µs≤tCYC≤200µs

expect on-board write

Keep RAM and register data in

HOLD mode.

2.4

Supply voltage

range in hold

mode

VHD

V

1

DD

2.2

3.6

Input high

voltage

V

(1)

• Ports 1, 71 to 73

• Port 70

Output disable

IH

0.3V

DD

2.4 to 3.6

V

DD

+0.7

input/interrupt

• Ports 0, C

• PWM

V

(2)

Output disable

0.3V

DD

IH

DD

+0.7

V

(3)

Port 70

2.4 to 3.6

0.9V

V

DD

Watchdog timer

RES

XT1, CF1,

V

(4)

0.75V

DD

Input low

Voltage

(1)

• Ports 1, 71 to 73

• Port 70

Output disable

IL

2.4 to 3.6

V

0.2V

SS

DD

input/interrupt

• Ports 0, C

• PWM

V

(2)

Output disable

IL

0.2V

0.8V

SS

DD

V

(3)

Port 70

IL

2.4 to 3.6

V

SS

Watchdog timer

-1.0

RES

V

(4)

XT1, CF1,

0.25V

IL

SS

DD

Operation

cycle time

External

tCYC

0.75

0.1

200

µs

FEXCF(1)

CF1

• CF2 open

4

8

system clock

frequency

Oscillation

frequency

range

• system clock divider: 1/1

• external clock DUTY=50±5%

4MHz ceramic resonator

oscillation

0.1

MHz

FmCF

CF1, CF2

2.4 to 3.6

4

See Fig. 1.

(Note2-1)

FmRC

FsX’tal

RC oscillation target:

0.3

0.5

0.7

V

=3.00V, Ta=25°C

DD

XT1, XT2

32.768kHz crystal resonator

oscillation

KHz

2.4 to 3.6

32.768

See Fig. 2.

Note 2-1: The parts value of oscillation circuit is shown in table 1 and table 2.

No.A0653-11/21

LC87F7032A

Electrical Characteristics at Ta = -20°C to +70°C, V 1 = V 2= 0V

SS

Specification

typ max

Parameter

Symbol

Pins

Conditions

V

[V]

min

unit

DD

High level input

current

I

(1)

IH

• Ports 0, 1, 7

• Port C, PWM

• Output disabled

• Pull-up resister OFF.

RES

•

• V =V

IN DD

2.4 to 3.6

1

(Including OFF state leak current

of the output Tr.)

I

(2)

IH

XT1, XT2

CF1

When configured as an input port

2.4 to 3.6

1

8

V

=V

IN DD

I

(3)

IH

=V

IN DD

µA

Low level input

current

(1)

IL

• Ports 0, 1, 7

• Port C, PWM

• Output disabled

• Pull-up resister OFF.

RES

•

• V =V

IN SS

2.4 to 3.6

-1

(Including OFF state leak current

of the output Tr.)

I

(2)

IL

XT1, XT2

CF1

When configured as an input port

2.4 to 3.6

3.0 to 3.6

-1

V

I

=V

IN SS

(3)

IL

=V

-8

IN SS

High level output

voltage

V

(1)

(2)

(3)

(4)

Ports 0, 1, 7

CMOS

=-0.4mA

V

DD

-0.4

OH

output option

I

=-0.2mA

=-0.1mA

=-1.6mA

=-0.8mA

V

DD

-0.4

OH

2.4 to 3.6

3.0 to 3.6

2.4 to 3.6

Port C

PWM

V

DD

-0.4

V

DD

-0.4

V

DD

-0.4

Low level output

voltage

V

(1)

(2)

(3)

(4)

(5)

Ports 0, 1, 7,PWM

P00, P01

I

=1.6mA

=0.8mA

=5.0mA

=2.5mA

=0.1mA

3.0 to 3.6

2.4 to 3.6

3.0 to 3.6

2.4 to 3.6

0.4

OL

V

Port C

LCD output voltage

regulation

VODLS

S0 to S23

=0mA

O

V1, V2, V3

2.4 to 3.6

0

±0.2

LCD level output

VODLC

COM0 to COM3

I =0mA

O

V1, V2, V3

0

±0.2

200

LCD level output

Resistance of

Rpu

• Ports 0, 1, 7

• Ports 1, 7

V

=0.9V

OH

DD

2.4 to 3.6

25

50

kΩ

pull-up MOS Tr.

Hysterisis voltage

VHYS(1)

CP

0.1V

V

DD

10

RES

•

Pin capacitance

All pins

• All other terminals connected to

V

.

SS

2.4 to 3.6

pF

• f=1MHz

• Ta=25°C

No.A0653-12/21

LC87F7032A

Serial I/O Characteristics at Ta = -20°C to +70°C, V 1 = V 2= 0V

SS

1. SIO0 Serial I/O Characteristics (Note 4-1-1)

Specification

Parameter

Frequency

Symbol

tSCK(1)

Pin/Remarks

SCK0(P12)

Conditions

V

min

typ

max

unit

DD

See Fig. 6.

2

1

Low level

tSCKL(1)

tSCKH(1)

tSCKHA(1)

pulse width

High level

pulse width

2.4 to 3.6

tCYC

• Continuous data transmission/

reception mode

4

• See Fig. 6.

(Note 4-1-2)

Frequency

tSCK(2)

SCK0(P12)

• CMOS output selected

• See Fig. 6.

4/3

Low level

tSCKL(2)

tSCKH(2)

tSCKHA(2)

1/2

pulse width

High level

pulse width

tSCK

tCYC

2.4 to 3.6

• Continuous data transmission/

reception mode

tSCKH(2)

+(10/3)

tCYC

tSCKH(2)

+2tCYC

• CMOS output selected

• See Fig. 6.

Data setup time

Data hold time

tsDI(1)

thDI(1)

tdD0(1)

tdD0(2)

tdD0(3)

SB0(P11),

SI0(P11)

• Must be specified with respect to

rising edge of SIOCLK.

• See Fig. 6.

2.4 to 3.6

0.03

Output

SO0(P10),

SB0(P11)

• Continuous data transmission/

reception mode

(

1/3)tCYC

+0.05

delay time

µs

(Note 4-1-3)

• Synchronous 8-bit mode

(Note 4-1-3)

1tCYC

+0.05

(Note 4-1-3)

(1/3)tCYC

+0.05

2.4 to 3.6

Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.

Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is

"H" to the first negative edge of the serial clock must be longer than tSCKHA.

Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of

output state change in open drain output mode. See Fig. 6.

No.A0653-13/21

LC87F7032A

2. SIO1 Serial I/O Characteristics (Note 4-2-1)

Specification

Parameter

Frequency

Symbol

tSCK(3)

Pin/Remarks

SCK1(P15)

Conditions

V

min

typ

max

unit

DD

See Fig. 6.

2

1

2

Low level

tSCKL(3)

tSCKH(3)

tSCK(4)

tSCKL(4)

tSCKH(4)

tsDI(2)

2.4 to 3.6

pulse width

High level

pulse width

Frequency

tCYC

SCK1(P15)

• CMOS output selected

• See Fig. 6.

Low level

pulse width

2.4 to 3.6

1/2

tSCK

High level

pulse width

Data setup time

SB1(P14),

SI1(P14)

• Must be specified with respect to

rising edge of SIOCLK.

• See Fig. 6.

2.4 to 3.6

0.03

Data hold time

thDI(2)

tdD0(4)

µs

Output delay

time

SO1(P13),

SB1(P14)

• Must be specified with respect to

falling edge of SIOCLK.

• Must be specified as the time to

the beginning of output state

change in open drain output

mode.

(1/3)tCYC

+0.05

2.4 to 3.6

• See Fig. 6.

Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.

Pulse Input Conditions at Ta = -20°C to +70°C, V 1 = V 2= 0V

SS SS

Specification

typ max

Parameter

Symbol

Pins

Conditions

V

[V]

min

unit

tCYC

µs

DD

High/low

level pulse

width

tPIH(1)

tPIL(1)

INT0(P70),

INT1(P71),

INT2(P72)

INT3(P73)

• Condition that interrupt is accepted

• Condition that event input to timer 0 is

accepted

2.4 to 3.6

1

2

tPIH(2)

tPIL(2)

• Condition that interrupt is accepted

• Condition that event input to timer 0 is

accepted

(Noise rejection ratio is 1/1.)

tPIH(3)

tPIL(3)

INT3(P73)

• Condition that interrupt is accepted

• Condition that event input to timer 0 is

accepted

(Noise rejection ratio is

1/32.)

64

tPIH(4)

tPIL(4)

INT3(P73)

• Condition that interrupt is accepted

• Condition that event input to timer 0 is

accepted

(Noise rejection ratio is

1/128.)

2.4 to 3.6

256

200

RES

tPIL(6)

• Condition that reset is accepted

No.A0653-14/21

LC87F7032A

AD Converter Characteristics at Ta = -20°C to +70°C, V 1 = V 2= 0V

SS

Specification

typ. max.

Parameter

Symbol

Pin/Remarks

Conditions

V

[V]

min.

unit

bit

DD

Resolution

N

AN0(P00) to

AN4(P04),

AN5(P70) to

AN8(P73)

8

Absolute

accuracy

Conversion

time

ET

(Note 6-1)

±1.5

LSB

tCAD

AD conversion time=32×tCYC

24

320

(tCYC=

10µs)

640

(When ADCR2=0) (Note 6-2)

(tCYC=

0.75µs)

48

µs

AD conversion time 64×tCYC

(When ADCR2=1) (Note 6-2)

(tCYC=

0.75µs)

(tCYC=

10µs)

Analog input

voltage range

Analog port

input current

VAIN

V

SS

DD

IAINH

IAINL

VAIN=V

DD

1

µA

VAIN=V

SS

-1

Note 6-1: The quantization error ( 1/2 LSB) is excluded from the absolute accuracy value.

Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till

the complete digital value corresponding to the analog input value is loaded in the required register.

Consumption Current Characteristics at Ta = -20°C to +70°C, V 1 = V 2= 0V

SS

Specification

Parameter

Symbol

Pins

Conditions

V

[V]

min

typ max

unit

DD

Normal mode

consumption

current

IDDOP(1)

V

1=

• FmCF=4MHz ceramic resonator oscillation

• FmX’tal=32.768kHz crystal oscillation

• System clock: CF 4MHz oscillation

• Internal RC oscillation stopped.

• Divider: 1/1

DD

2=

DD

V2

2.4 to 3.6

1.7

4.2

1.4

(Note 7-1)

IDDOP(2)

• FmCF=1MHz ceramic resonator oscillation

• FmX’tal=32.768kHz crystal oscillation

• System clock: CF 1MHz oscillation

• Internal RC oscillation stopped.

• Divider: 1/1

0.6

mA

IDDOP(3)

IDDOP(4)

IDDOP(5)

• FmCF=0Hz (No oscillation)

• FmX’tal=32.768kHz crystal oscillation

• System clock: RC oscillation

• Divider: 1/1

2.4 to 3.6

0.4

0.3

0.9

0.6

• FmCF=0Hz (No oscillation)

• FmX’tal=32.768kHz crystal oscillation

• System clock: RC oscillation

• Divider: 1/2

• FmCF=0Hz (No oscillation)

• FmX’tal=32.768kHz crystal oscillation

• System clock: variable

2.4 to 3.6

20

15

59

45

RC oscillation 1MHz

• Divider: 1/1

µA

IDDOP(6)

• FmCF=0Hz (No oscillation)

• FmX’tal=32.768kHz crystal oscillation

• System clock: 32.768kHz

• Internal RC oscillation stopped.

• Divider: 1/2

2.4 to 3.6

Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored.

Continued on next page.

No.A0653-15/21

LC87F7032A

Continued from preceding page.

Specification

typ max

Parameter

Symbol

Pins

1=

Conditions

V

[V]

min

unit

DD

HALT mode

consumption

current

IDDHALT(1)

V

HALT mode

DD

2=V2

DD

• FmCF=4MHz Ceramic resonator oscillation

• FmX’tal=32.768kHz crystal oscillation

• System clock: CF 4MHz oscillation

• Internal RC oscillation stopped.

• Divider: 1/1

2.4 to 3.6

0.8

2.1

1.4

(Note 7-1)

IDDHALT(2)

HALT mode

• FmCF=1MHz Ceramic resonator oscillation

• FmX’tal=32.768kHz crystal oscillation

• System clock:CF 1MHz oscillation

• Internal RC oscillation stopped.

• Divider: 1/1

2.4 to 3.6

0.3

mA

IDDHALT(3)

IDDHALT(4)

IDDHALT(5)

IDDHALT(6)

HALT mode

• FmCF=0Hz(Oscillation stop)

• FmX’tal=32.768kHz crystal oscillation

• System clock: RC oscillation

• Divider: 1/1

2.4 to 3.6

0.20

0.16

7.5

0.5

0.4

32

HALT mode

• FmCF=0Hz(Oscillation stop)

• FmX’tal=32.768kHz crystal oscillation

• System clock: RC oscillation

• Divider: 1/2

HALT mode

• FmCF=0Hz(Oscillation stop)

• FmX’tal=32.768kHz crystal oscillation

• System clock: variable RC oscillation 1MHz

• Divider: 1/1

HALT mode

• FmCF=0Hz(Oscillation stop)

• FmX’tal=32.768kHz crystal oscillation

• System clock: 32.768kHz

• Internal RC oscillation stopped.

• Divider: 1/2

2.4 to 3.6

5.5

27

µA

HOLD mode

consumption

current

IDDHOLD(1)

IDDHOLD(2)

HOLD mode

• CF1=V

DD

or open

2.4 to 3.6

0.03

3.8

10

24

(when using external clock)

Date/time clock

Timer HOLD

mode

HOLD mode

consumption

current

• CF1=V or open

DD

(when using external clock)

• FmX’tal=32.768kHz crystal oscillation

Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored.

No.A0653-16/21

LC87F7032A

F-ROM Programming Characteristics at Ta = +10°C to +55°C, V 1 = V 2= 0V

SS SS

Specification

Parameter

Symbol

Pin/Remarks

Conditions

V

[V]

min

typ max

unit

mA

DD

Onboard

IDDFW(1)

V

1

• 128-byte programming

• Erasing current included

DD

programming

current

3.0 to 3.6

15

40

Programming

time

tFW(1)

• 128-byte programming

• Erasing current included

• Time for setting up 128-byte data is

excluded.

20

40

ms

UART (Full Duplex) Operating Conditions at Ta = +20°C to +70°C, V 1 = V 2= 0V

SS

Specification

Parameter

Symbol

Pin/Remarks

Conditions

VDD[V]

min.

16/3

typ.

max.

8192/3

unit

Transfer rate

UBR

UTX(S22),

URX(S23)

2.4 to 3.6

tCYC

Data length: 7, 8, and 9 bits (LSB first)

Stop bits:

1 bit (2-bit in continuous data transmission)

Parity bits: None

Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H)

Start bit

Stop bit

End of

transmission

Start of

transmission

Transmit data (LSB first)

UBR

Example of 8-bit Data Reception Mode Processing (Receive Data=55H)

Stop bit

Start bit

Receive data (LSB first)

End of

reception

Start of

reception

UBR

No.A0653-17/21

LC87F7032A

Main System Clock Oscillation Circuit Characteristics

The characteristics in the table bellow is based on the following conditions:

Use the standard evaluation board SANYO has provided.

Use the peripheral parts with indicated value externally.

The peripheral parts value is a recommended value of oscillator manufacturer

Table 1. Main system clock oscillation circuit characteristics using ceramic resonator

Operating

Oscillation

Circuit parameters

supply voltage

range

stabilizing time

Frequency

Manufacturer

Type

Oscillator

Notes

C1

C2

Rd1

typ

max

[ms]

[V]

[pF]

(15)

[pF]

[Ω]

[ms]

SMD

Lead

CSTCR4M00G53-R0

CSTLS4M00G53-B0

(15)

1k

2.4 to 3.6

0.2

0.6

Built in

C1, C2

4.00MHz

Murata

(15)

2.2k

The oscillation stabilizing time is a period until the oscillation becomes stable after V

minimum operating voltage. (See Fig. 4.)

becomes higher than

DD

Subsystem Clock Oscillator Circuit Characteristics

The characteristics in the table bellow is based on the following conditions:

Use the standard evaluation board SANYO has provided.

Use the peripheral parts with indicated value externally.

The peripheral parts value is a recommended value of oscillator manufacturer

Table 2 Subsystem Clock Oscillation Circuit Characteristics Using Crystal Oscillator

Operating

Oscillation

Circuit Constant

supply

Stabilization Time

Frequency

Manufacturer

Oscillator

Notes

voltage range

C3

C4

Rf

Rd2

typ

[s]

max

[s]

[V]

[pF]

[Ω]

Applicable

32.768kHz

Epson Toyocom

MC-146

3

Open

0

2.4 to 3.6

1

3

CL value=7.0pF

The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which

starts the sub-clock oscillation or after releasing the HOLD mode. (See Fig. 4.)

Note: Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the

oscillation pins as possible with the shortest possible pattern length.

CF2

CF1

XT1

XT2

Rd1

C2

Rf

Rd2

C4

CF

C1

C3

X’tal

Figure 1 Ceramic Oscillator Circuit

Figure 2 Crystal Oscillator Circuit

0.5V

DD

Figure 3 AC Timing Measurement Point

No.A0653-18/21

LC87F7032A

V

DD

Power supply

limit

OV

Reset time

RES

Internal RC

Resonator oscillation

tmsCF

CF1, CF2

tmsX’tal

XT1, XT2

Operating mode

Reset

Unfixed

Instruction execution mode

Reset Time and Oscillation Stabilizing Time

Without HOLD

Release

HOLD reset signal

HOLD reset signal VALID

Internal RC

Resonator oscillation

tmsCF

CF1, CF2

tmsX’tal

XT1, XT2

Operation mode

HOLD

HALT

HOLD Release Signal and Oscillation Stable Time

Figure 4 Oscillation Stabilizing Time

No.A0653-19/21

LC87F7032A

V

DD

R

C

RES

Note:

Select C

and R value to assure that at least 200µs

RES

reset time is generated after the V

the minimum operating voltage.

becomes higher than

DD

RES

Figure 5 Reset Circuit

SIOCLK:

DATAIN:

DI0

DI1

DI2

DI3

DI4

DI5

DI6

DI7

DI8

DATAOUT:

DO0

DO1

DO2

DO3

DO4

DO5

DO6

DO7

DO8

Data RAM

transmission period

(SIO0 only)

tSCK

tSCKH

thDI

tSCKL

SIOCLK:

DATAIN:

tsDI

tdDO

DATAOUT:

Data RAM

transmission period

(SIO0 only)

tSCKL

tSCKHA

SIOCLK:

DATAIN:

tsDI

thDI

tdDO

DATAOUT:

Figure 6 Serial Input/Output Wave Form

tPIL

tPIH

Figure 7 Pulse Input Timing Condition

No.A0653-20/21

LC87F7032A

SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using

products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition

ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.

products described or contained herein.

SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all

semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or

malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise

to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt

safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not

limited to protective circuits and error prevention circuits for safe design, redundant design, and structural

design.

In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are

controlled under any of applicable local export control laws and regulations, such products may require the

export license from the authorities concerned in accordance with the above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or

mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,

without the prior written consent of SANYO Semiconductor Co.,Ltd.

Any and all information described or contained herein are subject to change without notice due to

product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the

SANYO Semiconductor Co.,Ltd. product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed

for volume production.

Upon using the technical information or products described herein, neither warranty nor license shall be granted

with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third

party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's

intellctual property rights which has resulted from the use of the technical information and products mentioned

above.

This catalog provides information as of February, 2007. Specifications and information herein are subject

to change without notice.

PS

No.A0653-21/21


型号：	LC87F7032A
厂家：	SANYO SEMICON DEVICE
描述：	CMOS IC FROM 32K byte, RAM 1024 byte on-chip 8-bit 1-chip Microcontroller CMOS集成电路从32K字节， RAM 1024字节的片上8位单芯片微控制器微控制器
文件：	总21页 (文件大小：132K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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