LC75857E-E [ONSEMI]
Duty LCD Driver with Key Input Function;
| 型号： | LC75857E-E |
| 厂家： | 
ONSEMI |
| 描述： | Duty LCD Driver with Key Input Function CD |
| 文件： | 总42页 (文件大小：738K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC75857E, LC75857W
1/3, 1/4-Duty LCD Driver
with Key Input Function
Overview
The LC75857E and LC75857W are 1/3 duty and 1/4 duty LCD display
drivers that can directly drive up to 164 segments and can control up to four
general-purpose output ports. These products also incorporate a key scan
circuit that accepts input from up to 30 keys to reduce printed circuit board
wiring.
www.onsemi.com
Features
Key input function for up to 30 keys
(A key scan is performed only when a key is pressed.)
1/3 duty and 1/4 duty drive schemes can be controlled from serial data.
1/2 bias and 1/3 bias drive schemes can be controlled from serial data.
Capable of driving up to 126 segments using 1/3 duty and up to 164
segments using 1/4 duty.
PQFP64 14x14 / QIP64E
[LC75857E]
Sleep mode and all segments off functions that are controlled from serial
data.
Switching between key scan output and segment output can be controlled
from the serial data.
The key scan operation enabled/disabled state can be controlled from the
serial data.
Switching between segment output port and general-purpose output port
can be controlled from serial data.
SPQFP64 10x10 / SQFP64
[LC75857W]
The common and segment output waveform frame frequency can be
controlled from the serial data.
Switching between RC oscillator mode and external clock mode can be
controlled from the serial data.
Serial data I/O supports CCB* format communication with the system
controller.
Direct display of display data without the use of a decoder provides high
generality.
Independent VLCD for the LCD driver block.
(When the logic block supply voltage VDD is in the range 3.6 to 6.0 V,
VLCD can be set to a voltage in the range 0.75 VDD to 6.0 V, and when
VDD is in the range 2.7 to 3.6 V, VLCD can be set to a voltage in the range
2.7 to 6.0 V.)
Provision of an on-chip voltage-detection type reset circuit prevents
incorrect displays.
* Computer Control Bus (CCB) is an ON Semiconductor’s original bus format and
the bus addresses are controlled by ON Semiconductor.
ORDERING INFORMATION
See detailed ordering and shipping information on page 42 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
July 2017 - Rev. 1
1
Publication Order Number :
LC75857E_W/D
LC75857E, LC75857W
Specifications
Absolute Maximum Ratings at Ta=25°C, V =0V
SS
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
Unit
V
V
max
max
V
V
–0.3 to +7.0
–0.3 to +7.0
–0.3 to +7.0
DD
DD
V
LCD
LCD
V
IN
V
IN
V
IN
1
2
3
CE, CL, DI
OSC,TEST
Input voltage
–0.3 to V +0.3
V
DD
V
1, V
2, KI1 to KI5
–0.3 to V
+0.3
LCD
LCD
LCD
V
V
V
1
DO
–0.3 to +7.0
–0.3 to V +0.3
OUT
OUT
OUT
Output voltage
2
3
OSC
V
DD
S1 to S42, COM1 to COM4, KS1 to KS6, P1 to P4
–0.3 to V
+0.3
300
3
LCD
I
I
I
I
1
S1 to S42
μA
mA
OUT
OUT
OUT
OUT
2
COM1 to COM4
KS1 to KS6
P1 to P4
Output current
3
4
1
5
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Ta = 85°C
200
mW
°C
–40 to +85
Tstg
–55 to +125
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Allowable Operating Ranges at Ta = –40 to +85°C, V =0V
SS
Ratings
typ
Parameter
Symbol
Conditions
Unit
V
min
2.7
0.75 V
max
6.0
V
DD
V
V
V
V
V
DD
Supply voltage
Input voltage
: V = 3.6 V to 6.0 V
6.0
6.0
LCD
LCD
LCD
LCD
DD
DD
V
LCD
: V = 2.7 V to 3.6 V
DD
2.7
V
V
1
1
2
2/3 V
1/3 V
V
V
LCD
LCD
LCD
LCD
V
2
LCD
LCD
6.0
V
1
CE, CL, DI
0.8 V
DD
IH
IH
IH
Input high level voltage
Input low level voltage
V
2
KI1 to KI5
0.6 V
V
V
LCD
LCD
V
3
OSC: External clock mode
CE, CL, DI
0.7 V
V
DD
0
DD
DD
V 1
IL
0.2 V
V 2
IL
KI1 to KI5
0
0
0.2 V
V
LCD
V 3
IL
OSC: External clock mode
OSC: RC oscillator mode
OSC: RC oscillator mode
OSC: RC oscillator mode
OSC: External clock mode
OSC: External clock mode
CL, DI
0.3 V
DD
Recommended RC oscillator external resistor
Recommended RC oscillator external capacitor
Guaranteed RC oscillator operating range
External clock frequency
External clock duty
R
39
k
pF
kHz
kHz
%
OSC
OSC
OSC
C
1000
38
f
19
19
30
76
76
70
f
:Figure 4
38
CK
D
:Figure 4
50
CK
ds
Data setup time
t
:Figures 2,3
:Figures 2,3
:Figures 2,3
:Figures 2,3
:Figures 2,3
:Figures 2,3
:Figures 2,3
:Figures 2,3
:Figures 2,3
:Figures 2,3
:Figures 2,3
160
160
160
160
160
160
160
ns
Data hold time
t
CL, DI
ns
dh
CE wait time
t
CE, CL
ns
cp
CE setup time
t
CE, CL
ns
cs
CE hold time
t
CE, CL
ns
ch
High level clock pulse width
Low level clock pulse width
Rise time
tø
CL
ns
H
tø
CL
ns
L
t
r
CE, CL, DI
160
160
ns
Fall time
t
CE, CL, DI
ns
f
1
1
DO output delay time
DO rise time
t
DO R =4.7 k, C =10pF *
1.5
1.5
μs
dc
PU
L
t
DO R =4.7 k, C =10pF *
μs
dr
PU
L
Note: *1. Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor R and the load capacitance C .
PU
L
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
www.onsemi.com
2
LC75857E, LC75857W
Electrical Characteristics for the Allowable Operation Ranges
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
VH1
VH2
CE, CL, DI
KI1 to KI5
0.1 VDD
0.1 VLCD
2.2
Hysteresis
V
V
Power-down detection voltage
Input high level current
VDET
2.0
2.4
I
IH1
IH2
CE, CL, DI: VI = 6.0 V
OSC: VI = VDD External clock mode
CE, CL, DI: VI = 0 V
5.0
5.0
μA
I
I
I
IL1
IL2
–5.0
–5.0
Input low level current
Input floating voltage
Pull-down resistance
Output off leakage current
μA
V
OSC: VI = 0 V External clock mode
KI1 to KI5
VIF
0.05 VLCD
250
KI1 to KI5: VLCD = 5.0 V
KI1 to KI5: VLCD = 3.0 V
DO: VO = 6.0 V
50
100
200
RPD
k
100
500
IOFFH
6.0
μA
KS1 to KS6: IO = –500 μA VLCD = 3.6 to 6.0 V VLCD – 1.0 VLCD – 0.5 VLCD – 0.2
KS1 to KS6: IO = –250 μA VLCD = 2.7 to 3.6 V VLCD – 0.8 VLCD – 0.4 VLCD – 0.1
V
OH1
Output high level voltage
V
V
V
OH2
OH3
OH4
P1 to P4: IO = –1 mA
VLCD – 0.9
VLCD – 0.9
VLCD – 0.9
0.2
V
V
S1 to S42: IO = –20 μA
COM1 to COM4: IO = –100 μA
KS1 to KS6: IO = 25 μA VLCD = 3.6 to 6.0 V
KS1 to KS6: IO = 12.5 μA VLCD = 2.7 to 3.6 V
P1 to P4: IO = 1 mA
0.5
0.4
1.5
1.2
V
OL1
0.1
V
V
V
OL2
OL3
OL4
0.9
Output low level voltage
S1 to S42: IO = 20 μA
0.9
COM1 to COM4: IO = 100 μA
DO: IO = 1 mA
0.9
VOL
5
0.1
0.5
V
MID1
COM1 to COM4: 1/2 bias, IO = ±100 μA
S1 to S42: 1/3 bias,IO = ±20 μA
S1 to S42: 1/3 bias, IO = ±20 μA
COM1 to COM4: 1/3 bias,IO = ±100 μA
COM1 to COM4: 1/3 bias,IO = ±100 μA
OSC: ROSC = 39 k , COSC = 1000 pF
VDD :Sleep mode
1/2 VLCD – 0.9
2/3 VLCD – 0.9
1/3 VLCD – 0.9
2/3 VLCD – 0.9
1/3 VLCD – 0.9
30.4
1/2 VLCD + 0.9
2/3 VLCD + 0.9
1/3 VLCD + 0.9
2/3 VLCD + 0.9
1/3 VLCD + 0.9
45.6
VMID
2
3
2
Output middle level voltage *
VMID
V
V
MID4
VMID
fosc
5
Oscillator frequency
Current drain
38
kHz
I
DD1
DD2
100
I
VDD: VDD = 6.0 V, output open,fosc = 38 kHz
VLCD : Sleep mode
300
600
ILCD1
5
μA
VLCD: VLCD = 6.0 V, output open, 1/2 bias,
fosc = 38 kHz
I
LCD2
100
60
200
120
VLCD: VLCD = 6.0 V, output open, 1/3 bias,
fosc = 38 kHz
ILCD3
Nete: *2. Excluding the bias voltage generation divider resistor built into VLCD1 and VLCD2. (See Figure 1.)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
3
LC75857E, LC75857W
VLCD
VLCD1
VLCD2
To the common segment driver
Excluding these registors.
Figure 1
1. Serial data I/O timing when CL is stopped at the low level
VIH1
CE
VIL1
t ø H
t ø L
tf
VIH1
50%
VIL1
CL
DI
tr
tch
tcp tcs
VIH1
VIL1
tds
tdh
tdc
tdr
DO
D0
D1
Figure 2
2. Serial data I/O timing when CL is stopped at the high level
VIH1
CE
VIL1
t ø L
t ø H
tr
VIH1
50%
VIL1
CL
DI
tf
tcp tcs
tch
VIH1
VIL1
tds
tdh
DO
D0
D1
tdc
tdr
Figure 3
3. OSC pin clock timing in external clock mode
1
tCKH
tCKL
fCK =
DCK =
[kHz]
tCKH + tCKL
VIH3
50%
VIL3
OSC
tCKH
tCKH + tCKL
×100[%]
Figure 4
Page 4
LC75857E, LC75857W
Pin Assignments
48
33
49
32
KI1
KI2
KI3
KI4
KI5
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
VDD
VLCD
VLCD1
VLCD2
VSS
TEST
OSC
DO
LC75857E/W
CE
CL
DI
64
17
1
16
Top view
Page 5
LC75857E, LC75857W
Block Diagram
VLCD
VLCD1
VLCD2
VSS
SEGMENT DRIVER & LATCH
COMMON
DRIVER
TEST
OSC
CLOCK
GENERATOR
CONTROL
REGISTER
DO
SHIFT REGISTER
KEY BUFFER
KEY SCAN
CCB
INTERFACE
DI
CL
CE
VDD
VDET
Page 6
LC75857E, LC75857W
Pin Functions
Handling
when unused
Pin
Pin No.
Function
Active
—
I/O
O
S1/P1 to
S4/P4
S5 to S38
Segment outputs for displaying the display data transferred by serial data input.
The S1/P1 to S4/P4 pins can be used as general-purpose output ports under serial
data control.
1 to 4
OPEN
OPEN
5 to 38
COM1
to
COM3
COM4/S39
Common driver outputs
The frame frequency is fo [Hz]
42 to 40
39
—
—
O
O
The COM4/S39 pin can be used as a segment output in 1/3 duty.
Key scan outputs
Although normal key scan timing lines require diodes to be inserted in the timing lines
to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these
outputs will not be damaged by shorting when these outputs are used to form a key
matrix. The KS1/S40 to KS3/S42 pins can be used as segment outputs when so
specified by the control data.
KS1/S40
KS2/S41
KS3/S42
43
44
45
OPEN
KS4 to KS6
46 to 48
Key scan inputs
These pins have built-in pull-down resistors.
KI1 to KI5
OSC
49 to 53
60
H
I
GND
VDD
The OSC pin can be used to form an oscillator circuit with an external resistor and an
external capacitor. If external clock mode is selected with the control data, this pin is
used to input an external clock signal.
—
H
I/O
CE
CL
DI
62
63
64
I
I
I
Serial data interface connections to the controller. Note that DO, being an open-drain
output, requires a pull-up resistor.
CE :Chip enable
CL :Synchronization clock
DI :Transfer data
GND
—
DO :Output data
DO
61
59
—
—
O
I
OPEN
—
TEST
This pin must be connected to ground.
Used for applying the LCD drive 2/3 bias voltage externally. Must be connected to
VLCD2 when a 1/2 bias drive scheme is used.
VLCD
1
56
—
I
OPEN
Used for applying the LCD drive 1/3 bias voltage externally. Must be connected to
VLCD1 when a 1/2 bias drive scheme is used.
VLCD
2
57
54
—
—
I
OPEN
—
VDD
VLCD
VSS
Logic block power supply connection. Provide a voltage of between 2.7 and 6.0V.
—
LCD driver block power supply connection. A voltage in the range 0.75 × VDD to 6.0 V
must be provided when VDD is in the range 3.6 to 6.0 V, and a voltage in the range
2.7 V to 6.0 V must be provided when VDD is in the range 2.7 to 3.6 V.
55
58
—
—
—
—
—
—
Power supply connection. Connect to ground.
Page 7
LC75857E, LC75857W
Serial Data Input
1. 1/3 duty
(1) When CL is stopped at the low level
CE
CL
KC2 KSC
0
1
0
0
0
0
1
0
D1 D2
D41 D42
D83 D84
D125 D126
0
0
0
0
0
SP KC0 KC1
K0 K1 P0 P1 P2 SC DR DT FC0 FC1 FC2 0C
0
0
DI
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Control data
DD
DO
0
1
0
0
0
0
1
0
D43 D44
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
B3
Display data
B0 B1 B2
A0 A1 A2 A3
Fixed data
DD
0
1
0
0
0
0
1
0
D85 D86
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2
A0 A1 A2 A3
B3
Display data
Fixed data
DD
......
Note: B0 to B3, A0 to A3
CCB address
Direction data
................................
DD
Page 8
LC75857E, LC75857W
(2) When CL is stopped at the high level
CE
CL
KC2 KSC
0
1
0
0
0
0
1
0
D1 D2
Display data
D41 D42
0
0
0
0
0
SP KC0 KC1
K0 K1 P0 P1 P2 SC DR DT FC0 FC1 FC2 0C
0
0
DI
Control data
B0 B1 B2 B3 A0 A1 A2 A3
DD
DO
0
1
0
0
0
0
1
0
D43 D44
D83 D84
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
0
1
0
0
0
0
1
0
D85 D86
D125 D126
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
......
Note: B0 to B3, A0 to A3
CCB address
Direction data
................................
DD
............
..............
............................
CCB address
D1 to D126
SP
KC0 to KC2
42H
Display data
Normal mode/sleep mode control data
Key scan output state setting data
..............
..........................
......................
KSC
K0, K1
Key scan operation enabled/disabled state setting data
Key scan output/segment output selection data
Segment output port/general-purpose output port selection data
Segment on/off control data
1/2 bias or 1/3 bias drive selection data
1/3 duty or 1/4 duty drive selection data
Common and segment output waveform frame frequency setting data
RC oscillator mode/external clock mode switching selection data
..................
P0 to P2
............................
............................
............................
..............
SC
DR
DT
FC0 to FC2
............................
OC
Page 9
LC75857E, LC75857W
2. 1/4duty
(1) When CL is stopped at the low level
CE
CL
KC2 KSC
D40 D41 D42 D43 D44
0
0
0
0
SP KC0 KC1
K0 K1 P0 P1 P2 SC DR DT FC0 FC1 FC2 0C
0
0
1
1
0
0
1
0
0
0
0
1
0
D1
DI
Control data
Display data
B0 B1 B2 B3 A0 A1 A2 A3
DD
DO
D84
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
1
0
D45
B0 B1 B2 B3 A0 A1 A2 A3
Display data
DD
DD
DD
Fixed data
D124
0
0
0
0
0
1
0
0
0
0
1
0
D85
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
D164
0
0
0
0
0
1
0
0
0
0
1
0
D125
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
......
Note: B0 to B3, A0 to A3
CCB address
Direction data
................................
DD
Page 10
LC75857E, LC75857W
(2) When CL is stopped at the high level
CE
CL
KC2 KSC
D40 D41 D42 D43 D44
0
SP KC0 KC1
K0 K1 P0 P1 P2 SC DR DT FC0 FC1 FC2 0C
0
0
1
0
1
DI
0
1
0
0
0
0
1
0
D1
D45
D85
D125
Display data
Control data
B0 B1 B2 B3 A0 A1 A2 A3
DD
DO
D84
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
D124
0
0
0
0
1
0
1
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
Fixed data
Display data
DD
D164
0
0
0
0
1
0
1
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
......
Note: B0 to B3, A0 to A3
CCB address
Direction data
................................
DD
............
..............
............................
CCB address
D1 to D164
SP
KC0 to KC2
42H
Display data
Normal mode/sleep mode control data
Key scan output state setting data
..............
..........................
......................
KSC
K0, K1
Key scan operation enabled/disabled state setting data
Key scan output/segment output selection data
Segment output port/general-purpose output port selection data
Segment on/off control data
1/2 bias or 1/3 bias drive selection data
1/3 duty or 1/4 duty drive selection data
Common and segment output waveform frame frequency setting data
RC oscillator mode/external clock mode switching selection data
..................
P0 to P2
............................
............................
............................
..............
SC
DR
DT
FC0 to FC2
............................
OC
Page 11
LC75857E, 75857W
Control Data Functions
1. SP : Normal mode/sleep mode control data
This control data bit switches the IC between normal mode and sleep mode.
OSC pin state
Common and segment
Key scan
General-purpose
output port states
SP Mode
RC oscillator mode
External clock mode
pin output states
operating state
0
1
Normal
sleep
Oscillator operating
External clock signal accepted
LCD drive waveforms
are output
Oscillator stopped
Acceptance of the external
clock signal is disabled.
The state can be set The state can be set
(The oscillator operates
L (VSS)
during key scan operations.) (The external clock signal is accepted
during key scan operations)
Note:
See the descriptions of the KC0 to KC2, KSC, K0, K1, and P0 to P2 bits in the control data for details on setting the key scanoperating state and
setting the general-purpose output port state.
2. KC0 to KC2 : Key scan output state setting data
These control data bits set the states of the key scan output pins KS1 to KS6.
Control data
Output pin states during key scan standby
KC0
0
KC1
0
KC2
0
KS1
H
L
KS2
H
H
L
KS3
H
H
H
L
KS4
H
KS5
H
KS6
H
0
0
1
H
H
H
0
1
0
L
H
H
H
0
1
1
L
L
H
H
H
1
0
0
L
L
L
L
H
H
1
0
1
L
L
L
L
L
H
1
1
0
L
L
L
L
L
L
Note:
This assumes that the KS1/S40 to KS3/S42 output pins are selected for key scan output.
Also note that key scan output signals are not output from output pins that are set to the low level.
3. KSC : Key scan operation enabled/disabled state setting data
This control data bit enables or disables key scan operation.
KSC
0
Key scan operating state
Key scan operation enabled
(A key scan operation is performed if any key on the lines corresponding to KS1 to KS6 pin which is set high is pressed .)
Key scan operation disabled
1
(No key scan operation is performed, even if any of the keys in the key matrix are pressed. If this state is set up, the key data
is forcibly reset to 0 and the key data read request is also cleared. (DO is set high.))
4. K0, K1 : Key scan output /segment output selection data
These control data bits switch the functions of the KS1/S40 to KS3/S42 output pins between key scan output and
segment output.
Control data
K0 K1
Output pin state
KS2/S41
KS2
Maximum number of
input keys
KS1/S40
KS1
KS3/S42
KS3
0
0
30
25
20
15
0
1
1
1
0
1
S40
KS2
KS3
S40
S41
KS3
S40
S41
S42
Note: KSn(n = 1 to 3) : Key scan output
Sn (n = 40 to 42): Segment output
Page 12
LC75857E, LC75857W
5. P0 to P2 : Segment output port/general-purpose output port selection data
These control data bits switch the functions of the S1/P1 to S4/P4 output pins between the segment output port and
the general-purpose output port.
Control data
Output pin state
P0
0
P1
0
P2
0
S1/P1
S1
S2/P2
S3/P3
S3
S4/P4
S4
S2
S2
P2
P2
P2
0
0
1
P1
S3
S4
0
1
0
P1
S3
S4
0
1
1
P1
P3
S4
1
0
0
P1
P3
P4
Note: Sn(n=1 to 4): Segment output port
Pn(n=1 to 4): General-purpose output port
The table below lists the correspondence between the display data and the output pins when these pins are selected to
be general-purpose output ports.
Corresponding display data
Output pin
1/3 duty
1/4 duty
S1/P1
S2/P2
S3/P3
S4/P4
D1
D1
D4
D5
D7
D9
D10
D13
For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output
port, the S4/P4 output pin will output a high level (V ) when the display data D13 is 1, and will output a low level
LCD
(Vss) when D13 is 0.
6. SC : Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
0
Display state
on
off
1
However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting
segment off waveforms from the segment output pins.
7. DR : 1/2 bias or 1/3 bias drive selection data
This control data bit switches between LCD 1/2 bias or 1/3 bias drive.
DR
0
Bias drive scheme
1/3 bias drive
1
1/2 bias drive
8. DT : 1/3 duty or 1/4 duty drive selection data
This control data bit switches between LCD 1/3 duty or 1/4 duty drive.
DT
0
Duty drive scheme
1/4 duty drive
Output pin state (COM4/S39)
COM4
S39
1
1/3 duty drive
Note: COM4: Common output
S39 : Segment output
Page 13
LC75857E, LC75857W
9. FC0 to FC2 : Common and segment output waveform frame frequency setting data
These control data bits set the common and segment output waveform frequency.
Control data
Frame frequency, fo (Hz)
FC0
0
FC1
0
FC2
0
f
f
f
f
f
OSC/768, fCK/768
OSC/576, fCK/576
OSC/384, fCK/384
OSC/288, fCK/288
OSC/192, fCK/192
0
0
1
0
1
0
0
1
1
1
0
0
10. OC : RC oscillator mode/external clock mode switching selection data
This control data bit selects the OSC pin function (RC oscillator mode or external clock mode).
OC
0
OSC pin function
RC oscillator mode
External clock mode
1
Note: If RC oscillator mode is selected, connect an external resistor Rosc and an external capacitor Cosc to the OSC pin.
Display Data and Output Pin Correspondence
1. 1/3 duty
Output pin
S1/P1
S2/P2
S3/P3
S4/P4
S5
COM1
D1
COM2
D2
COM3
D3
Output pin
S22
COM1
D64
COM2
D65
COM3
D66
D4
D5
D6
S23
D67
D68
D69
D7
D8
D9
S24
D70
D71
D72
D10
D13
D16
D19
D22
D25
D28
D31
D34
D37
D40
D43
D46
D49
D52
D55
D58
D61
D11
D14
D17
D20
D23
D26
D29
D32
D35
D38
D41
D44
D47
D50
D53
D56
D59
D62
D12
D15
D18
D21
D24
D27
D30
D33
D36
D39
D42
D45
D48
D51
D54
D57
D60
D63
S25
D73
D74
D75
S26
D76
D77
D78
S6
S27
D79
D80
D81
S7
S28
D82
D83
D84
S8
S29
D85
D86
D87
S9
S30
D88
D89
D90
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S31
D91
D92
D93
S32
D94
D95
D96
S33
D97
D98
D99
S34
D100
D103
D106
D109
D112
D115
D118
D121
D124
D101
D104
D107
D110
D113
D116
D119
D122
D125
D102
D105
D108
D111
D114
D117
D120
D123
D126
S35
S36
S37
S38
COM4/S39
KS1/S40
KS2/S41
KS3/S42
Note: This is for the case where the output pins S1/P1 to S4/P4, COM4/S74, KS1/S40 to KS3/S42 are selected for use as segment outputs.
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D31
0
D32
0
D33
0
The LCD segments for COM1, COM2 and COM3 are off.
The LCD segment for COM3 is on.
0
0
1
0
1
0
The LCD segment for COM2 is on.
0
1
1
The LCD segments for COM2 and COM3 are on.
The LCD segment for COM1 is on.
1
0
0
1
0
1
The LCD segments for COM1 and COM3 are on.
The LCD segments for COM1 and COM2 are on.
The LCD segments for COM1, COM2 and COM3 are on.
1
1
0
1
1
1
Page 14
LC75857E, LC75857W
2. 1/4 duty
Output pin
S1/P1
S2/P2
S3/P3
S4/P4
S5
COM1
D1
COM2
D2
COM3
D3
COM4
D4
Output pin
S22
COM1
COM2
D86
COM3
D87
COM4
D88
D85
D89
D5
D6
D7
D8
S23
D90
D91
D92
D9
D10
D14
D18
D22
D26
D30
D34
D38
D42
D46
D50
D54
D58
D62
D66
D70
D74
D78
D82
D11
D15
D19
D23
D27
D31
D35
D39
D43
D47
D51
D55
D59
D63
D67
D71
D75
D79
D83
D12
D16
D20
D24
D28
D32
D36
D40
D44
D48
D52
D56
D60
D64
D68
D72
D76
D80
D84
S24
D93
D94
D95
D96
D13
D17
D21
D25
D29
D33
D37
D41
D45
D49
D53
D57
D61
D65
D69
D73
D77
D81
S25
D97
D98
D99
D100
D104
D108
D112
D116
D120
D124
D128
D132
D136
D140
D144
D148
D152
D156
D160
D164
S26
D101
D105
D109
D113
D117
D121
D125
D129
D133
D137
D141
D145
D149
D153
D157
D161
D102
D106
D110
D114
D118
D122
D126
D130
D134
D138
D142
D146
D150
D154
D158
D162
D103
D107
D111
D115
D119
D123
D127
D131
D135
D139
D143
D147
D151
D155
D159
D163
S6
S27
S7
S28
S8
S29
S9
S30
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S31
S32
S33
S34
S35
S36
S37
S38
KS1/S40
KS2/S41
KS3/S42
Note: This is for the case where the output pins S1/P1 to S4/P4, KS1/S40 to KS3/S42 are selected for use as segment outputs.
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D41
0
D42
0
D43
0
D44
0
The LCD segments for COM1,COM2,COM3 and COM4 are off.
The LCD segment for COM4 is on.
0
0
0
1
0
0
1
0
The LCD segment for COM3 is on.
0
0
1
1
The LCD segments for COM3 and COM4 are on.
The LCD segment for COM2 is on.
0
1
0
0
0
1
0
1
The LCD segments for COM2 and COM4 are on.
The LCD segments for COM2 and COM3 are on.
The LCD segments for COM2,COM3 and COM4 are on.
The LCD segment for COM1 is on.
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
The LCD segments for COM1 and COM4 are on.
The LCD segments for COM1 and COM3 are on.
The LCD segments for COM1,COM3 and COM4 are on.
The LCD segments for COM1 and COM2 are on.
The LCD segments for COM1,COM2 and COM4 are on.
The LCD segments for COM1,COM2 and COM3 are on.
The LCD segments for COM1,COM2,COM3 and COM4 are on.
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Page 15
LC75857E, LC75857W
Serial Data Output
1. When CL is stopped at the low level
CE
CL
1
1
0
0
0
0
1
0
DI
B0 B1 B2 B3 A0 A1 A2 A3
X
KD1 KD2
KD27 KD28 KD29 KD30 SA
Output data
DO
X: don't care
Note: B0 to B3, A0 to A3······CCB address
2. When CL is stopped at the high level
CE
CL
1
1
0
0
0
0
1
0
DI
B0 B1 B2 B3 A0 A1 A2
A3
X KD1 KD2 KD3
KD28 KD29 KD30 SA
X
DO
Output data
X: don't care
Note: B0 to B3, A0 to A3······CCB address
......
CCB address
KD1 to KD30
SA
43H
Key data
Sleep acknowledge data
........
........................
Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data(SA) will be invalid.
Page 16
LC75857E, LC75857W
Output Data
1. KD1 to KD30 : Key data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and
one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the
relationship between those pins and the key data bits.
KI1
KI2
KI3
KI4
KI5
KS1/S40
KS2/S41
KS3/S42
KS4
KD1
KD2
KD3
KD4
KD5
KD6
KD7
KD8
KD9
KD10
KD15
KD20
KD25
KD30
KD11
KD16
KD21
KD26
KD12
KD17
KD22
KD27
KD13
KD18
KD23
KD28
KD14
KD19
KD24
KD29
KS5
KS6
When the KS1/S40 and KS2/S41 output pins are selected to be segment outputs by control data bits K0 and K1 and a
key matrix of up to 20 keys is formed using the KS3/S42,KS4 to KS6 output pins and the KI1 to KI5 input pins, the
KD1 to KD10 key data bits will be set to 0.
2. SA : Sleep acknowledge data
This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data
is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep
mode and 0 in normal mode.
Sleep Mode Functions
Sleep mode is set up by setting SP in the control data to 1. When sleep mode is set up, both the segment and the common
outputs will go to the low level. In RC oscillator mode (OC = 0), the oscillator on the OSC pin will stop (although it will
operate during key scan operations), and in external clock mode (OC = 1), the external clock signal reception on the OSC
pin will stop (although the clock signal will be received during key scan operations). Thus this mode reduces power
consumption. However, the S1/P1 to S4/P4 output pins can be used as general-purpose output ports under control of the
P0 to P2 bits in the control data even in sleep mode. Sleep mode is cancelled by setting SP in the control data to 0.
Page 17
LC75857E, LC75857W
Key Scan Operation Functions
1. Key scan timing
The key scan period is 288T(s). To reliably determine the on/off state of the keys, the LC75857E/W scans the keys
twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low
level on DO) 615T(s) after starting a key scan. If the key data dose not agree and a key was pressed at that point, it
scans the keys again. Thus the LC75857E/W cannot detect a key press shorter than 615T(s).
*3
*3
*3
*3
*3
*3
1
1
*3
*3
*3
*3
*3
*3
KS1
KS2
KS3
KS4
KS5
KS6
2
2
3
3
1
fosc
1
fCK
T=
=
4
4
5
5
6
6
Key on
576T[s]
Note: *3. These are set to the high or low level by the KC0 to KC2 bits in the control data. Key scan output signals are not output from pins that are set to the low level.
2. Normal mode, when key scan operations are enabled
•
The KS1 to KS6 pins are set to the high or low level by the KC0 to KC2 bits in the control data. (See the
description of the control data.)
•
When any key on the lines corresponding to KS1 to KS6 pin which is set high is pressed, a key scan is
performed. Keys are scanned until all keys are released. Multiple key presses are recognized by determining
whether multiple key data bits are set.
1
1
——
——
•
•
If a key is pressed for longer than 615 T (s) (Where T=
=
) the LC75857E/W outputs a key data read
fCK
fosc
request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data.
However, if CE is high during a serial data transfer, DO will be set high.
After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75857E/W
performes another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1
to 10 kΩ).
Key input 1
Key input 2
Key scan
615T[s]
615T[s]
615T[s]
CE
DI
Serial data transfer
(KSC = 0)
Serial data transfer
(KSC = 0)
Serial data transfer
Key address
Key address
Key address (43H)
(KSC = 0)
DO
Key data read
Key data read
Key data read
Key data read request
Key data read request
Key data read request
1
fosc
1
fCK
=
T=
Page 18
LC75857E, LC75857W
3. Sleep mode, when key scan operations are enabled
•
The KS1 to KS6 pins are set to the high or low level by the KC0 to KC2 bits in the control data. (See the
description of the control data.)
•
When any key on the lines corresponding to KS1 to KS6 pin which is set high is pressed, either the OSC pin
oscillator starts (if the IC is in RC oscillator mode) or the IC starts accepting the external clock signal (if the IC is
in external clock mode), a key scan is performed. Keys are scanned until all keys are released. Multiple key
presses are recoghized by determinig whether multiple key data bits are set.
1
1
•
•
•
If a key is pressed for longer than 615T(s)(Where T=
request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data.
However, if CE is high during a serial data transfer, DO will be set high.
=
) the LC75857E/W outputs a key data read
—— ——
fosc
fCK
After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75857E/W
performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain
output, requires a pull-up resistor (between 1 and 10 kΩ).
Sleep mode key scan example
Example: KC0 = 1, KC1 = 0, KC2 = 1, (sleep with only KS6 high)
[L] KS1
[L] KS2
[L] KS3
[L] KS4
[L] KS5
[H] KS6
*4
When any one of these keys is pressed, either the
OSC pin oscillator starts (if the IC is in RC
oscillator mode) or the IC starts accepting the
external clock signal (if the IC is in external clock
mode) and a key scan operation is performed.
KI1
KI2
KI3
KI4
KI5
Note: *4. These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above
example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5
lines are pressed at the same time.
Key input
(KS6 line)
Key scan
615T[s]
615T[s]
CE
DI
Serial data transfer
(KSC = 0)
Serial data transfer
Serial data transfer
(KSC = 0)
1
fosc
1
fCK
Key address (43H)
Key address
(KSC = 0)
=
T=
DO
Key data read
Key data read
Key data read request
Key data read request
Page 19
LC75857E, LC75857W
4. Normal/sleep mode, when key scan operations are disabled
•
•
•
•
The KS1 to KS6 pins are set to the high or low level by the KC0 to KC2 bits in the control data.
No key scan operation is performed, whichever key is pressed.
If the key scan disabled state (KSC = 1 in the control data) is set during a key scan, the key scan is stopped.
If the key scan disabled state (KSC = 1 in the control data) is set when a key data read request (a low level on DO)
is output to the controller, all the key data is set to 0 and the key data read request is cleared (DO is set high).
Note that DO, being an open-drain output, requires a pull-up resister (between 1 to 10 kΩ).
The key scan disabled state is cleared by setting KSC in the control data to 0.
•
Key input 1
Key input 2
Key scan
615T[s]
615T[s]
CE
DI
Serial data transfer Serial data transfer Serial data transfer
(KSC = 0) (KSC = 1) (KSC = 0)
Serial data transfer Serial data transfer
(KSC = 1) (KSC = 0)
Key address
(43H)
DO
Key data
read
Key data read request
Key data read request
1
T=
1
=
fosc
fCK
Multiple Key Presses
Although the LC75857E/W is capable of key scanning without inserting diodes for dual key presses, triple key presses on
the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than
these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be
inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should
check the key data for three or more 1 bits and ignore such data.
Page 20
LC75857E, LC75857W
1/3 Duty, 1/2 Bias Drive Technique
fo[Hz]
VLCD
VLCD1,VLCD2
0V
COM1
COM2
COM3
VLCD
VLCD1,VLCD2
0V
VLCD
VLCD1,VLCD2
0V
VLCD
VLCD1,VLCD2
0V
LCD driver output when all LCD segments corresponding to
COM1, COM2 and COM3 are turned off.
VLCD
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM1 are on
VLCD
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM2 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1 and COM2 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1 and COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments corresponding
to COM2 and COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when all LCD segments corresponding to
COM1, COM2 and COM3 are on.
1/3 Duty, 1/2 Bias Waveforms
fosc
768
fosc
576
fosc
384
fosc
288
fosc
192
fCK
768
fCK
576
fCK
384
fCK
288
fCK
192
Note: When FC0 = 0, FC1 = 0, and FC2 = 0 in the control data
When FC0 = 0, FC1 = 0, and FC2 = 1 in the control data
When FC0 = 0, FC1 = 1, and FC2 = 0 in the control data
When FC0 = 0, FC1 = 1, and FC2 = 1 in the control data
When FC0 = 1, FC1 = 0, and FC2 = 0 in the control data
f0 =
f0 =
f0 =
f0 =
f0 =
=
=
=
=
=
Page 21
LC75857E, LC75857W
1/3 Duty, 1/3 Bias Drive Technique
fo[Hz]
VLCD
VLCD1
VLCD2
0V
COM1
COM2
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
COM3
VLCD
VLCD1
VLCD2
0V
LCD driver output when all LCD segments corresponding to
COM1, COM2 and COM3 are turned off.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM1 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM2 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1 and COM2 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1 and COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments corresponding
to COM2 and COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2 and COM3 are on.
1/3 Duty, 1/3 Bias Waveforms
fosc
768
fosc
576
fosc
384
fosc
288
fosc
192
fCK
768
fCK
576
fCK
384
fCK
288
fCK
192
Note: When FC0 = 0, FC1 = 0, and FC2 = 0 in the control data
When FC0 = 0, FC1 = 0, and FC2 = 1 in the control data
When FC0 = 0, FC1 = 1, and FC2 = 0 in the control data
When FC0 = 0, FC1 = 1, and FC2 = 1 in the control data
When FC0 = 1, FC1 = 0, and FC2 = 0 in the control data
f0 =
f0 =
f0 =
f0 =
f0 =
=
=
=
=
=
Page 22
LC75857E, LC75857W
1/4 Duty, 1/2 Bias Drive Technique
fo[Hz]
VLCD
VLCD1, VLCD2
0V
COM1
VLCD
VLCD1, VLCD2
0V
COM2
COM3
VLCD
VLCD1, VLCD2
0V
VLCD
VLCD1, VLCD2
0V
COM4
VLCD
VLCD1, VLCD2
0V
LCD driver output when all LCD segments corresponding to
COM1, COM2, COM3 and COM4 are turned off.
VLCD
VLCD1, VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM1 are on.
VLCD
VLCD1, VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM2 are on.
VLCD
VLCD1, VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1 and COM2 are on.
VLCD
VLCD1, VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM3 are on.
VLCD
VLCD1, VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1 and COM3 are on.
VLCD
VLCD1, VLCD2
0V
LCD driver output when LCD segments corresponding
to COM2 and COM3 are on.
VLCD
VLCD1, VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1, COM2 and COM3 are on.
VLCD
VLCD1, VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM4 are on.
VLCD
VLCD1, VLCD2
0V
LCD driver output when LCD segments corresponding
to COM2 and COM4 are on.
VLCD
VLCD1, VLCD2
0V
LCD driver output when all LCD segments corresponding to
COM1, COM2, COM3 and COM4 are on.
1/4 Duty, 1/2 Bias Waveforms
fosc
768
fosc
576
fosc
384
fosc
288
fosc
192
fCK
768
fCK
576
fCK
384
fCK
288
fCK
192
Note: When FC0 = 0, FC1 = 0, and FC2 = 0 in the control data
When FC0 = 0, FC1 = 0, and FC2 = 1 in the control data
When FC0 = 0, FC1 = 1, and FC2 = 0 in the control data
When FC0 = 0, FC1 = 1, and FC2 = 1 in the control data
When FC0 = 1, FC1 = 0, and FC2 = 0 in the control data
f0 =
f0 =
f0 =
f0 =
f0 =
=
=
=
=
=
Page 23
LC75857E, LC75857W
1/4 Duty, 1/3 Bias Drive Technique
fo[Hz]
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
COM1
COM2
COM3
COM4
VLCD
VLCD1
VLCD2
0V
LCD driver output when all LCD segments corresponding to
COM1, COM2, COM3 and COM4 are turned off.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM1 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM2 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1 and COM2 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1 and COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments corresponding
to COM2 and COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1, COM2 and COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM4 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments corresponding
to COM2 and COM4 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when all LCD segments corresponding to
COM1, COM2, COM3 and COM4 are on.
1/4 Duty, 1/3 Bias Waveforms
fosc
768
fosc
576
fosc
384
fosc
288
fosc
192
fCK
768
fCK
576
fCK
384
fCK
288
fCK
192
Note: When FC0 = 0, FC1 = 0, and FC2 = 0 in the control data
When FC0 = 0, FC1 = 0, and FC2 = 1 in the control data
When FC0 = 0, FC1 = 1, and FC2 = 0 in the control data
When FC0 = 0, FC1 = 1, and FC2 = 1 in the control data
When FC0 = 1, FC1 = 0, and FC2 = 0 in the control data
f0 =
f0 =
f0 =
f0 =
f0 =
=
=
=
=
=
Page 24
LC75857E, LC75857W
Voltage Detection Type Reset Circuit (VDET)
This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage
drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET,
which is 2.2V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power
supply line so that the logic block power supply voltage V rise time when the logic block power is first applied and the
DD
logic block power supply voltage V fall time when the voltage drops are both at least 1 ms. (See Figure 5 and Figure 6.)
DD
Power Supply Sequence
The following sequences must be observed when power is turned on and off. (See Figure 5 and Figure 6.)
• Power on :Logic block power supply(V ) on → LCD driver block power supply(V
) on
LCD
DD
• Power off:LCD driver block power supply(V ) off → Logic block power supply(V ) off
LCD DD
However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off
at the same time.
System Reset
The LC75857E/W supports the reset methods described below. When a system reset is applied, display is turned off, key
scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning
become possible.
1. Reset methods
If at least 1 ms is assured as the logic block supply voltage V rise time when logic block power is applied, a system
DD
reset will be applied by the VDET output signal when the logic block supply voltage is brought up. If at least 1 ms is
assured as the logic block supply voltage V fall time when logic block power drops, a system reset will be applied
DD
in the same manner by the VDET output signal when the supply voltage is lowered. Note that the reset is cleared at
the point when all the serial data (1/3 duty: the display data D1 to D126 and the control data, 1/4 duty: the display
data D1 to D164 and the control data) has been transferred, i.e., on the fall of the CE signal on the transfer of the last
direction data, after all the direction data has been transferred. (See Figure 5 and Figure 6.)
Page 25
LC75857E, LC75857W
• 1/3 duty
t1 t2
t3 t4
VDD
VLCD
CE
VDET
VDET
VIL1
D1 to D42, SP,
Display and control data transfer
KC0 to KC2, KSC, K0,
K1,P0 to P2, SC, DR,
DT, FC0 to FC2, OC
Undefined
Undefined
Undefined
Undefined
Defined
Defined
Defined
Internal data
Undefined
Internal data (D43 to D84)
Internal data (D85 to D126)
Undefined
System reset period
Note: t1 ≥ 1 [ms] (Logic block power supply voltage VDD rise time)
t2 ≥ 0
t3 ≥ 0
t4 ≥ 1 [ms] (Logic block power supply voltage VDD fall time)
Figure 5
• 1/4 duty
t1 t2
t3 t4
VDD
VLCD
CE
VDET
VDET
VIL1
D1 to D44, SP,
KC0 to KC2, KSC, K0,
K1, P0 to P2, SC, DR,
DT,FC0 to FC2, OC
Display and control data transfer
Internal data
Undefined
Undefined
Undefined
Undefined
Defined
Defined
Defined
Defined
Undefined
Internal data (D45 to D84)
Undefined
Undefined
Internal data (D85 to D124)
Internal data (D125 to D164)
Undefined
System reset period
Note: t1 ≥ 1 [ms] (Logic block power supply voltage VDD rise time)
t2 ≥ 0
t3 ≥ 0
t4 ≥ 1 [ms] (Logic block power supply voltage VDD fall time)
Figure 6
Page 26
LC75857E, LC75857W
2. LC75857E/W internal block states during the reset period
• CLOCK GENERATOR
A reset is applied and either the OSC pin oscillator is stopped or external clock input is stopped.
• COMMON DRIVER, SEGMENT DRIVER & LATCH
Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
• KEY SCAN
Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.
• KEY BUFFER
Reset is applied and all the key data is set to low.
• CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER
Since serial data transfer is possible, these circuits are not reset.
VLCD
SEGMENT DRIVER & LATCH
VLCD1
COMMON
DRIVER
VLCD2
VSS
TEST
OSC
CLOCK
GENERATOR
CONTROL
REGISTER
DO
SHIFT REGISTER
KEY BUFFER
CCB
INTERFACE
DI
CL
CE
VDD
KEY SCAN
VDET
Blocks that are reset
Page 27
LC75857E, LC75857W
3. Pin states during the reset period
pin
S1/P1 to S4/P4
S5 to S38
State during reset
L *5
L
COM1 to COM3
COM4/S39
KS1/S40 to KS3/S42
KS4 to KS6
OSC
L
L *6
L *5
L *7
Z *8
H *9
DO
Notes:*5. These output pins are forcibly set to the segment output function and held low.
*6. When power is first applied, this output pin is forcibly set to the common output function and held low. However, when the DT control data bit is
transferred, either the common output or the segment output function is selected.
*7. This output pin is forcibly held fixed at the low level.
*8. This I/O pin is forcibly set to the high-impedance state.
*9. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin remains high during the reset period
even if a key data read operation is performed.
Notes on the OSC Pin Peripheral Circuit
1. RC oscillator mode (control data bit OC = 0)
When RC oscillator mode is selected, the external resistor Rosc and the external capacitor Cosc must be connected
between the OSC pin and ground.
OSC
Rosc Cosc
2. External clock mode (control data bit OC = 1)
When external clock mode is selected, the current protection resistor Rg (4.7 to 47 kΩ) must be connected between
the OSC pin and the external clock output pin (external oscillator). The value of this resistor is determined by the
allowable current for the external clock output pin. Verify that the external clock waveform is not deformed
significantly.
External clock
OSC
output pin
Rg
External oscillator
Note: The external clock output pin allowable current must be greater than VDD/Rg.
Page 28
LC75857E, LC75857W
Sample Application Circuit 1
1/3 duty, 1/2 bias (for use with normal panels)
(general-purpose output ports)
(P1)
(P2)
(P3)
(P4)
Used with the backlight
controller or other circuit.
OSC
*11
+3V
VDD
COM1
*10
COM2
COM3
P1/S1
P2/S2
P3/S3
P4/S4
S5
VSS
TEST
+5V
VLCD
VLCD1
VLCD2
S38
COM4/S39
C
C ≥ 0.047 µF
S S S
4 4 4
2 1 0
/ / /
CE
CL
DI
(S40)
(S41)
(S42)
From the controller
K K K K K K K K K K K
I I I I I
5 4 3 2 1
S S S S S S
6 5 4 3 2 1
DO
To the controller
To the controller
power supply
*12
Key matrix
(up to 30 keys)
Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic
block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET.
*11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and
ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 kΩ) must be connected between the OSC pin and
the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.)
*12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
Page 29
LC75857E, LC75857W
Sample Application Circuit 2
1/3 duty, 1/2 bias (for use with large panels)
(general-purpose output ports)
(P1)
(P2)
(P3)
(P4)
Used with the backlight
controller or other circuit.
OSC
*11
+3V
VDD
COM1
*10
COM2
COM3
P1/S1
P2/S2
P3/S3
P4/S4
S5
VSS
TEST
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
+5V
VLCD
R
R
VLCD1
VLCD2
C
S38
COM4/S39
S S S
4 4 4
2 1 0
/ / /
CE
CL
DI
(S40)
(S41)
(S42)
From the controller
K K K K K K K K K K K
I I I I I
5 4 3 2 1
S S S S S S
6 5 4 3 2 1
To the controller
DO
To the controller
power supply
*12
Key matrix
(up to 30 keys)
Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic
block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET.
*11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and
ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 kΩ) must be connected between the OSC pin and
the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.)
*12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
Page 30
LC75857E, LC75857W
Sample Application Circuit 3
1/3 duty, 1/3 bias (for use with normal panels)
(general-purpose output ports)
(P1)
(P2)
(P3)
(P4)
Used with the backlight
controller or other circuit.
OSC
*11
+3V
VDD
COM1
*10
COM2
COM3
P1/S1
P2/S2
P3/S3
P4/S4
S5
VSS
TEST
+5V
VLCD
VLCD1
VLCD2
C ≥ 0.047 µF
S38
COM4/S39
C
C
S S S
4 4 4
2 1 0
/ / /
CE
CL
DI
(S40)
(S41)
(S42)
From the controller
K K K K K K K K K K K
I I I I I
5 4 3 2 1
S S S S S S
6 5 4 3 2 1
To the controller
DO
To the controller
power supply
*12
Key matrix
(up to 30 keys)
Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic
block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET.
*11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and
ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 kΩ) must be connected between the OSC pin and
the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.)
*12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
Page 31
LC75857E, LC75857W
Sample Application Circuit 4
1/3 duty, 1/3 bias (for use with large panels)
(general-purpose output ports)
(P1)
(P2)
(P3)
(P4)
Used with the backlight
controller or other circuit.
OSC
*11
+3V
VDD
COM1
*10
COM2
COM3
P1/S1
P2/S2
P3/S3
P4/S4
S5
VSS
TEST
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
VLCD
+5V
R
R
R
VLCD1
VLCD2
C
C
S38
COM4/S39
S S S
4 4 4
2 1 0
/ / /
CE
CL
DI
(S40)
(S41)
(S42)
From the controller
K K K K K K K K K K K
I I I I I
5 4 3 2 1
S S S S S S
6 5 4 3 2 1
To the controller
DO
To the controller
power supply
*12
Key matrix
(up to 30 keys)
Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic
block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET.
*11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and
ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 kΩ) must be connected between the OSC pin and
the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.)
*12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
Page 32
LC75857E, LC75857W
Sample Application Circuit 5
1/4 duty, 1/2 bias (for use with normal panels)
(general-purpose output ports)
(P1)
(P2)
(P3)
(P4)
Used with the backlight
controller or other circuit.
OSC
*11
+3V
VDD
COM1
*10
COM2
COM3
S39/COM4
P1/S1
VSS
TEST
+5V
VLCD
P2/S2
P3/S3
VLCD1
VLCD2
P4/S4
S5
C
C ≥ 0.047 µF
S38
S S S
4 4 4
2 1 0
/ / /
CE
CL
DI
(S40)
(S41)
(S42)
From the controller
K K K K K K K K K K K
I I I I I
5 4 3 2 1
S S S S S S
6 5 4 3 2 1
To the controller
DO
To the controller
power supply
*12
Key matrix
(up to 30 keys)
Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic
block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET.
*11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and
ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 kΩ) must be connected between the OSC pin and
the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.)
*12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
Page 33
LC75857E, LC75857W
Sample Application Circuit 6
1/4 duty, 1/2 bias (for use with large panels)
(general-purpose output ports)
(P1)
(P2)
(P3)
(P4)
Used with the backlight
controller or other circuit.
OSC
*11
+3V
VDD
COM1
*10
COM2
COM3
S39/COM4
P1/S1
VSS
TEST
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
VLCD
P2/S2
+5V
P3/S3
P4/S4
R
R
VLCD1
VLCD2
S5
C
S38
S S S
4 4 4
2 1 0
/ / /
CE
CL
DI
(S40)
(S41)
(S42)
From the controller
K K K K K K K K K K K
I I I I I
5 4 3 2 1
S S S S S S
6 5 4 3 2 1
To the controller
DO
To the controller
power supply
*12
Key matrix
(up to 30 keys)
Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic
block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET.
*11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and
ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 kΩ) must be connected between the OSC pin and
the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.)
*12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
Page 34
LC75857E, LC75857W
Sample Application Circuit 7
1/4 duty, 1/3 bias (for use with normal panels)
(general-purpose output ports)
(P1)
(P2)
(P3)
(P4)
Used with the backlight
controller or other circuit.
OSC
*11
+3V
VDD
COM1
*10
COM2
COM3
S39/COM4
P1/S1
VSS
TEST
+5V
VLCD
P2/S2
P3/S3
VLCD1
VLCD2
P4/S4
S5
C ≥ 0.047 µF
C
C
S38
S S S
4 4 4
2 1 0
/ / /
CE
CL
DI
(S40)
(S41)
(S42)
From the controller
K K K K K K K K K K K
I I I I I
5 4 3 2 1
S S S S S S
6 5 4 3 2 1
To the controller
DO
To the controller
power supply
*12
Key matrix
(up to 30 keys)
Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic
block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET.
*11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and
ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 kΩ) must be connected between the OSC pin and
the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.)
*12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
Page 35
LC75857E, LC75857W
Sample Application Circuit 8
1/4 duty, 1/3 bias (for use with large panels)
(general-purpose output ports)
(P1)
(P2)
(P3)
(P4)
Used with the backlight
controller or other circuit.
OSC
*11
+3V
VDD
COM1
*10
COM2
COM3
S39/COM4
P1/S1
VSS
TEST
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
+5V
VLCD
P2/S2
R
R
R
P3/S3
P4/S4
VLCD1
VLCD2
S5
C
C
S38
S S S
4 4 4
2 1 0
/ / /
CE
CL
DI
(S40)
(S41)
(S42)
From the controller
K K K K K K K K K K K
I I I I I
5 4 3 2 1
S S S S S S
6 5 4 3 2 1
To the controller
DO
To the controller
power supply
*12
Key matrix
(up to 30 keys)
Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic
block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET.
*11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and
ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 kΩ) must be connected between the OSC pin and
the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.)
*12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
Notes on transferring display data from the controller
When using the LC75857E/W in 1/3 duty, applications transfer the display data (D1 to D126) in three operations, and in
1/4 duty, they transfer the display data (D1 to D164) in four operations. In either case, applications should transfer all of
the display data within 30 ms to maintain the quality of the displayed image.
Page 36
LC75857E, LC75857W
Notes on the controller key data read techniques
1. Timer based key data acquisition
(1) Flowchart
CE = [L]
NO
DO = [L]
YES
Key data read
processing
(2) Timing chart
Key on
Key on
Key input
Key scan
t5
t6
t5
t5
CE
DI
t8
t8
t8
Key address
t7
t7
t7
Key data read
DO
Key data read request
t9
t9
t9
t9
Controller
determination
(Key on)
Controller
determination
(Key off)
Controller
determination
(Key on)
Controller
determination
(Key off)
Controller
determination
(Key on)
t5: Key scan execution time when the key data agreed for two key scans. (615T(s))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1230T(s))
t7: Key address (43H) transfer time
1
1
T =——— = ——
t8: Key data read time
fosc fCK
(3) Explanation
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must
check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a key has
been pressed and executes the key data read operation.
The period t9 in this technique must satisfy the following condition.
t9>t6+t7+t8
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
Page 37
LC75857E, LC75857W
2. Interrupt based key data acquisition
(1) Flowchart
CE = [L]
NO
DO = [L]
YES
Key data read
processing
Wait for at
least t10
CE = [L]
NO
DO = [H]
YES
Key OFF
(2) Timing chart
Key on
Key on
Key input
Key scan
t5
t5
t6
t5
CE
t8
t8
t8
t8
Key address
DI
t7
t7
t7
t7
Key data read
DO
Key data read request
t10
t10
t10
t10
Controller
determination
(Key on)
Controller
determination
(Key on)
Controller
determination
(Key off)
Controller
determination
(Key off)
Controller
determination
(Key on)
Controller
determination
(Key on)
t5: Key scan execution time when the key data agreed for two key scans. (615T(s))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1230T(s))
t7: Key address (43H) transfer time
1
1
T =——— = ——
t8: Key data read time
fosc fCK
Page 38
LC75857E, LC75857W
(3) Explanation
In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller
must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and
executes the key data read operation. After that the next key on/off determination is performed after the time t10
has elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique
must satisfy the following condition.
t10 > t6
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
www.onsemi.com
39
LC75857E, LC75857W
Package Dimensions
unit : mm
[LC75857E]
PQFP64 14x14 / QIP64E
CASE 122BP
ISSUE A
17.20.2
14.00.1
1
2
0.15
0.8
0.35
0.15
(1.0)
0 to 10
0.10
GENERIC
SOLDERING FOOTPRINT*
MARKING DIAGRAM*
16.30
XXXXXXXX
YMDDD
(Unit: mm)
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
0.80
0.50
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
40
LC75857E, LC75857W
Package Dimensions
unit : mm
[LC75857W]
SPQFP64 10x10 / SQFP64
CASE 131AK
ISSUE A
12.00.2
10.00.1
1 2
0.150.05
0.5
0.18
0.10
(1.25)
0 to 10
0.10
SOLDERING FOOTPRINT*
GENERIC MARKING DIAGRAM*
11.40
XXXXXXXX
YDD
XXXXXXXX
YMDDD
(Unit: mm)
XXXXX = Specific Device Code
Y = Year
XXXXX = Specific Device Code
Y = Year
DD = Additional Traceability Data
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
0.50
0.28
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
41
LC75857E, LC75857W
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
PQFP64 14x14 / QIP64E
(Pb-Free)
LC75857E-E
60 / Tray JEDEC
60 / Tray Foam
PQFP64 14x14 / QIP64E
(Pb-Free)
LC75857ES-E
LC75857W-E
LC75857WH-E
LC75857WS-E
SPQFP64 10x10 / SQFP64
(Pb-Free)
800 / Tray JEDEC
800 / Tray JEDEC
800 / Tray JEDEC
SPQFP64 10x10 / SQFP64
(Pb-Free)
SPQFP64 10x10 / SQFP64
(Pb-Free)
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries
in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other
intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON
Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or
use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is
responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or
standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its
patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support
systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall
indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an
Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
www.onsemi.com
42
相关型号：
©2020 ICPDF网 联系我们和版权申明