LC75863E [SANYO]
1/3 Duty LCD Display Drivers with Key Input Function; 用按键输入功能1/3占空比LCD显示驱动器
| 型号： | LC75863E |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 1/3 Duty LCD Display Drivers with Key Input Function |
| 文件： | 总24页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN7135
CMOS IC
LC75863E, 75863W
1/3 Duty LCD Display Drivers with Key Input Function
Overview
Package Dimensions
The LC75863E and LC75863W are 1/3 duty LCD display
drivers that can directly drive up to 75 segments and can
control up to four general-purpose output ports. These
products also incorporate a key scan circuit that accepts
input from up to 30 keys to reduce printed circuit board
wiring.
unit: mm
3156-QIP48E
[LC75863E]
17.2
14.0
0.35
1.6
1.5
36
1.0
1.5
25
0.15
37
24
Features
• Key input function for up to 30 keys (A key scan is
performed only when a key is pressed.)
• 1/3duty - 1/2bias and 1/3duty - 1/3bias drive schemes
can be controlled from serial data (up to 75 segments).
• Sleep mode and all segments off functions that are
controlled from serial data.
13
48
0.1
2.7
12
1
• Segment output port/general-purpose output port
function switching that is controlled from serial data.
• Serial data I/O supports CCB format communication
with the system controller.
• Direct display of display data without the use of a
decoder provides high generality.
0.8
15.6
SANYO: QIP48E
unit: mm
3163A-SQFP48
[LC75863W]
9.0
7.0
• Independent V
for the LCD driver block (V
can
LCD
LCD
0.75
0.5
0.18
0.75
0.15
be set to in the range V -0.5 to 6.0 volts.)
DD
25
36
• Provision of an on-chip voltage-detection type reset
circuit prevents incorrect displays.
37
24
• RC oscillator circuit.
13
48
1
12
•
•
CCB is a trademark of SANYO ELECTRIC CO., LTD.
CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
0.5
0.5
SANYO: SQFP48
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D2001TN (OT) No. 7135-1/24
LC75863E, 75863W
Pin Assignment
36
37
25
24
KI5
VDD
VLCD
VLCD1
VLCD2
VSS
TEST
OSC
DO
COM1
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
LC75863E
(QIP48E)
LC75863W
(SQFP48)
CE
CL
DI
48
1
13
12
Top view
Specifications
Absolute Maximum Ratings at Ta=25°C, V =0V
SS
Parameter
Maximum supply voltage
Symbol
DD max
LCD max VLCD
Conditions
Ratings
–0.3 to +7.0
–0.3 to +7.0
–0.3 to +7.0
–0.3 to VDD +0.3
–0.3 to VLCD +0.3
-0.3 to +7.0
–0.3 to VDD +0.3
–0.3 to VLCD +0.3
300
Unit
V
V
VDD
V
VIN1
VIN2
VIN3
CE, CL, DI
OSC,TEST
Input voltage
V
VLCD1, VLCD2, KI1 to KI5
V
V
V
OUT1
OUT2
OUT3
DO
Output voltage
OSC
V
S1 to S25, COM1 to COM3, KS1 to KS6, P1 to P4
IOUT1
IOUT2
IOUT3
IOUT4
S1 to S25
µA
mA
COM1 to COM3
KS1 to KS6
P1 to P4
3
Output current
1
5
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Ta = 85°C
150
mW
°C
–40 to +85
–55 to +125
Tstg
°C
Allowable Operating Ranges at Ta = –40 to +85°C, V =0V
SS
Ratings
Parameter
Symbol
Conditions
Unit
V
min
4.5
typ
max
6.0
VDD
VDD
Supply voltage
Input voltage
VLCD
VLCD
VLCD
VLCD
VDD – 0.5
6.0
VLCD
V
V
LCD1
LCD2
1
2
2/3 VLCD
1/3 VLCD
V
VLCD
VIH
1
CE, CL, DI
KI1 to KI5
0.8 VDD
0.6 VDD
0
6.0
Input high level voltage
Input low level voltage
V
V
V
IH2
VLCD
VIL
CE, CL, DI, KI1 to KI5
0.2 VDD
Continued on next page.
No. 7135-2/24
LC75863E, 75863W
Continued from preceding page.
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
Recommended external resistance
Recommended external capacitance
Guaranteed oscillator range
Data setup time
ROSC
COSC
fOSC
tds
OSC
39
kΩ
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
OSC
1000
38
OSC
19
76
CL, DI
:Figure 2
:Figure 2
:Figure 2
:Figure 2
:Figure 2
:Figure 2
:Figure 2
:Figure 2
:Figure 2
:Figure 2
:Figure 2
160
160
160
160
160
160
160
Data hold time
tdh
CL, DI
CE wait time
tcp
CE, CL
CE setup time
tcs
CE, CL
CE hold time
tch
CE, CL
High level clock pulse width
Low level clock pulse width
Rise time
tøH
tøL
tr
CL
CL
CE, CL, DI
160
160
Fall time
tf
CE, CL, DI
DO output delay time
DO rise time
tdc
DO RPU=4.7kΩ, CL=10pF *1
DO RPU=4.7kΩ, CL=10pF *1
1.5
1.5
tdr
Note: *1. Since DO is an open-drain output, these times depend on the values of the pull-up resistor RPU and the load capacitance CL.
Electrical Characteristics for the Allowable Operating Ranges
Ratings
Parameter
Symbol
Conditions
CE, CL, DI, KI1 to KI5
Unit
min
typ
0.1 VDD
3.0
max
Hysteresis
VH
VDET
IIH
V
V
Power-down detection voltage
Input high level current
Input low level current
Input floating voltage
2.5
3.5
5.0
CE, CL, DI: VI = 6.0V
µA
µA
V
IIL
CE, CL, DI: VI = 0V
–5.0
50
VIF
KI1 to KI5
0.05 VDD
250
Pull-down resistance
RPD
IOFFH
KI1 to KI5: VDD = 5.0V
100
kΩ
µA
Output off leakage current
DO: VO = 6.0V
6.0
V
V
V
OH1
OH2
OH3
KS1 to KS6: IO = –500µA
P1 to P4: IO = –1mA
VLCD – 1.0 VLCD – 0.5 VLCD – 0.2
VLCD – 1.0
Output high level voltage
Output low level voltage
V
S1 to S25: IO = –20µA
VLCD – 1.0
VOH
4
COM1 to COM3: IO = –100µA
KS1 to KS6: IO = 25µA
VLCD – 1.0
V
V
V
V
V
OL1
OL2
OL3
OL4
OL5
0.2
0.5
0.1
1.5
1.0
1.0
1.0
0.5
+ 1.0
+ 1.0
+ 1.0
+ 1.0
+ 1.0
P1 to P4: IO = 1mA
S1 to S25: IO = 20µA
V
COM1 to COM3: IO = 100µA
DO: IO = 1mA
V
MID1
COM1 to COM3: 1/2bias, IO = ±100µA
S1 to S25: 1/3bias,IO = ±20µA
S1 to S25: 1/3bias, IO = ±20µA
COM1 to COM3: 1/3bias,IO = ±100µA
COM1 to COM3: 1/3bias,IO = ±100µA
OSC: ROSC = 39kΩ, COSC = 1000pF
VDD :Sleep mode
1/2V
2/3V
1/3V
2/3V
1/3V
– 1.0
– 1.0
– 1.0
– 1.0
– 1.0
1/2V
2/3V
1/3V
2/3V
1/3V
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
VMID
2
3
Output middle level voltage *2
VMID
V
V
MID4
VMID
fosc
5
Oscillator frequency
30.4
38
45.6
100
540
5
kHz
I
DD1
DD2
I
VDD: VDD = 6.0V, output open,fosc = 38kHz
VLCD : Sleep mode
270
I
LCD1
ILCD
LCD3
Current drain
µA
VLCD: VLCD = 6.0V, output open, 1/2bias,
fosc = 38kHz
2
100
60
200
120
VLCD: VLCD = 6.0V, output open, 1/3bias,
fosc = 38kHz
I
Note: *2. Excluding the bias voltage generation divider resistor built into VLCD1 and VLCD2. (See Figure 1.)
No. 7135-3/24
LC75863E, 75863W
VLCD
VLCD1
VLCD2
To the common segment driver
Excluding these resistors.
Figure 1
1. When CL is stopped at the low level
VIH1
CE
VIL
tøH
tøL
VIH1
50%
CL
VIL
tr
tf
tcp
tcs
tch
VIH1
DI
VIL
tds
tdh
tdc
tdr
DO
D0
D1
2. When CL is stopped at the high level
VIH1
CE
VIL
tøL
tøH
VIH1
50%
VIL
CL
DI
tf
tr
tcp
tcs
tch
tdr
VIH1
VIL
tds
tdh
DO
D0
D1
tdc
Figure 2
No. 7135-4/24
LC75863E, 75863W
Block Diagram
VLCD
VLCD1
VLCD2
VSS
SEGMENT DRIVER & LATCH
SHIFT REGISTER
COMMON
DRIVER
TEST
OSC
CLOCK
GENERATOR
CONTROL
REGISTER
DO
CCB
INTERFACE
DI
CL
CE
KEY BUFFER
VDD
VDET
KEY SCAN
No. 7135-5/24
LC75863E, 75863W
Pin Functions
Handling
when unused
Pin
Pin No.
Function
Active
—
I/O
S1/P1
S2/P2
S3/P3
S4/P4
S5 to S23
1
2
3
4
Segment outputs for displaying the display data transferred by serial data input.
The S1/P1 to S4/P4 pins can be used as general-purpose output ports under serial
data control.
●
OPEN
OPEN
5 to 23
COM1
COM2
COM3
24
25
26
Common driver outputs
—
—
●
The frame frequency fo is given by : fo = (fOSC/384)Hz.
Key scan outputs
Although normal key scan timing lines require diodes to be inserted in the timing lines
to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these
outputs will not be damaged by shorting when these outputs are used to form a key
matrix. The KS1/S24 and KS2/S25 pins can be used as segment outputs when so
specified by the control data.
KS1/S24
KS2/S25
KS3 to KS6
27
28
29 to 32
O
OPEN
Key scan inputs
These pins have built-in pull-down resistors.
KI1 to KI5
OSC
33 to 37
44
H
I
GND
VDD
Oscillator connection
An oscillator circuit is formed by connecting an external resistor and capacitor at this
pin.
—
I/O
Serial data interface connections to the controller. Note that DO, being an open-drain
output, requires a pull-up resistor.
CE :Chip enable
CL :Synchronization clock
DI :Transfer data
CE
CL
DI
46
47
48
H
I
I
I
▲
GND
—
DO :Output data
DO
45
43
—
—
O
I
OPEN
—
TEST
This pin must be connected to ground.
Used for applying the LCD drive 2/3 bias voltage externally. Must be connected to
VLCD2 when a 1/2 bias drive scheme is used.
VLCD
1
40
41
38
—
—
—
I
I
OPEN
OPEN
—
Used for applying the LCD drive 1/3 bias voltage externally. Must be connected to
VLCD1 when a 1/2 bias drive scheme is used.
VLCD
2
Logic block power supply connection. Provide a voltage of between 4.5 and 6.0V.
VDD
—
LCD driver block power supply connection. Provide a voltage of between VDD–0.5 and
6.0V.
VLCD
VSS
39
42
—
—
—
—
—
—
Power supply connection. Connect to ground.
No. 7135-6/24
LC75863E, 75863W
Serial Data Input
1. When CL is stopped at the low level
CE
CL
0
1
0
0
0
0
1
0
D1 D2
D34 D35 D36 D37 D38 D39
0
0
0
0
0
0
0 S0 S1 K0 K1 P0 P1 P2 SCDR
Control Data
0
DI
Display Data
B0 B1 B2 B3 A0 A1 A2 A3
DD
DO
0
1
0
0
0
0
1
0
D40 D41
D73 D74 D75
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Display Data
Fixed Data
B0 B1 B2 B3 A0 A1 A2 A3
DD
......
Note: B0 to B3, A0 to A3
CCB address
Direction data
................................
DD
2. When CL is stopped at the high level
CE
CL
0
1
0
0
0
0
1
0
D1 D2
D34 D35 D36 D37 D38 D39
0
0
0
0
0
0
0 S0 S1 K0 K1 P0 P1 P2 SC DR 0
DI
Display Data
B0 B1 B2 B3 A0 A1 A2 A3
Control Data
DD
DO
0
1
0
0
0
0
1
0
D40 D41
D73 D74 D75
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display Data
Fixed Data
DD
......
Note: B0 to B3, A0 to A3
CCB address
Direction data
................................
DD
........
..............
....................
....................
................
CCB address
D1 to D75
S0,S1
K0,K1
P0 to P2
42H
Display data
Sleep control data
Key scan output/segment output selection data
Segment output port/general-purpose output port selection data
Segment on/off control data
1/2 bias or 1/3 bias drive selection data
........................
........................
SC
DR
No. 7135-7/24
LC75863E, 75863W
Control Data Functions
1. S0, S1 : Sleep control data
These control data bits switch between normal mode and sleep mode and set the states of the KS1 to KS6 key scan
outputs during key scan standby.
Control data
S0 S1
Output pin states during key scan standby
Segment outputs
Common outputs
Mode
OSC oscillator
KS1
H
KS2
H
KS3
H
KS4
H
KS5
H
KS6
H
0
0
Normal
Sleep
Sleep
Sleep
Operating
Stopped
Stopped
Stopped
Operating
0
1
1
1
0
1
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
H
H
H
H
H
Note: This assumes that the KS1/S24 and KS2/S25 output pins are selected for key scan output.
2. K0, K1 : Key scan output /segment output selection data
These control data bits switch the functions of the KS1/S24 and KS2/S25 output pins between key scan output and
segment output.
Control data
K0 K1
Output pin state
Maximum number of
input keys
KS1/S24
KS2/S25
KS2
0
0
KS1
S24
S24
30
25
20
0
1
1
KS2
X
S25
X: don’t care
Note: KSn(n=1 or 2) : Key scan output
Sn (n=24 or 25): Segment output
3. P0 to P2 : Segment output port/general-purpose output port selection data
These control data bits switch the functions of the S1/P1 to S4/P4 output pins between the segment output port and
the general-purpose output port.
Control data
Output pin state
P0
0
P1
0
P2
0
S1/P1
S1
S2/P2
S2
S3/P3
S3
S4/P4
S4
0
0
1
P1
S2
S3
S4
0
1
0
P1
P2
S3
S4
0
1
1
P1
P2
P3
S4
1
0
0
P1
P2
P3
P4
Note: Sn(n=1 to 4): Segment output port
Pn(n=1 to 4): General-purpose output port
The table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports.
Output pin
S1/P1
Corresponding display data
D1
D4
S2/P2
S3/P3
D7
S4/P4
D10
For example, if the S4/P4 output pin is selected to be a general-purpose output port, the S4/P4 output pin will output a high level (VLCD) when the display data
D10 is 1, and will output a low level (Vss) when D10 is 0.
No. 7135-8/24
LC75863E, 75863W
4. SC : Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
0
Display state
on
off
1
However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment
output pins.
5. DR : 1/2 bias or 1/3 bias drive selection data
This control data bit switches between LCD 1/2 bias or 1/3 bias drive.
DR
0
Drive scheme
1/3 bias drive
1/2 bias drive
1
Display Data and Output Pin Correspondence
Output pin
S1/P1
S2/P2
S3/P3
S4/P4
S5
COM1
D1
COM2
D2
COM3
D3
Output pin
S14
COM1
D40
D43
D46
D49
D52
D55
D58
D61
D64
D67
D70
D73
COM2
D41
D44
D47
D50
D53
D56
D59
D62
D65
D68
D71
D74
COM3
D42
D45
D48
D51
D54
D57
D60
D63
D66
D69
D72
D75
D4
D5
D6
S15
D7
D8
D9
S16
D10
D13
D16
D19
D22
D25
D28
D31
D34
D37
D11
D14
D17
D20
D23
D26
D29
D32
D35
D38
D12
D15
D18
D21
D24
D27
D30
D33
D36
D39
S17
S18
S6
S19
S7
S20
S8
S21
S9
S22
S10
S23
S11
KS1/S24
KS2/S25
S12
S13
Note: This is for the case where the output pins S1/P1 to S4/P4, KS1/S24 and KS2/S25 are selected for use as segment outputs.
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D31
0
D32
0
D33
0
The LCD segments for COM1, COM2 and COM3 are off.
The LCD segment for COM3 is on.
0
0
1
0
1
0
The LCD segment for COM2 is on.
0
1
1
The LCD segments for COM2 and COM3 are on.
The LCD segment for COM1 is on.
1
0
0
1
0
1
The LCD segments for COM1 and COM3 are on.
The LCD segments for COM1 and COM2 are on.
The LCD segments for COM1, COM2 and COM3 are on.
1
1
0
1
1
1
No. 7135-9/24
LC75863E, 75863W
Serial Data Output
1. When CL is stopped at the low level
CE
CL
DI
1
1
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
DO
X
KD1 KD2
KD27 KD28 KD29 KD30 SA
Output data
X: don’t care
Note: B0 to B3, A0 to A3······CCB address
2. When CL is stopped at the high level
CE
CL
DI
1
1
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2
A3
DO
X
KD1 KD2 KD3
KD28 KD29 KD30 SA
X
Output data
X: don’t care
Note: B0 to B3, A0 to A3······CCB address
......
CCB address
KD1 to KD30
SA
43H
Key data
Sleep acknowledge data
........
........................
Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data(SA) will be invalid.
No. 7135-10/24
LC75863E, 75863W
Output Data
1. KD1 to KD30 : Key data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and
one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the
relationship between those pins and the key data bits.
KI1
KI2
KI3
KI4
KI5
KS1/S24
KS2/S25
KS3
KD1
KD2
KD3
KD4
KD5
KD6
KD7
KD8
KD9
KD10
KD15
KD20
KD25
KD30
KD11
KD16
KD21
KD26
KD12
KD17
KD22
KD27
KD13
KD18
KD23
KD28
KD14
KD19
KD24
KD29
KS4
KS5
KS6
When the KS1/S24 and KS2/S25 output pins are selected to be segment outputs by control data bits K0 and K1 and a
key matrix of up to 20 keys is formed using the KS3 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to
KD10 key data bits will be set to 0.
2. SA : Sleep acknowledge data
This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data
is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep
mode and 0 in normal mode.
Sleep Mode Functions
Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common
outputs will also go low, and the oscillator on the OSC pin will stop (it will be started by a key press). This reduces
power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. However, note that the
S1/P1 to S4/P4 outputs can be used as general-purpose output ports according to the state of the P0 to P2 control data
bits, even in sleep mode. (See the control data description for details.)
No. 7135-11/24
LC75863E, 75863W
Key Scan Operation Functions
1. Key scan timing
The key scan period is 288T(s). To reliably determine the on/off state of the keys, the LC75863E/W scans the keys
twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low
level on DO) 615T(s) after starting a key scan. If the key data dose not agree and a key was pressed at that point, it
scans the keys again. Thus the LC75863E/W cannot detect a key press shorter than 615T(s).
KS1
KS2
KS3
KS4
KS5
KS6
*3
*3
*3
*3
*3
1
1
*3
*3
*3
*3
*3
2
2
3
3
1
T=
fosc
4
4
5
5
6
6
Key on
576T[s]
Note: *3.In sleep mode the high/low state of these pins is determined by the S0 and S1 bits in the control data. Key scan output signals are not output from
pins that are set low.
2. In normal mode
•
•
The pins KS1 to KS6 are set high.
When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key
presses are recognized by determining whether multiple key data bits are set.
1
——
) the LC75863E/W outputs a key data read request (a
•
•
If a key is pressed for longer than 615T(s) (Where T=
fosc
low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, DO will be set high.
After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75863E/W
performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1
and 10 kΩ).
Key input 1
Key input 2
Key scan
615T[s]
615T[s]
615T[s]
CE
Serial data
transfer
Serial data
transfer
Serial data
transfer
Key address
(43H)
Key address
Key address
DI
DO
Key data read
Key data read
Key data read
Key data read request
Key data read request
Key data read request
T=
1
fosc
No. 7135-12/24
LC75863E, 75863W
3. In sleep mode
•
The pins KS1 to KS6 are set to high or low by the S0 and S1 bits in the control data. (See the control data
description for details.)
•
If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the
OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses
are recognized by determining whether multiple key data bits are set.
1
——
) the LC75863E/W outputs a key data read request (a
•
•
•
If a key is pressed for longer than 615T(s)(Where T=
fosc
low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, DO will be set high.
After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75863E/W
performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain
output, requires a pull-up resistor (between 1 and 10 kΩ).
Sleep mode key scan example
Example: S0=0, S1=1 (sleep with only KS6 high)
When any one of these keys is pressed,
the oscillatior on the OSC pin is started
and the keys are scanned.
*4
KI1
KI2
KI3
KI4
KI5
Note: *4.These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above
example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5
lines are pressed at the same time.
Key input
(KS6 line)
Key scan
615T[s]
615T[s]
CE
DI
Serial data
transfer
Serial data
transfer
Serial data
transfer
Key address
(43H)
1
fosc
Key address
T=
DO
Key data read
Key data read
Key data read request
Key data read request
Multiple Key Presses
Although the LC75863E/W is capable of key scanning without inserting diodes for dual key presses, triple key presses on
the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than
these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be
inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should
check the key data for three or more 1 bits and ignore such data.
No. 7135-13/24
LC75863E, 75863W
1/3 Duty, 1/2 Bias Drive Technique
fosc
384
[Hz ]
VLCD
VLCD1, VLCD2
0V
COM1
COM2
COM3
VLCD
VLCD1, VLCD2
0V
VLCD
VLCD1, VLCD2
0V
VLCD
LCD driver output when all LCD
segments corresponding to COM1,
COM2 and COM3 are turned off.
VLCD1, VLCD2
0V
VLCD
LCD driver output when only LCD
segments corresponding to COM1
are on
VLCD1, VLCD2
0V
VLCD
LCD driver output when only LCD
segments corresponding to COM2
are on.
VLCD1, VLCD2
0V
VLCD
LCD driver output when LCD
segments corresponding to COM1
and COM2 are on.
VLCD1, VLCD2
0V
VLCD
LCD driver output when only LCD
segments corresponding to COM3
are on.
VLCD1, VLCD2
0V
VLCD
LCD driver output when LCD
segments corresponding to COM1
and COM3 are on.
VLCD1, VLCD2
0V
VLCD
LCD driver output when LCD
segments corresponding to COM2
and COM3 are on.
VLCD1, VLCD2
0V
VLCD
LCD driver output when all LCD
segments corresponding to COM1,
COM2 and COM3 are on.
VLCD1, VLCD2
0V
1/3 Duty, 1/2 Bias Waveforms
No. 7135-14/24
LC75863E, 75863W
1/3 Duty, 1/3 Bias Drive Technique
fosc
[Hz ]
384
VLCD
VLCD1
VLCD2
0V
COM1
COM2
COM3
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
LCD driver output when all LCD
segments corresponding to COM1,
COM2 and COM3 are turned off.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD
segments corresponding to COM1
are on
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD
segments corresponding to COM2
are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD
segments corresponding to COM1
and COM2 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD
segments corresponding to COM3
are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD
segments corresponding to COM1
and COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD
segments corresponding to COM2
and COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when all LCD
segments corresponding to COM1,
COM2 and COM3 are on.
1/3 Duty, 1/3 Bias Waveforms
No. 7135-15/24
LC75863E, 75863W
Voltage Detection Type Reset Circuit (VDET)
This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage
drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET,
which is 3.0V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power
supply line so that the logic block power supply voltage V rise time when the logic block power is first applied and the
DD
logic block power supply voltage V fall time when the voltage drops are both at least 1 ms. (See Figure 3.)
DD
Power Supply Sequence
The following sequences must be observed when power is turned on and off. (See Figure 3.)
• Power on :Logic block power supply(V ) on → LCD driver block power supply(V
) on
LCD
DD
• Power off:LCD driver block power supply(V ) off → Logic block power supply(V ) off
LCD DD
However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off
at the same time.
System Reset
The LC75863E/W supports the reset methods described below. When a system reset is applied, display is turned off, key
scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning
become possible.
1. Reset methods
• Reset at power-on and power-down
If at least 1 ms is assured as the logic block supply voltage V rise time when logic block power is applied, a system
DD
reset will be applied by the VDET output signal when the logic block supply voltage is brought up. If at least 1 ms is
assured as the logic block supply voltage V fall time when logic block power drops, a system reset will be applied in
DD
the same manner by the VDET output signal when the supply voltage is lowered. Note that the reset is cleared at the
point when all the serial data (the display data D1 to D75 and the control data) has been transferred, i.e., on the fall of the
CE signal on the transfer of the last direction data, after all the direction data has been transferred (see Figure 3).
t1 t2
t3 t4
VDD
VDET
VDET
VLCD
CE
VIL
Display and control data transfer
Undefined
D1 to D39
Defined
Defined
Undefined
Undefined
Internal data
Internal data
S0, S1, K0, K1
P0 to P2, SC, DR
Undefined
System reset period
(D40 to D75)
Note: t1 ≥ 1 [ms] (Logic block power supply voltage VDD rise time)
t2 ≥ 0
t3 ≥ 0
t4 ≥ 1 [ms] (Logic block power supply voltage VDD fall time)
Figure 3
No. 7135-16/24
LC75863E, 75863W
2. LC75863E/W internal block states during the reset period
• CLOCK GENERATOR
Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined
after the S0 and S1 control data bits are transferred.
• COMMON DRIVER, SEGMENT DRIVER & LATCH
Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
• KEY SCAN
Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.
• KEY BUFFER
Reset is applied and all the key data is set to low.
• CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER
Since serial data transfer is possible, these circuits are not reset.
VLCD
SEGMENT
DRIVER
&
LATCH
VLCD1
COMMON
DRIVER
VLCD2
VSS
SHIFT
REGISTER
TEST
OSC
CLOCK
CONTROL
REGISTER
GENERATOR
DO
CCB
DI
CL
CE
INTERFACE
KEY
BUFFER
VDD
VDET
KEY
SCAN
Blocks that are reset
No. 7135-17/24
LC75863E, 75863W
3. Output pin states during the reset period
Output pin
S1/P1 to S4/P4
S5 to S23
State during reset
L *5
L
COM1 to COM3
KS1/S24, KS2/S25
KS3 to KS5
KS6
L
L *5
X *6
H
DO
H *7
X: don’t care
Note: *5.These output pins are forcibly set to the segment output function and held low.
*6.When power is first applied, these output pins are undefined until the S0 and S1 control data bits have been transferred.
*7.Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin remains high during the reset period
even if a key data read operation is performed.
Sample Application Circuit 1
1/2 bias (for use with normal panels)
(general-purpose
output ports)
(P1)
(P2)
Used with the
backlight controller
(P3)
(P4)
or other circuit.
OSC
+5 V
VDD
COM1
COM2
COM3
P1/S1
P2/S2
P3/S3
P4/S4
S5
*8
VSS
TEST
+5.5 V
VLCD
VLCD1
VLCD2
C ≥ 0.047 µF
C
S23
S S
2 2
5 4
CE
CL
DI
From the
controller
/
/
(S24)
(S25)
K K K K K
K K K K K K
S S S S S S
6 5 4 3 2 1
I
I I I I
To the controller
DO
5 4 3 2 1
To the controller
power supply
*9
Key matrix
(up to 30 keys)
Note: *8. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the
logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75863E/W is reset by the VDET.
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 7135-18/24
LC75863E, 75863W
Sample Application Circuit 2
1/2 bias (for use with large panels)
(general-purpose
output ports)
(P1)
(P2)
(P3)
(P4)
Used with the
backlight controller
or other circuit.
OSC
+5 V
VDD
COM1
COM2
COM3
P1/S1
P2/S2
P3/S3
P4/S4
S5
*8
VSS
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
+5.5 V
TEST
VLCD
R
VLCD1
VLCD2
C
R
S23
S S
2 2
5 4
CE
CL
DI
From the
controller
/
/
(S24)
(S25)
K K K K K
K K K K K K
S S S S S S
6 5 4 3 2 1
I
I I I I
To the controller
DO
5 4 3 2 1
To the controller
power supply
*9
Key matrix
(up to 30 keys)
Note: *8. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the
logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75863E/W is reset by the VDET.
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 7135-19/24
LC75863E, 75863W
Sample Application Circuit 3
1/3 bias (for use with normal panels)
(general-purpose
output ports)
(P1)
(P2)
(P3)
(P4)
Used with the
backlight controller
or other circuit.
OSC
+5 V
VDD
COM1
COM2
COM3
P1/S1
P2/S2
P3/S3
P4/S4
S5
*8
VSS
TEST
+5.5 V
VLCD
VLCD1
VLCD2
C ≥ 0.047 µF
C
C
S23
S S
2 2
5 4
CE
CL
DI
From the
controller
/
/
(S24)
(S25)
K K K K K
K K K K K K
S S S S S S
6 5 4 3 2 1
I
I I I I
To the controller
DO
5 4 3 2 1
To the controller
power supply
*9
Key matrix
(up to 30 keys)
Note: *8. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the
logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75863E/W is reset by the VDET.
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
No. 7135-20/24
LC75863E, 75863W
Sample Application Circuit 4
1/3 bias (for use with large panels)
(general-purpose
output ports)
(P1)
(P2)
(P3)
(P4)
Used with the
backlight controller
or other circuit.
OSC
+5 V
VDD
COM1
COM2
COM3
P1/S1
P2/S2
P3/S3
P4/S4
S5
*8
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
VSS
TEST
+5.5 V
VLCD
R
R
R
VLCD1
VLCD2
C
C
S23
S S
2 2
5 4
CE
CL
DI
From the
controller
/
/
(S24)
(S25)
K K K K K
K K K K K K
S S S S S S
6 5 4 3 2 1
I
I I I I
To the controller
DO
5 4 3 2 1
To the controller
power supply
*9
Key matrix
(up to 30 keys)
Note: *8. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the
logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75863E/W is reset by the VDET.
*9. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of
the external wiring so that signal waveforms are not degraded.
Notes on transferring display data from the controller
The display data (D1 to 75) is transferred to the LC75863E/W in two operations. All of the display data should be
transferred within 30 ms to maintain the quality of the displayed image.
No. 7135-21/24
LC75863E, 75863W
Notes on the controller key data read techniques
1. Timer based key data acquisition
(1) Flowchart
NO
YES
Key data read
processing
(2) Timing chart
Key on
Key on
Key input
Key scan
t5
t6
t5
t5
CE
t8
t8
t8
Key
address
DI
t7
t7
t7
Key data read
DO
Key data read request
t9
t9
t9
t9
Controller
determination
(Key on)
Controller
determination
(Key on)
Controller
determination
(Key off)
Controller
determination
(Key on)
Controller
determination
(Key off)
t5: Key scan execution time when the key data agreed for two key scans. (615T(s))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again.
(1230T(s))
t7: Key address (43H) transfer time
t8: Key data read time
1
fosc
T = ———
(3) Explanation
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must
check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a key has
been pressed and executes the key data read operation.
The period t9 in this technique must satisfy the following condition.
t9>t6+t7+t8
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
No. 7135-22/24
LC75863E, 75863W
2. Interrupt based key data acquisition
(1) Flowchart
NO
YES
Key data read
processing
Wait for at
least t10
NO
YES
Key OFF
(2) Timing chart
Key on
Key on
Key input
Key scan
CE
t5
t5
t6
t5
t8
t8
t8
t8
Key
address
DI
t7
t7
t7
t7
Key data read
DO
Key data read request
t10
t10
Controller
determination
(Key on)
t10
t10
Controller
determination
(Key off)
Controller
Controller
determination determination
(Key off) (Key on)
Controller
Controller
determination
(Key on)
determination
(Key on)
t5: Key scan execution time when the key data agreed for two key scans. (615T(S))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again.
(1230T(S))
t7: Key address (43H) transfer time
t8: Key data read time
1
fosc
T = ———
No. 7135-23/24
LC75863E, 75863W
(3) Explanation
In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller
must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and
executes the key data read operation. After that the next key on/off determination is performed after the time t10 has
elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique must
satisfy the following condition.
t10 > t6
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of December, 2001. Specifications and information herein are
subject to change without notice.
PS No. 7135-24/24
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