LC75864E [SANYO]
1/4 Duty LCD Display Drivers with Key Input Function; 用按键输入功能1/4占空比LCD显示驱动器
| 型号： | LC75864E |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | 1/4 Duty LCD Display Drivers with Key Input Function |
| 文件： | 总26页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN6860
CMOS IC
LC75864E, 75864W
1/4 Duty LCD Display Drivers with Key Input Function
Overview
Package Dimensions
unit: mm
The LC75864E and LC75864W are 1/4 duty LCD display
drivers that can directly drive up to 96 segments and can
control up to four general-purpose output ports. These
products also incorporate a key scan circuit that accepts
input from up to 30 keys to reduce printed circuit board
wiring.
3156-QIP48E
[LC75864E]
17.2
14.0
1.6
1.0
0.35
1.5
36
1.5
25
0.15
37
24
13
Features
• Key input function for up to 30 keys (A key scan is
performed only when a key is pressed.)
• 1/4 duty - 1/2 bias and 1/4 duty - 1/3 bias drive schemes
can be controlled from serial data (up to 96 segments).
• Sleep mode and all segments off functions that are
controlled from serial data
48
0.1
2.7
12
1
• Segment output port/general-purpose output port
function switching that is controlled from serial data
• Serial data I/O supports CCB format communication
with the system controller.
• Direct display of display data without the use of a
decoder provides high generality.
0.8
15.6
SANYO: QIP48E
unit: mm
3163A-SQFP48
[LC75864W]
• Independent V
for the LCD driver block
LCD
9.0
7.0
(V
can be set to in the range V - 0.5 to 6.0 volts.)
DD
LCD
0.75
0.5
0.18
0.75
24
0.15
• Provision of an on-chip voltage-detection type reset
circuit prevents incorrect displays.
25
36
37
• RC oscillator circuit
13
48
1
12
0.5
0.5
•
•
CCB is a trademark of SANYO ELECTRIC CO., LTD.
SANYO: SQFP48
CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D2501TN (OT) No. 6860-1/26
LC75864E, 75864W
Pin Assignment
36
37
25
24
KI5
VDD
COM2
COM1
S22
VLCD
VLCD
1
2
S21
LC75864E
(QIP48E)
LC75864W
(SQFP48)
VLCD
S20
VSS
TEST
OSC
DO
S19
S18
S17
S16
CE
S15
CL
S14
DI
48
13
12
S13
1
Top view
Specifications
Absolute Maximum Ratings at Ta = 25°C, V = 0 V
SS
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
Unit
V
V
max
max
1
V
V
–0.3 to +7.0
–0.3 to +7.0
–0.3 to +7.0
DD
DD
V
LCD
V
LCD
CE, CL, DI
IN
Input voltage
V
2
3
OSC, TEST
–0.3 to V
+ 0.3
+ 0.3
V
IN
DD
V
V
1, V
2, KI1 to KI5
–0.3 to V
LCD
IN
LCD
LCD
V
V
V
I
1
DO
–0.3 to +7.0
OUT
OUT
OUT
Output voltage
2
3
OSC
–0.3 to V
+ 0.3
+ 0.3
300
3
V
DD
S1 to S24, COM1 to COM4, KS1 to KS6, P1 to P4
–0.3 to V
LCD
1
S1 to S24
µA
mA
OUT
OUT
OUT
OUT
I
I
I
2
COM1 to COM4
KS1 to KS6
P1 to P4
Output current
3
4
1
5
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Ta = 85°C
150
mW
°C
–40 to +85
Tstg
–55 to +125
°C
No. 6860-2/26
LC75864E, 75864W
Allowable Operating Ranges at Ta = –40 to +85°C, V = 0 V
SS
Ratings
typ
Parameter
Symbol
Conditions
Unit
V
min
4.5
– 0.5
max
6.0
V
V
DD
DD
Supply voltage
V
V
V
DD
6.0
LCD
LCD
V
V
1
2
V
1
2
2/3 V
V
V
LCD
LCD
LCD
LCD
Input voltage
V
V
1/3 V
LCD
LCD
LCD
LCD
6.0
V
1
2
CE, CL, DI
0.8 V
0.6 V
IH
DD
Input high level voltage
Input low level voltage
V
V
V
KI1 to KI5
V
IH
DD
0
LCD
V
CE, CL, DI, KI1 to KI5
0.2 V
DD
IL
Recommended external
resistance
R
OSC
OSC
43
kΩ
OSC
OSC
Recommended external
capacitance
C
f
680
50
pF
Guaranteed oscillation range
Data setup time
Data hold time
OSC
25
100
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
OSC
t
CL, DI: Figure 2
CL, DI: Figure 2
CE, CL: Figure 2
CE, CL: Figure 2
CE, CL: Figure 2
CL: Figure 2
160
160
160
160
160
160
160
ds
t
dh
CE wait time
t
cp
CE setup time
t
cs
CE hold time
t
ch
High level clock pulse width
Low level clock pulse width
Rise time
t
øH
t
CL: Figure 2
øL
t
r
CE, CL, DI: Figure 2
CE, CL, DI: Figure 2
160
160
Fall time
t
f
1
DO output delay time
DO rise time
t
DO, R = 4.7 kΩ, C = 10 pF* : Figure 2
1.5
1.5
dc
PU
L
1
t
DO, R = 4.7 kΩ, C = 10 pF* : Figure 2
PU
L
dr
Note: *1. Since DO is an open-drain output, these times depend on the values of the pull-up resistor R and the load capacitance C .
PU
L
No. 6860-3/26
LC75864E, 75864W
Electrical Characteristics for the Allowable Operating Ranges
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
max
Hysteresis
V
H
CE, CL, DI, KI1 to KI5
0.1 V
V
V
DD
Power-down detection voltage
Input high level current
Input low level current
Input floating voltage
V
2.5
3.0
3.5
5.0
DET
I
CE, CL, DI: V = 6.0 V
I
µA
µA
V
IH
I
CE, CL, DI: V = 0 V
I
–5.0
50
IL
V
KI1 to KI5
0.05 V
DD
IF
Pull-down resistance
R
KI1 to KI5: V
= 5.0 V
100
250
kΩ
µA
PD
DD
Output off leakage current
I
DO: V = 6.0 V
6.0
OFFH
O
V
V
V
V
1
2
3
4
1
2
3
4
5
KS1 to KS6: I = –500 µA
O
V
V
V
V
– 1.0
– 1.0
– 1.0
– 1.0
0.2
V
– 0.5
V – 0.2
LCD
OH
OH
OH
OH
LCD
LCD
LCD
LCD
LCD
P1 to P4: I = –1 mA
O
Output high level voltage
Output low level voltage
V
S1 to S24: I = –20 µA
O
COM1 to COM4: I = –100 µA
O
V
V
V
V
V
KS1 to KS6: I = 25 µA
O
0.5
0.1
1.5
1.0
1.0
1.0
0.5
OL
OL
OL
OL
OL
P1 to P4: I = 1 mA
O
S1 to S24: I = 20 µA
O
V
COM1 to COM4: I = 100 µA
O
DO: I = 1 mA
O
1/2 V
2/3 V
1/3 V
2/3 V
1/3 V
–
1.0
1/2 V
2/3 V
1/3 V
2/3 V
1/3 V
+
1.0
LCD
LCD
V
V
V
V
1
2
3
4
5
COM1 to COM4: 1/2 bias, I = ±100 µA
O
MID
MID
MID
MID
MID
–
1.0
+
1.0
LCD
LCD
S1 to S24: 1/3 bias, I = ±20 µA
O
–
1.0
+
1.0
LCD
LCD
*2
Output middle level voltage
S1 to S24: 1/3 bias, I = ±20 µA
O
V
–
1.0
+
1.0
LCD
LCD
COM1 to COM4: 1/3 bias, I = ±100 µA
O
–
1.0
+
1.0
LCD
LCD
V
f
COM1 to COM4: 1/3 bias, I = ±100 µA
O
Oscillator frequency
Current drain
OSC: R
= 43 kΩ, C
= 680 pF
40
50
60
kHz
µA
OSC
OSC
OSC
I
1
2
V
V
V
V
V
: Sleep mode
DD
100
540
5
DD
DD
I
: V
= 6.0 V, output open, f
= 50 kHz
OSC
270
DD DD
I
I
I
1
2
3
: Sleep mode
LCD
LCD
LCD
LCD
: V
= 6.0 V, output open, 1/2 bias, f
= 6.0 V, output open, 1/3 bias, f
= 50 kHz
= 50 kHz
100
60
200
120
LCD LCD
OSC
: V
LCD LCD
OSC
Note: *2. Excluding the bias voltage generation divider resistor built into V
1 and V
2. (See Figure 1.)
LCD
LCD
VLCD
VLCD
1
2
To the common segment driver
VLCD
Excluding these resistors.
Figure 1
No. 6860-4/26
LC75864E, 75864W
1. When CL is stopped at the low level
VIH1
CE
VIL
tøH
tdh
tøL
VIH1
50%
VIL
CL
DI
tr
tf
tch
tcp
tcs
VIH1
VIL
tds
tdc
tdr
DO
D0
D1
2. When CL is stopped at the high level
VIH1
CE
VIL
tøL
tøH
VIH1
50%
VIL
CL
DI
tf
tr
tch
tcp tcs
VIH1
VIL
tds
tdh
DO
D0
D1
tdc
tdr
Figure 2
No. 6860-5/26
LC75864E, 75864W
Block Diagram
VLCD
SEGMENT DRIVER & LATCH
SHIFT REGISTER
VLCD
1
2
COMMON
DRIVER
VLCD
VSS
TEST
OSC
CLOCK
GENERATOR
CONTROL
REGISTER
DO
CCB
INTERFACE
DI
CL
CE
KEY BUFFER
VDD
VDET
KEY SCAN
No. 6860-6/26
LC75864E, 75864W
Pin Functions
Handling
when unused
Pin
Pin No.
Function
Active
—
I/O
O
Segment outputs for displaying the display data transferred by serial data
input.
S1/P1 to S4/P4
S5 to S22
1 to 4
Open
Open
5 to 22
The S1/P1 to S4/P4 pins can be used as general-purpose output ports
under serial data control.
COM1
COM2
COM3
COM4
23
24
25
26
Common driver outputs
—
O
The frame frequency f is given by: f = (f /512) Hz.
OSC
O
O
Key scan outputs
Although normal key scan timing lines require diodes to be inserted in the
timing lines to prevent shorts, since these outputs are unbalanced CMOS
transistor outputs, these outputs will not be damaged by shorting when
these outputs are used to form a key matrix. The KS1/S23 and KS2/S24
pins can be used as segment outputs when so specified by the control data.
27
28
KS1/S23
KS2/S24
—
O
Open
GND
29 to 32
KS3 to KS6
Key scan inputs
These pins have built-in pull-down resistors.
33 to 37
44
KI1 to KI5
OSC
H
I
Oscillator connection
An oscillator circuit is formed by connecting an external resistor and
capacitor at this pin.
V
—
H
I/O
DD
CE
CL
I
I
46
47
48
45
43
Serial data interface connections to the controller. Note that DO, being an
open-drain output, requires a pull-up resistor.
GND
CE: Chip enable
CL: Synchronization clock
DI: Transfer data
DI
—
—
—
I
DO: Output data
DO
O
I
Open
—
TEST
This pin must be connected to ground.
Used for applying the LCD drive 2/3 bias voltage externally. Must be
V
V
1
40
—
—
—
I
I
Open
Open
—
LCD
LCD
connected to V
2 when a 1/2 bias drive scheme is used.
LCD
Used for applying the LCD drive 1/3 bias voltage externally. Must be
connected to V 1 when a 1/2 bias drive scheme is used.
2
41
38
LCD
Logic block power supply connection. Provide a voltage of between 4.5 and
6.0 V.
V
—
DD
LCD driver block power supply connection. Provide a voltage of between
V
—
—
—
—
—
—
39
42
LCD
V
– 0.5 and 6.0 V.
DD
V
Power supply connection. Connect to ground.
SS
No. 6860-7/26
LC75864E, 75864W
Serial Data Input
1. When CL is stopped at the low level
CE
CL
DI
0
1
0
0
0
0
1
0
D1 D2
D47 D48
0
0
0
0
0
0
S0 S1 K0 K1 P0 P1 P2 SC DR
Control data
0
Display data
DD
B0 B1 B2 B3 A0 A1 A2 A3
DO
0
1
0
0
0
0
1
0
D49 D50
D95 D96
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Display data
Fixed data
DD
B0 B1 B2 B3 A0 A1 A2 A3
Note: B0 to B3, A0 to A3 ... CCB address
DD ... Direction data
2. When CL is stopped at the high level
CE
CL
DI
0
1
0
0
0
0
1
0
D1 D2
D47 D48
0
0
0
0
0
0
S0 S1 K0 K1 P0 P1 P2 SC DR
Control data
0
Display data
DD
B0 B1 B2 B3 A0 A1 A2 A3
DO
0
1
0
0
0
0
1
0
D49 D50
D95 D96
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Display data
Fixed data
DD
B0 B1 B2 B3 A0 A1 A2 A3
Note: B0 to B3, A0 to A3 ... CCB address
DD ... Direction data
• CCB address......42H
• D1 to D96..........Display data
• S0, S1 ................Sleep control data
• K0, K1...............Key scan output/segment output selection data
• P0 to P2.............Segment output port/general-purpose output port selection data
• SC......................Segment on/off control data
• DR.....................1/2 bias or 1/3 bias drive selection data
No. 6860-8/26
LC75864E, 75864W
Control Data Functions
1. S0, S1: Sleep control data
These control data bits switch between normal mode and sleep mode and set the states of the KS1 to KS6 key scan
outputs during key scan standby.
Control data
S0
Output pin states during key scan standby
KS1 KS2 KS3 KS4 KS5 KS6
Segment outputs
Common outputs
Mode
OSC oscillator
S1
0
0
0
1
1
Normal
Sleep
Sleep
Sleep
Operating
Stopped
Stopped
Stopped
Operating
H
L
H
L
H
L
H
L
H
L
H
H
H
H
1
L
L
L
0
L
L
L
L
H
H
1
H
H
H
H
Note: This assumes that the KS1/S23 and KS2/S24 output pins are selected for key scan output.
2. K0, K1: Key scan output/segment output selection data
These control data bits switch the functions of the KS1/S23 and KS2/S24 output pins between key scan output and
segment output.
Control data
K0
Output pin state
Maximum number of input keys
K1
0
KS1/S23
KS2/S24
KS2
Notes: KSn (n = 1 , 2): Key scan output
Sn (n = 23, 24): Segment output
0
0
1
KS1
S23
S23
30
25
20
1
KS2
✕
S24
✕: don’t care
3. P0 to P2: Segment output port/general-purpose output port selection data
These control data bits switch the functions of the S1/P1 to S4/P4 output pins between the segment output port and
the general-purpose output port.
Control data
Output pin state
S2/P2 S3/P3
P0
0
P1
0
P2
0
S1/P1
S1
S4/P4
S4
S2
S2
P2
P2
P2
S3
S3
S3
P3
P3
0
0
1
P1
S4
Notes: Sn (n = 1 to 4):
Segment output port
0
1
0
P1
S4
0
1
1
P1
S4
Pn (n = 1 to 4):
1
0
0
P1
P4
General-purpose output port
The table below lists the correspondence between the display data and the output pins when these pins are selected to
be general-purpose output ports.
Output pin
S1/P1
Corresponding display data
D1
D5
S2/P2
S3/P3
D9
S4/P4
D13
For example, if the S4/P4 output pin is selected to be a general-purpose output port, the S4/P4 output pin will output
a high level (V ) when the display data D13 is 1, and will output a low level(V ) when D13 is 0.
LCD SS
4. SC: Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
0
Display state
On
Off
1
However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting
segment off waveforms from the segment output pins.
No. 6860-9/26
LC75864E, 75864W
5. DR: 1/2 bias or 1/3 bias drive selection data
This control data bit switches between LCD 1/2 bias or 1/3 bias drive.
DR
0
Drive scheme
1/3 bias drive
1/2 bias drive
1
Display Data and Output Pin Correspondence
Output pin
S1/P1
S2/P2
S3/P3
S4/P4
S5
COM1
D1
COM2
D2
COM3
D3
COM4
D4
Output pin
S13
COM1
D49
D53
D57
D61
D65
D69
D73
D77
D81
D85
D89
D93
COM2
D50
D54
D58
D62
D66
D70
D74
D78
D82
D86
D90
D94
COM3
D51
D55
D59
D63
D67
D71
D75
D79
D83
D87
D91
D95
COM4
D52
D56
D60
D64
D68
D72
D76
D80
D84
D88
D92
D96
D5
D6
D7
D8
S14
D9
D10
D14
D18
D22
D26
D30
D34
D38
D42
D46
D11
D15
D19
D23
D27
D31
D35
D39
D43
D47
D12
D16
D20
D24
D28
D32
D36
D40
D44
D48
S15
D13
D17
D21
D25
D29
D33
D37
D41
D45
S16
S17
S6
S18
S7
S19
S8
S20
S9
S21
S10
S22
S11
KS1/S23
KS2/S24
S12
Note: This is for the case where the output pins S1/P1 to S4/P4, KS1/S23, and KS2/S24 are selected for use as segment outputs.
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D41
0
D42
0
D43
0
D44
0
The LCD segments for COM1, COM2, COM3 and COM4 are off.
The LCD segment for COM4 is on.
0
0
0
1
0
0
1
0
The LCD segment for COM3 is on.
0
0
1
1
The LCD segments for COM3 and COM4 are on.
The LCD segment for COM2 is on.
0
1
0
0
0
1
0
1
The LCD segments for COM2 and COM4 are on.
The LCD segments for COM2 and COM3 are on.
The LCD segments for COM2, COM3 and COM4 are on.
The LCD segment for COM1 is on.
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
The LCD segments for COM1 and COM4 are on.
The LCD segments for COM1 and COM3 are on.
The LCD segments for COM1, COM3 and COM4 are on.
The LCD segments for COM1 and COM2 are on.
The LCD segments for COM1, COM2 and COM4 are on.
The LCD segments for COM1, COM2 and COM3 are on.
The LCD segments for COM1, COM2, COM3 and COM4 are on.
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
No. 6860-10/26
LC75864E, 75864W
Serial Data Output
1. When CL is stopped at the low level
CE
CL
DI
1
1
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
DO
X
KD1 KD2
KD27 KD28 KD29 KD30 SA
Output data
X: don’t care
Note: B0 to B3, A0 to A3 ... CCB address
2. When CL is stopped at the high level
CE
CL
DI
1
1
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2
A3
DO
X
KD1 KD2 KD3
KD28 KD29 KD30 SA
X
Output data
X: don’t care
Note: B0 to B3, A0 to A3 ... CCB address
• CCB address...............43H
• KD1 to KD30.............Key data
• SA...............................Sleep acknowledge data
Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep
acknowledge data (SA) will be invalid.
Output Data
1. KD1 to KD30: Key data
When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and
one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the
relationship between those pins and the key data bits.
KI1
KI2
KI3
KI4
KI5
KS1/S23
KS2/S24
KS3
KD1
KD2
KD3
KD4
KD5
KD6
KD7
KD8
KD9
KD10
KD15
KD20
KD25
KD30
KD11
KD16
KD21
KD26
KD12
KD17
KD22
KD27
KD13
KD18
KD23
KD28
KD14
KD19
KD24
KD29
KS4
KS5
KS6
When the KS1/S23 and KS2/S24 output pins are selected to be segment outputs by control data bits K0 and K1 and a
key matrix of up to 20 keys is formed using the KS3 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to
KD10 key data bits will be set to 0.
2. SA: Sleep acknowledge data
This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data
is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep
mode and 0 in normal mode.
No. 6860-11/26
LC75864E, 75864W
Sleep Mode Functions
Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common
outputs will also go low, and the oscillator on the OSC pin will stop (it will be started by a key press). This reduces
power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. However, note that the
S1/P1 to S4/P4 outputs can be used as general-purpose output ports according to the state of the P0 to P2 control data
bits, even in sleep mode. (See the control data description for details.)
Key Scan Operation Functions
1. Key scan timing
The key scan period is 384 T (s). To reliably determine the on/off state of the keys, the LC75864E/W scans the keys
twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low
level on DO) 800 T (s) after starting a key scan. If the key data does not agree and a key was pressed at that point, it
scans the keys again. Thus the LC75864E/W cannot detect a key press shorter than 800 T (s).
KS1
KS2
KS3
KS4
KS5
KS6
*3
*3
*3
*3
*3
1
1
*3
*3
*3
*3
*3
2
2
3
3
1
T =
fosc
4
4
5
5
6
6
768T (s)
Key on
Note: *3. In sleep mode the high/low state of these pins is determined by the S0 and S1 bits in the control data. Key scan output signals are not output
from pins that are set low.
2. In normal mode
• The pins KS1 to KS6 are set high
• When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key
presses are recognized by determining whether multiple key data bits are set.
1
• If a key is pressed for longer than 800 T (s) (where T =
) the LC75864E/W outputs a key data read request (a
f
OSC
low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, DO will be set high.
• After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75864E/W
performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1
and 10 kΩ).
No. 6860-12/26
LC75864E, 75864W
Key input 1
Key input 2
Key scan
CE
800T(s)
800T(s)
800T(s)
Serial data transfer
Serial data transfer
Key address (43H)
Serial data transfer
Key address
Key address
DI
DO
Key data read
Key data read
Key data read request
Key data read
Key data read request
Key data read request
1
T=
fosc
3. In sleep mode
• The pins KS1 to KS6 are set to high or low by the S0 and S1 bits in the control data. (See the control data
description for details.)
• If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the
OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses
are recognized by determining whether multiple key data bits are set.
1
• If a key is pressed for longer than 800 T (s) (where T =
) the LC75864E/W outputs a key data read request (a
f
OSC
low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if
CE is high during a serial data transfer, DO will be set high.
• After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75864E/W
performs another key scan. However, this does not clear sleep mode. Also note that DO, being an open-drain
output, requires a pull-up resistor (between 1 and 10 kΩ).
• Sleep mode key scan example
Example: S0 = 0, S1 = 1 (sleep with only KS6 high)
When any one of these keys is pressed, the
oscillator on the OSC pin is started and the keys
are scanned.
Note *4. These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the
above example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on
the KS1 to KS5 lines are pressed at the same time.
No. 6860-13/26
LC75864E, 75864W
Key input
(KS6 line)
Key scan
800T(s)
800T(s)
CE
1
Serial data transfer
Serial data transfer
Key address (43H)
Serial data transfer
Key address
T=
fosc
DI
DO
Key data read
Key data read
Key data read request
Key data read request
Multiple Key Presses
Although the LC75864E/W is capable of key scanning without inserting diodes for dual key presses, triple key presses
on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than
these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be
inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should
check the key data for three or more 1 bits and ignore such data.
No. 6860-14/26
LC75864E, 75864W
1/4 Duty, 1/2 Bias Drive Technique
fosc
(Hz)
512
VLCD
VLCD1, VLCD2
0V
COM1
COM2
VLCD
VLCD1, VLCD2
0V
VLCD
COM3
COM4
VLCD1, VLCD2
0V
VLCD
VLCD1, VLCD2
0V
VLCD
VLCD1, VLCD2
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3 and COM4
are turned off.
VLCD
VLCD1, VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM1 are on
VLCD
VLCD1, VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM2 are on.
VLCD
VLCD1, VLCD2
0V
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
VLCD
VLCD1, VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM3 are on.
VLCD
VLCD1, VLCD2
0V
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
VLCD
VLCD1, VLCD2
0V
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
VLCD
LCD driver output when LCD segments
VLCD1, VLCD2
0V
corresponding to COM1, COM2 and COM3 are on.
VLCD
VLCD1, VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM4 are on.
VLCD
VLCD1, VLCD2
0V
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3 and COM4
are on.
VLCD
VLCD1, VLCD2
0V
1/4 Duty, 1/2 Bias Waveforms
No. 6860-15/26
LC75864E, 75864W
1/4 Duty, 1/3 Bias Drive Technique
fosc
(Hz)
512
VLCD
VLCD1
VLCD2
0V
COM1
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
COM2
COM3
VLCD
VLCD1
VLCD2
0V
COM4
VLCD
VLCD1
VLCD2
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3 and COM4
are turned off.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM1 are on
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM2 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments
corresponding to COM1, COM2 and COM3 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM4 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
VLCD
VLCD1
VLCD2
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3 and COM4
are on.
1/4 Duty, 1/3 Bias Waveforms
No. 6860-16/26
LC75864E, 75864W
Voltage Detection Type Reset Circuit (VDET)
This circuit generates an output signal and resets the system when logic block power is first applied and when the
voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage
VDET, which is 3.0 V, typical. To assure that this function operates reliably, a capacitor must be added to the logic
block power supply line so that the logic block power supply voltage V rise time when the logic block power is first
DD
applied and the logic block power supply voltage V fall time when the voltage drops are both at least 1 ms.
DD
(See Figure 3.)
Power Supply Sequence
The following sequences must be observed when power is turned on and off. (See Figure 3.)
• Power on: Logic block power supply (V ) on → LCD driver block power supply (V
) on.
DD
LCD
• Power off: LCD driver block power supply (V
) off → Logic block power supply (V ) off.
DD
LCD
However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off
at the same time.
System Reset
The LC75864E/W supports the reset method described below. When a system reset is applied, display is turned off, key
scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning
become possible.
1. Reset method
• Reset at power-on and power-down
If at least 1 ms is assured as the logic block supply voltage V rise time when logic block power is applied, a
DD
system reset will be applied by the VDET output signal when the logic block supply voltage is brought up. If at
least 1 ms is assured as the logic block supply voltage V fall time when logic block power drops, a system reset
DD
will be applied in the same manner by the VDET output signal when the supply voltage is lowered. Note that the
reset is cleared at the point when all the serial data (the display data D1 to D96 and the control data) has been
transferred, i.e., on the fall of the CE signal on the transfer of the last direction data, after all the direction data has
been transferred. (See Figure 3.)
t1 t2
t3 t4
VDD
VDET
VDET
VLCD
CE
VIL
Display and control data transfer
Undefined
D1 to D48
S0, S1, K0, K1
P0 to P2, SC, DR
Internal data
Defined
Defined
Undefined
Undefined
Internal data (D49 to D96)
Undefined
System reset period
Note:
• t1 ≥ 1 [ms] (Logic block power supply voltage VDD rise time)
• t2 ≥ 0
• t3 ≥ 0
• t4 ≥ 1 [ms] (Logic block power supply voltage VDD fall time)
Figure 3
No. 6860-17/26
LC75864E, 75864W
2. LC75864E/W internal block states during the reset period
• CLOCK GENERATOR
Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined
after the S0 and S1 control data bits are transferred.
• COMMON DRIVER, SEGMENT DRIVER & LATCH
Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
• KEY SCAN
Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.
• KEY BUFFER
Reset is applied and all the key data is set to low.
• CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER
Since serial data transfer is possible, these circuits are not reset.
VLCD
SEGMENT DRIVER & LATCH
V
LCD1
LCD2
VSS
COMMON
DRIVER
V
SHIFT REGISTER
TEST
OSC
CLOCK
GENERATOR
CONTROL
REGISTER
DO
CCB
INTERFACE
DI
CL
CE
KEY BUFFER
VDD
VDET
KEY SCAN
Blocks that are reset
No. 6860-18/26
LC75864E, 75864W
3. Output pin states during the reset period
Output pin
S1/P1 to S4/P4
S5 to S22
State during reset
*5
L
L
L
COM1 to COM4
KS1/S23, KS2/S24
KS3 to KS5
KS6
*5
L
*6
✕
H
*7
DO
H
✕: don’t care
Note: * 5. These output pins are forcibly set to the segment output function and held low.
* 6. When power is first applied, these output pins are undefined until the S0 and S1 control data bits have been transferred.
* 7. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin remains high during the reset
period even if a key data read operation is performed.
No. 6860-19/26
LC75864E, 75864W
Sample Application Circuit 1
1/2 bias (for use with normal panels)
(general-purpose
output ports)
Used with the
backlight controller
or other circuit.
(P1)
(P2)
(P3)
(P4)
OSC
+5V
VDD
COM1
COM2
COM3
COM4
P1/S1
P2/S2
P3/S3
P4/S4
S5
*8
VSS
TEST
+5.5V
VLCD
VLCD
1
VLCD
2
C ≥ 0.047 µF
S22
S
S
2
2
4
CE
CL
From the
controller
3
/
K
S
1
(S23)
(S24)
/
DI K K K K K
I I I I I
DO
K K K K K
S S S S S
6 5 4 3 2
To the controller
To the controller
5 4 3 2 1
*9
power supply
Key matrix
(up to 30 keys)
Note: *8.Add a capacitor to the logic block power supply line so that the logic block power supply voltage V
rise time when power is applied and the logic
DD
block power supply voltage V
fall time when power drops are both at least 1 ms, as the LC75864E/W is reset by the VDET.
DD
*9.The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the
external wiring so that signal waveforms are not degraded.
No. 6860-20/26
LC75864E, 75864W
Sample Application Circuit 2
1/2 bias (for use with large panels)
(general-purpose
output ports)
Used with the
backlight controller
or other circuit.
(P1)
(P2)
(P3)
(P4)
OSC
+5V
VDD
COM1
COM2
COM3
COM4
P1/S1
P2/S2
P3/S3
P4/S4
S5
*8
VSS
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
TEST
+5.5V
VLCD
R
VLCD1
VLCD2
C
R
S22
S
S
2
3
/
2
4
CE
CL
From the
controller
(S23)
(S24)
/
DI K K K K K
I I I I I
DO
K
S
1
K K K K K
S S S S S
6 5 4 3 2
To the controller
To the controller
power supply
5 4 3 2 1
*9
Key matrix
(up to 30 keys)
Note: *8.Add a capacitor to the logic block power supply line so that the logic block power supply voltage V
rise time when power is applied and the logic
DD
block power supply voltage V
fall time when power drops are both at least 1 ms, as the LC75864E/W is reset by the VDET.
DD
*9.The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the
external wiring so that signal waveforms are not degraded.
No. 6860-21/26
LC75864E, 75864W
Sample Application Circuit 3
1/3 bias (for use with normal panels)
(general-purpose
output ports)
Used with the
backlight controller
or other circuit.
(P1)
(P2)
(P3)
(P4)
OSC
+5V
VDD
COM1
COM2
COM3
COM4
P1/S1
P2/S2
P3/S3
P4/S4
S5
*8
VSS
TEST
+5.5V
VLCD
VLCD
VLCD
1
2
C ≥ 0.047 µF
C
C
S22
S
S
2
2
4
CE
CL
From the
controller
3
/
K
S
1
(S23)
(S24)
/
DI K K K K K
I I I I I
DO
K K K K K
S S S S S
6 5 4 3 2
To the controller
To the controller
power supply
5 4 3 2 1
*9
Key matrix
(up to 30 keys)
Note: *8.Add a capacitor to the logic block power supply line so that the logic block power supply voltage V
rise time when power is applied and the logic
DD
block power supply voltage V
fall time when power drops are both at least 1 ms, as the LC75864E/W is reset by the VDET.
DD
*9.The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the
external wiring so that signal waveforms are not degraded.
No. 6860-22/26
LC75864E, 75864W
Sample Application Circuit 4
1/3 bias (for use with large panels)
(general-purpose
output ports)
Used with the
backlight controller
or other circuit.
(P1)
(P2)
(P3)
(P4)
OSC
+5V
VDD
COM1
COM2
COM3
COM4
P1/S1
P2/S2
P3/S3
P4/S4
S5
*8
10 kΩ ≥ R ≥ 1 kΩ
C ≥ 0.047 µF
VSS
TEST
VLCD
+5.5V
R
VLCD
1
R
R
VLCD
2
C
C
S22
S
S
2
3
/
2
4
CE
CL
From the
controller
(S23)
(S24)
/
DI K K K K K
I I I I I
DO
K
S
1
K K K K K
S S S S S
6 5 4 3 2
To the controller
To the controller
power supply
5 4 3 2 1
*9
Key matrix
(up to 30 keys)
Note: *8.Add a capacitor to the logic block power supply line so that the logic block power supply voltage V
rise time when power is applied and the logic
DD
block power supply voltage V
fall time when power drops are both at least 1 ms, as the LC75864E/W is reset by the VDET.
DD
*9.The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the
external wiring so that signal waveforms are not degraded.
Notes on transferring display data from the controller
The display data (D1 to D96) is transferred to the LC75864E/W in two operations. All of the display data should be
transferred within 30 ms to maintain the quality of the displayed image.
No. 6860-23/26
LC75864E, 75864W
Notes on the controller key data read techniques
1. Timer based key data acquisition
(1) Flowchart
Key data read
processing
(2) Timing chart
Key on
Key on
Key input
Key scan
t5
t6
t5
t5
CE
t8
t8
t8
Key
address
DI
t7
t7
t7
Key data read
DO
Key data read request
t9
t9
t9
t9
Controller determination
Controller determination
Controller determination
(Key off)
Controller determination
(Key on)
Controller determination
(Key off)
(Key on)
(Key on)
t5: Key scan execution time when the key data agreed for two key scans. (800 T (s))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1600 T (s))
1
T =
f
OSC
t7: Key address (43H) transfer time
t8: Key data read time
(3) Explanation
In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller
must check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a
key has been pressed and executes the key data read operation.
The period t9 in this technique must satisfy the following condition.
t9 > t6 + t7 + t8
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
No. 6860-24/26
LC75864E, 75864W
2. Interrupt based key data acquisition
(1) Flowchart
Key data read
processing
Wait for at
least t10
(2) Timing chart
Key on
Key on
Key input
Key scan
t5
t5
t6
t5
CE
t8
t8
t8
t8
Key
address
DI
t7
t7
t7
t7
Key data read
DO
Key data read request
t10
t10
t10
t10
Controller
Controller
determination
(Key off)
Controller
determination
(Key on)
Controller
Controller
Controller
determination
(Key on)
determination
(Key on)
determination
(Key on)
determination
(Key off)
t5: Key scan execution time when the key data agreed for two key scans. (800 T (s))
t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1600 T (s))
1
T =
f
OSC
t7: Key address (43H) transfer time
t8: Key data read time
No. 6860-25/26
LC75864E, 75864W
(3)Explanation
In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller
must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and
executes the key data read operation. After that the next key on/off determination is performed after the time t10
has elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique
must satisfy the following condition.
t10 > t6
If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge
data (SA) will be invalid.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of December, 2001. Specifications and information herein are
subject to change without notice.
PS No. 6860-26/26
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