FDMS86150ET100 [ONSEMI]
N 沟道屏蔽门极 PowerTrench® MOSFET 100 V,128A,4.85mΩ;型号: | FDMS86150ET100 |
厂家: | ONSEMI |
描述: | N 沟道屏蔽门极 PowerTrench® MOSFET 100 V,128A,4.85mΩ 开关 脉冲 光电二极管 晶体管 |
文件: | 总8页 (文件大小:360K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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January 2015
FDMS86150ET100
N-Channel Shielded Gate PowerTrench® MOSFET
100 V, 128 A, 4.85 mΩ
Features
Extended TJ rating to 175°C
General Description
Shielded Gate MOSFET Technology
This N-Channel MOSFET is produced using Fairchild
Semiconductor‘s advanced PowerTrench® process that
incorporates Shielded Gate technology. This process has been
optimized for the on-state resistance and yet maintain superior
switching performance.
Max rDS(on) = 4.85 mΩ at VGS = 10 V, ID = 16 A
Max rDS(on) = 7.8 mΩ at VGS = 6 V, ID = 13 A
Advanced Package and Silicon combination for low rDS(on)
and high efficiency
Applications
MSL1 robust package design
100% UIL tested
Primary DC-DC MOSFET
Secondary Synchronous Rectifier
Load Switch
RoHS Compliant
Bottom
Top
Pin 1
S
S
D
D
D
D
S
Pin 1
S
G
S
S
G
D
D
D
D
Power 56
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
Parameter
Ratings
100
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Continuous
V
V
±20
TC = 25 °C
TC = 100 °C
TA = 25 °C
(Note 5)
(Note 5)
(Note 1a)
(Note 4)
(Note 3)
128
90
ID
A
-Continuous
16
-Pulsed
617
EAS
Single Pulse Avalanche Energy
Power Dissipation
Power Dissipation
726
mJ
W
TC = 25 °C
TA = 25 °C
187
PD
(Note 1a)
3.3
TJ, TSTG
Operating and Storage Junction Temperature Range
-55 to +175
°C
Thermal Characteristics
RθJC
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
0.8
45
°C/W
(Note 1a)
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ’’
Tape Width
12 mm
Quantity
FDMS86150ET
FDMS86150ET100
Power 56
3000 units
©2015 Fairchild Semiconductor Corporation
FDMS86150ET100 Rev.C
www.fairchildsemi.com
1
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
100
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
I
D = 250 μA, referenced to 25 °C
72
mV/°C
IDSS
IGSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
VDS = 80 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
1
μA
±100
nA
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
2
3
4
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
I
D = 250 μA, referenced to 25 °C
GS = 10 V, ID = 16 A
-10
mV/°C
V
3.9
6
4.85
7.8
rDS(on)
gFS
Static Drain to Source On Resistance
Forward Transconductance
VGS = 6 V, ID = 13 A
mΩ
VGS = 10 V, ID = 16 A, TJ = 125 °C
VDS = 10 V, ID = 16 A
7.3
53
9.1
S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
3055
696
29
4065
930
50
pF
pF
pF
Ω
VDS = 50 V, VGS = 0 V,
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
0.1
0.7
3.6
Switching Characteristics
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
18
8.3
28
33
17
45
12
62
35
ns
ns
VDD = 50 V, ID = 16 A,
VGS = 10 V, RGEN = 6 Ω
Turn-Off Delay Time
Fall Time
ns
6
ns
Qg
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
VGS = 0 V to 10 V
VGS = 0 V to 5 V
44
nC
nC
nC
nC
Qg
25
VDD = 50 V,
D = 16 A
I
Qgs
Qgd
12.9
9.2
Drain-Source Diode Characteristics
V
GS = 0 V, IS = 2.1 A
(Note 2)
(Note 2)
0.69
0.78
69
1.2
1.3
VSD
Source to Drain Diode Forward Voltage
V
VGS = 0 V, IS = 16 A
trr
Reverse Recovery Time
110
150
ns
IF = 16 A, di/dt = 100 A/μs
Qrr
Reverse Recovery Charge
94
nC
Notes:
2
1. R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is determined by the user's board design.
θCA
θJA
a. 45 °C/W when mounted on a
b. 115 °C/W when mounted on a
minimum pad of 2 oz copper.
2
1 in pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. E of 726 mJ is based on starting T = 25 °C, L = 3 mH, I = 22 A, V = 100 V, V = 10 V, 100% test at L = 0.1 mH, I = 69 A.
AS
J
AS
DD
GS
AS
4. Pulse Id please refer to Fig.11 SOA curve for detail.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
©2015 Fairchild Semiconductor Corporation
FDMS86150ET100 Rev.C
www.fairchildsemi.com
2
Typical Characteristics TJ = 25 °C unless otherwise noted
300
4
3
2
1
0
VGS = 10 V
VGS = 8 V
VGS = 7 V
VGS = 5 V
250
200
150
100
50
VGS = 6 V
VGS = 7 V
VGS = 6 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 10 V
VGS = 8 V
PULSE DURATION = 80 μs
VGS = 5 V
DUTY CYCLE = 0.5% MAX
0
0
1
2
3
4
5
0
50
100
150
200
250
300
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
Figure2. N o r m a l i z e d O n - R e s i s ta n c e
vs Drain Current and Gate Voltage
20
2.5
ID = 16 A
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID = 16 A
VGS = 10 V
15
10
5
2.0
1.5
1.0
0.5
TJ = 150 o
C
TJ = 25 o
C
0
4
5
6
7
8
9
10
-75 -50 -25
0
25 50 75 100 125 150 17
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure4. On-Resistance vs Gate to
Source Voltage
Figure 3. Normalized On Resistance
vs Junction Temperature
300
300
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 0 V
100
250
TJ = 175 o
C
VDS = 5 V
200
10
1
TJ = 25 oC
150
100
0.1
TJ = -55 o
C
TJ = 175 o
C
TJ = 25 o
C
0.01
0.001
50
0
TJ = -55 o
C
2
3
4
5
6
7
8
0.0
0.2
0.4
0.6
0.8
1.0
1.
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure6. Source to Drain Diode
Forward Voltage vs Source Current
©2015 Fairchild Semiconductor Corporation
FDMS86150ET100 Rev.C
www.fairchildsemi.com
3
Typical Characteristics TJ = 25 °C unless otherwise noted
10
10000
1000
100
ID = 16 A
VDD = 50 V
8
6
4
2
0
Ciss
VDD = 25 V
VDD = 75 V
Coss
Crss
f = 1 MHz
= 0 V
V
GS
10
0.1
1
10
100
0
10
20
30
40
50
VDS, DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
g
Figure 7. Gate Charge Characteristics
Figure8. C a p a c i t a n c e v s D r a i n
to Source Voltage
150
100
10
1
TJ = 25 o
C
120
90
60
30
0
VGS = 10 V
TJ = 100 o
C
VGS = 6 V
TJ = 150 o
C
RθJC = 0.8 oC/W
0.01
0.1
1
10
100
1000
25
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
tAV, TIME IN AVALANCHE (ms)
Figure9. U n c l a m p e d I n d u c t i v e
Switching Capability
Figure10. Maximum Continuous Drain
Current vs Case Temperature
1000
100
10
50000
SINGLE PULSE
θJC = 0.8oC/W
TC = 25 oC
10 μs
R
10000
1000
THIS AREA IS
LIMITED BY rDS(on)
100 μs
1
1 ms
SINGLE PULSE
TJ = MAX RATED
RθJC = 0.8 oC/W
TC = 25 oC
10 ms
0.1
100ms/DC
CURVE BENT TO
MEASURED DATA
100
50
0.01
10-5
10-4
10-3
t, PULSE WIDTH (sec)
10-2
10-1
0.1
1
10
100
500
1
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
Figure12. Single Pulse Maximum
Power Dissipation
©2015 Fairchild Semiconductor Corporation
FDMS86150ET100 Rev.C
www.fairchildsemi.com
4
Typical Characteristics TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.05
P
DM
0.1
0.02
0.01
t
1
t
2
SINGLE PULSE
0.01
NOTES:
Z
(t) = r(t) x R
= 0.8 °C/W
θJC
θJC
R
θJC
Peak T = P
x Z (t) + T
θJC C
J
DM
Duty Cycle, D = t / t
1
2
0.001
10-5
10-4
10-3
t, RECTANGULAR PULSE DURATION (sec)
10-2
10-1
1
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
©2015 Fairchild Semiconductor Corporation
FDMS86150ET100 Rev.C
www.fairchildsemi.com
5
5.10
4.90
A
4.42
3.81
PKG
C
L
B
7
6
5
8
8
5
1.14
KEEP OUT AREA
3.65
6.25
5.90
C
PKG
L
6.61
4.79
1.27
1
4
PIN #1
IDICATOR
TOP VIEW
SIDE VIEW
1
2
1.27
3
4
0.61
SEE
DETAIL A
3.81
5.10
LAND PATTERN
RECOMMENDATION
3.81
1.27
0.10
C A B
0.47
0.37
(0.38)
(8X)
1
4
(0.35)
0.65
0.55
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC MO-240, ISSUE A, VAR. AA,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
PIN #1
INDICATOR
4.66
4.46
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-2009.
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING FILE NAME: PQFN08JREV3.
8
5
0.70
4.33
4.13
BOTTOM VIEW
0.10 C
1.10
0.90
0.08 C
C
0.05
0.00
0.25
0.15
SEATING
PLANE
SCALE: 2:1
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ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
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