FDMD82100 [ONSEMI]
双 N 沟道 Power Trench® MOSFET 100V，25A，19mΩ;
| 型号： | FDMD82100 |
| 厂家： | 
ONSEMI |
| 描述： | 双 N 沟道 Power Trench® MOSFET 100V，25A，19mΩ 开关 光电二极管 晶体管 |
| 文件： | 总8页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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MOSFET – Dual N-Channel,
POWERTRENCH)
V
r
MAX
I
D
MAX
DS
DS(ON)
100 V
ꢁ
ꢂ
m
ꢀ
@
1
0
V
25 A
33 mꢀ @ 6 V
100 V, 25 A, 19 mW
Pin 1
FDMD82100
General Description
This device includes two 100 V N−Channel MOSFETs in a dual
Power (3.3 mm X 5 mm) package. HS source and LS Drain internally
connected for half/full bridge, low source inductance package,
Top
Bottom
Power 3.3 x 5
low r
/Qg FOM silicon.
DS(on)
PQFN12 3.3X5, 0.65P
CASE 483BN
Features
• Max r
= 19 mꢀ at V = 10 V, I = 7 A
= 33 mꢀ at V = 6 V, I = 5.5 A
GS D
DS(on)
GS
D
• Max r
DS(on)
• Ideal for Flexible Layout in Primary Side of Bridge Topology
• 100% UIL Tested
MARKING DIAGRAM
• Kelvin High Side MOSFET Drive Pin−out Capability
• This Device is Pb−Free, Halide Free and RoHS Compliant
AYWWZZ
82100
Applications
• Synchronous Buck : Primary Switch of Half/Full bridge converter
for telecom
• Motor Bridge: Primary Switch of Half/Full bridge converter
for BLDC motor
A
YWW
ZZ
= Assembly Plant Code
= Date Code (Year & Week)
= Lot Code
82100
= Specific Device Code
• MV POL: 48 V Synchronous Buck Switch
MOSFET MAXIMUM RATINGS (T = 25°C unless otherwise noted)
PIN CONNECTIONS
A
Symbol
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current Continuous
Rating
100
20
Unit
V
V
DS
V
GS
D1
D1
D1
G2
S2
S2
G1
V
G1R
I
D
T
C
= 25°C
25
A
D2/S1
Continuous T = 25°C
7
A
(Note 1a)
D2/S1
Pulsed (Note 4)
80
D2/S1
D2/S1
E
Single Pulse Avalanche Energy (Note 3)
121
mJ
W
AS
P
Power Dissipation (Note 1a) T = 25°C
2.1
1
D
A
Power Dissipation (Note 1b) T = 25°C
A
T , T
Operating and Storage Junction
Temperature Range
−55 to + 150
°C
J
STG
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 6 of this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
February, 2023 − Rev. 3
FDMD82100/D
FDMD82100
THERMAL CHARACTERISTICS
Symbol
Parameter
Ratings
3.1
Unit
R
ꢃ
JC
R
ꢃ
JA
R
ꢃ
JA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
(Top Source)
(Note 1a)
°C/W
60
(Note 1b)
130
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
OFF CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
I
I
= 250 ꢄ A, V = 0 V
GS
100
−
−
−
V
DSS
D
Breakdown Voltage Temperature
Coefficient
= 250 ꢄ A, referenced to 25°C
−
70
mV/°C
ꢅ BVDSS
ꢅ TJ
D
I
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V
V
= 80 V, V
GS
= 0 V
= 0 V
−
−
−
−
1
ꢄ A
DSS
GSS
DS
I
=
20 V, V
100
nA
GS
DS
ON CHARACTERISTICS
V
Gate to Source Threshold Voltage
V
I
= V , I = 250 ꢄ A
2
3.3
4
V
GS(th)
GS
DS
D
Gate to Source Threshold Voltage
Temperature Coefficient
= 250 ꢄ A, referenced to 25°C
−
−9
−
mV/°C
ꢅ VGS(th)
ꢅ TJ
D
r
Static Drain to Source On Resistance
Forward Transconductance
V
GS
V
GS
V
GS
V
DS
= 10 V, I = 7 A
−
−
−
−
15
23
27
18
19
33
35
−
mꢀ
DS(on)
D
= 6 V, I = 5.5 A
D
= 10 V, I = 7 A, T = 125°C
D
J
g
FS
= 5 V, I = 7 A
S
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
DS
= 50 V, V = 0 V, f = 1 MHz
−
−
805
176
8
1070
235
15
pF
pF
pF
ꢀ
iss
GS
C
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
oss
C
−
rss
R
0.1
1.8
3.6
g
SWITCHING CHARACTERISTICS
td
Turn−On Delay Time
Rise Time
V
V
= 50 V, I = 7 A,
−
−
−
−
−
−
−
−
9.4
3.2
15
3.3
12
8
19
10
27
10
17
11
−
ns
(on)
DD
GS
D
= 10 V, R
= 6 ꢀ
GEN
t
r
t
Turn−Off Delay Time
Fall Time
d(off)
t
f
Q
Total Gate Charge
V
GS
V
GS
V
DD
= 0 V to 10 V, V = 50 V, I = 7 A
nC
g(TOT)
DD
D
= 0 V to 6 V, V = 50 V, I = 7 A
DD
D
Q
Q
Gate to Source Charge
= 50 V, I = 7 A
3.9
2.7
nC
nC
gs
D
Gate to Drain “Miller” Charge
−
gd
DRAIN−SOURCE DIODE CHARACTERISTICS
V
Source to Drain Diode Forward Voltage
Reverse Recovery Time
V
= 0 V, I = 7 A
(Note 2)
−
−
−
0.8
46
48
1.2
74
77
V
SD
GS
S
t
I = 7 A, di/dt = 100 A/ꢄ s
F
ns
nC
rr
Q
Reverse Recovery Charge
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
FDMD82100
NOTES:
1. R
2
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. R
is guaranteed
ꢃ
ꢃ
JC
JA
by design while R
is determined by the user’s board design.
ꢃ
CA
b. 130°C/W when mounted on
a minimum pad of 2 oz copper
a. 60°C/W when mounted on
2
a 1 in pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 ꢄ s, Duty cycle < 2.0%.
3. E of 121 mJ is based on starting T = 25°C, L = 3 mH, I = 9 A, V = 100 V, V = 10 V, 100% tested at L = 0.1 mH, I = 30 A.
AS
J
AS
DD
GS
AS
4. Pulse Id refers to Figure 11. Forward Bias Safe Operation Area.
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3
FDMD82100
TYPICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
80
4
V
GS
V
GS
= 10 V
= 8 V
V
GS
= 7 V
V
GS
= 5 V
3
2
1
0
60
40
V
= 6 V
Pulse Duration = 80 ꢄs
Duty Cycle = 0.5% Max
GS
V
= 7 V
GS
V
= 8 V
GS
V
V
= 6 V
= 5 V
GS
20
0
V
GS
= 10 V
GS
Pulse Duration = 80 ꢄs
Duty Cycle = 0.5% Max
40
I , Drain Current (A)
0
20
60
80
1
2
3
4
5
0
V
, Drain to Source Voltage (V)
D
DS
Figure 1. On Region Characteristics
Figure 2. Normalized On−Resistance
vs. Drain Current and Gate Voltage
2.2
2.0
1.8
1.6
1.4
1.2
1.0
100
75
I
V
= 7 A
D
Pulse Duration = 80 ꢄs
Duty Cycle = 0.5% Max
I
D
= 7 A
= 10 V
GS
50
25
0
T = 125°C
J
T = 25°C
0.8
0.6
J
−75 −50 −25
0
25
50
75 100 125 150
4
5
6
7
8
9
10
V
GS
, Gate to Source Voltage (V)
T , Junction Temperature (5C)
J
Figure 3. Normalized On Resistance
vs. Junction Temperature
Figure 4. On−Resistance vs. Gate to Source
Voltage
100
10
80
60
V
GS
= 0 V
Pulse Duration = 80 ꢄs
Duty Cycle = 0.5% Max
V
DS
= 5 V
T = 150°C
J
1
T = 25°C
40
20
0
J
0.1
T = 150°C
J
T = −55°C
J
0.01
0.001
T = 25°C
J
T = −55°C
J
6
0.0
0.2
0.4
0.6
0.8
1.0
1.2
2
4
8
10
V
GS
, Gate to Source Voltage (V)
V
SD
, Body Diode Forward Voltage (V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode
Forward Voltage vs. Source Current
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4
FDMD82100
TYPICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (continued)
J
10
8
10000
I
D
= 7 A
V
= 50 V
DD
C
iss
1000
100
10
V
DD
= 25 V
V
= 75 V
DD
6
C
oss
rss
4
C
2
0
f = 1 MHz
= 0 V
V
GS
1
0
4
0.1
1
10
100
2
6
8
10
12
14
V
DS
, Drain to Source Voltage (V)
Q , Gate Charge (nC)
g
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs. Drain to Source Voltage
40
30
20
10
0
50
10
R
= 3.1°C/W
ꢃ
JC
T = 25°C
J
V
= 10 V
GS
Limited by Package
T = 100°C
J
V
GS
= 6 V
T = 150°C
J
1
0.001
0.01
0.1
10
100
25
50
75
100
125
150
1
t
, Time in Avalanche (ms)
AV
T , Case Temperature (5C)
C
Figure 9. Unclamped Inductive Switching
Capability
Figure 10. Maximum Continuous Drain Current
vs. Case Temperature
200
100
10000
1000
100
Single pulse
R
= 3.1°C/W
ꢃ
JC
T
C
= 25°C
10 ꢄs
10
1
This Area is
Limited by r
100 ꢄs
DS(on)
Single Pulse
T = Max Rated
1 ms
10 ms
DC
J
ꢃ
Curve Bent to
R
= 3.1°C/W
JC
Measured Data
T
C
= 25°C
0.1
0.1
1
10
−5
−4
−3
−2
−1
1
10
100
300
10
10
10
10
1
t, Pulse Width (s)
V
DS
, Drain to Source Voltage (V)
Figure 11. Forward Bias Safe Operating Area
Figure 12. Single Pulse Maximum
Power Dissipation
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5
FDMD82100
TYPICAL CHARACTERISTICS (T = 25°C UNLESS OTHERWISE NOTED) (CONTINUED)
J
2
1
DUTY CYCLE−DESCENDING ORDER
D = 0.5
PDM
0.2
0.1
0.05
0.02
0.01
t1
0.1
t2
NOTES:
Z
ꢃ
(t) = r(t) x R
ꢃ
JC
JC
R
= 3.1°C/W
ꢃ
JC
Single pulse
10−4
Peak T = P
Duty Cycle: D = t / t
x Z (t) + T
ꢃ
JC C
J
DM
0.01
1
2
0.005
10−3
10−2
10−5
10−1
1
t, Rectangular Pulse Duration (s)
Figure 13. Junction−to−Case Transient Thermal Response Curve
PACKAGE MARKING AND ORDERING INFORMATION
Device
Device Marking
Package
Reel Size
Tape Width
Quantity
FDMD82100
82100
PQFN12 3.3x5, 0.65P
(Power 3.3 x 5)
(Pb−Free, Halide Free)
13”
12 mm
3000 Units
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other
countries.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PQFN12 3.3X5, 0.65P
CASE 483BN
ISSUE A
DATE 26 AUG 2021
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13670G
PQFN12 3.3X5, 0.65P
PAGE 1 OF 1
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