MSM54V24632A [OKI]
131,072-Word x 32-Bit x 2-Bank SGRAM without Graphics Functions; 131,072字×32位×2 ，银行SGRAM无图形功能
| 型号： | MSM54V24632A |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 131,072-Word x 32-Bit x 2-Bank SGRAM without Graphics Functions |
| 文件： | 总29页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
¡ Semiconductor
11 Feb. 1998
MSM54V24632A
131,072-Word ¥ 32-Bit ¥ 2-Bank SGRAM without Graphics Functions
DESCRIPTION
The MSM54V24632A is a synchronous graphics random access memory without graphics
orientedfunctions;BlockWrite,Writeperbit,SinglewriteandBurststop. Itis organizedas128K
words ¥ 32 bits ¥ 2 banks.
This device can operate up to 125MHz by using synchronous interface.
FEATURES
• 131,072-words ¥ 32 bits ¥ 2 banks memory
• Single 3.3 V±0.3 V power supply
• LVTTL compatible inputs and outputs
• All input signals are latched at rising edge of system clock
• Auto precharge and controlled precharge
• Internal pipelined operation: column address can be changed every clock cycle
• Dual internal banks controlled by A9 (Bank Address: BA)
• Independent byte operation via DQM0 to DQM3
• Simplified function (No Block write, Write per bit, Single write and Burst stop)
• Programmable burst sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable CAS latency (1, 2 and 3)
• Power Down operation and Clock Suspend operation
• Auto refresh and Self refresh capability
• 1,024 refresh cycle / 16 ms
• Package :
100-pin plastic QFP
(QFP100-P-1420-0.65-BK4)
(Product : MSM54V24632A-xxGS-BK4)
xx indicates speed rank.
PRODUCT FAMILY
Clock Frequency
MHz (Max.)
Family
Package
MSM54V24632A-8
MSM54V24632A-10
MSM54V24632A-12
125
100
83
100-pin Plastic QFP (14 ¥ 20 mm)
1
MSM54V24632A
¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
100pin Plastic QFP
DQ3
Vcc(Q)
DQ4
1
2
3
4
5
6
7
8
9
80 DQ28
79 Vcc(Q)
78 DQ27
77 DQ26
76 Vss(Q)
75 DQ25
74 DQ24
73 Vcc(Q)
72 DQ15
71 DQ14
70 Vss(Q)
69 DQ13
68 DQ12
67 Vcc(Q)
66 Vss
DQ5
Vss(Q)
DQ6
DQ7
Vcc(Q)
DQ16
DQ17 10
Vss(Q) 11
DQ18 12
DQ19 13
Vcc(Q) 14
Vcc 15
Vss 16
65 Vcc
DQ20 17
DQ21 18
Vss(Q) 19
DQ22 20
DQ23 21
Vcc(Q) 22
DQM0 23
DQM2 24
WE 25
64 DQ11
63 DQ10
62 Vss(Q)
61 DQ9
60 DQ8
59 Vcc(Q)
58 NC
57 DQM3
56 DQM1
55 CLK
CAS 26
RAS 27
CS 28
54 CKE
53 NC
A9 29
52 NC
NC 30
51 A8
Pin Name
Function
System Clock
Pin Name
Function
CLK
CS
DQM0~DQM3 Data Input/Output Mask
Chip Select
DQi
Data Input/Output
CKE
A0 - A8
A9
Clock Enable
VCC
Power Supply (3.3 V)
Ground (0 V)
Address
VSS
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
VCC(Q)
VSS(Q)
NC
Data Output Power Supply (3.3 V)
Data Output Ground (0 V)
No Connection
RAS
CAS
WE
Note:
3
The same power supply voltage must be provided to every V pin and V (Q)pin.
CC CC
The same GND voltage level must be provided to every V pin and V (Q) pin.
SS
SS
¡ Semiconductor
MSM54V24632A
PIN DESCRIPTION
CLK
Fetches all inputs at the "H" edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
CS
DQM0, DQM1, DQM2 and DQM3.
CKE
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked that the subsequent CLK operation is deactivated.
CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Address
A9
Row address: RA0 – RA8
Column address: CA0 – CA7
Selects bank to be activated during row address latch time and selects bank for precharge and read/
write during column address latch time. A9= "L" : Bank A, A9= "H" : Bank B
RAS
CAS
WE
Functionality depends on the combination. For details, see the function truth table.
DQM0
~DQM3
Masks the read data of two clocks later when DQM0~DQM3 is set "H" at the "H" edge of the clock signal.
Masks the write data of the same clock when DQM0~DQM3 is set "H" at the "H" edge of the clock signal.
Data inputs/outputs are multiplexed on the same pin.
DQi
3
MSM54V24632A
¡ Semiconductor
BLOCK DIAGRAM
CKE
CLK
CS
Progra-
ming
Register
Latency
& Burst
Controller
I/O
Controller
RAS
CAS
Timing
Register
WE
DQM0
DQM1
DQM2
DQM3
Bank
Controller
A9
Internal
Col.
Address
Counter
Input
Data
Register
A0-A9
Input
Buffers
32
32
Column
Address
Buffers
8
8
Column Decoders
Sense Amplifier
32
32
16
Read
Data
Register
Output
Buffers
DQ0-DQ31
Internal
Row
Address
Counter
4Mb
Memory
Cells
Row
Decoders
Word
Drivers
Row
Address
Buffers
4Mb
Memory
Cells
Row
Decoders
Word
Drivers
9
9
Sense Amplifier
Column Decoders
5
¡ Semiconductor
MSM54V24632A
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(Voltages referenced to VSS
)
Parameter
Symbol
Rating
–0.5 to 4.6
–0.5 to 4.6
–55 to 150
1
Unit
V
Voltage on Any Pin Relative to VSS
VIN, VOUT
V
CC Supply Voltage
VCC, VCC
Tstg
Q
V
Storage Temperature
Power Dissipation
°C
W
PD*
Short Circuit Current
Operating Temperature
IOS
50
mA
°C
Topr
0 to 70
*: Ta = 25°C
Recommended Operating Conditions
(Voltages referenced to VSS = 0 V)
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
Min.
3.0
Typ.
3.3
—
Max.
3.6
Unit
VCC, VCC
VIH
Q
V
V
V
2.0
V
CC + 0.2
0.8
VIL
–0.3
—
Capacitance
(VCC = 3.3 V 0.3 V, Ta = 25°C, f = 1 MHꢀ)
Parameter
Symbol
Typ.
Max.
Unit
Input Capacitance (A0 - A9)
Input Capacitance (CLK, CKE, CS,
RAS, CAS, WE, DQM0~DQM3)
Input/Output Capacitance
(DQ0 - DQ31)
CIN1
—
5
pF
CIN2
—
5
7
pF
pF
COUT
—
5
MSM54V24632A
¡ Semiconductor
DC Characteristics
Condition
CKE
Version
–10
Min.Max.Min.Max.Min.Max.
Parameter
Symbol
Unit Note
–8
–12
Bank
Others
IOH = –2 mA 2.4
Output High Voltage VOH
Output Low Voltage VOL
Input Leakage Current ILI
Output Leakage Current ILO
—
—
—
—
—
—
—
—
—
2.4
—
—
2.4
—
—
V
V
IOL = 2 mA
—
0.4
0.4
0.4
—
—
–
10 10
10 10
–
10 10
10 10
–
10 10 mA
10 10 mA
–
–
–
ICC
1
One Bank
Active
CKE ≥ VIH tCC = min
RC = min
t
—
180
—
160
—
140 mA 1, 2
Average Power
Supply Current
(Operating)
No Burst
ICC1D Both Banks
Active
CKE ≥ VIH tCC = min
t
t
RC = min
RRD = min
—
240
—
200
—
180 mA 1, 2
No Burst
Power Supply
Current (Stand by)
ICC
2
Both Banks
Precharge
CKE ≥ VIH tCC = min
—
—
80
35
—
—
70
30
—
—
60 mA
25 mA
3
3
Average Power
Supply Current
(Clock Suspension)
ICC3S Both Banks
Active
CKE £ VIL tCC = min
Average Power
Supply Current
(Active Stand by)
ICC
3
One Bank
Active
CKE ≥ VIH tCC = min
—
—
—
95
—
—
—
80
—
—
—
70 mA
3
Power Supply
Current (Burst)
ICC
4
Both Banks
Active
CKE ≥ VIH tCC = min
CKE ≥ VIH tCC = min
210
170
180
150
160 mA 1, 2
I
CC5 One Bank
Power Supply
Current
Active
tRC = min
130 mA
2
(Auto-Refresh)
Average Power
Supply Current
(Self-Refresh)
ICC
6
7
Both Banks
Precharge
CKE £ VIL tCC = min
CKE £ VIL tCC = min
—
—
2
2
—
—
2
2
—
—
2
2
mA
mA
Average Power
Supply Current
(Power down)
ICC
Both Banks
Precharge
Notes: 1. Measured with outputs open.
2. Address and data can be changed once or not be changed during one cycle.
3. Address and data can be changed once or not be changed during two cycles.
7
¡ Semiconductor
MSM54V24632A
Mode Set Address Keys
Operation Code
CAS Latency
A6 A5 A4
Burst Type
Burst Length
A2 A1 A0 BT = 0
A8
0
A7
0
TM
CL
A3
BT
BT = 1
Mode Setting
Reserved
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
1
0
1
Sequential
Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
2
4
8
0
1
2
4
8
1
0
2
1
1
3
Reserved
Reserved
Reserved
Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Note:
A9 should stay "L" during mode set cycle.
POWER ON SEQUENCE
1. With inputs in NOP state, turn on the power supply and start the system clock.
2. After the V voltage has reached the specified level, pause for 200 ms or more with
CC
the input kept in NOP state.
3. Issue the precharge all bank command.
4. Apply an Auto-refresh eight or more times.
5. Enter the mode register setting command.
7
MSM54V24632A
¡ Semiconductor
AC Characteristics 1
Note 1, 2
MSM54V24632A-8 MSM54V24632A-10 MSM54V24632A-12
Parameter
Symbol
Unit Note
Min.
8
Max.
—
—
—
7
Min.
10
15
30
—
—
—
3
Max.
—
—
—
9
Min.
12
18
36
—
—
—
4
Max.
—
CL = 3
Clock Cycles Time CL = 2
CL = 1
ns
ns
ns
tCC
12
24
—
—
—
2.5
2.5
2.5
1
—
—
CL = 3
10
ns
ns
ns
ns
ns
ns
ns
3, 4
3, 4
3, 4
Access Time from
CL = 2
tAC
10
22
—
—
—
—
13
27
—
—
—
—
15
Clock
CL = 1
Clock "H" Pulse Time
Clock "L" Pulse Time
Input Setup Time
32
tCH
tCL
tSI
—
3
4
—
3
3
—
Input Hold Time
tHI
1
1.5
—
Output Low Impedance
Time form Clock
tOLZ
tOHZ
3
—
6
3
—
8
3
—
10
ns
ns
Output High Impedance
Time form Clock
—
—
—
Output Hold from Clock
RAS Cycle Time
tOH
tRC
3
—
—
—
105
—
—
3
—
—
—
105
—
—
3
106
36
72
36
24
—
—
—
105
—
—
ns
ns
ns
ns
ns
ns
3
72
24
48
24
16
90
30
60
30
20
RAS Precharge Time
RAS Active Time
tRP
tRAS
tRCD
tWR
RAS to CAS Delay Time
Write Recovery Time
Write Command Input Time
form Output
tOWD
16
16
—
—
20
20
—
—
24
24
—
—
ns
ns
RAS to RAS Bank Active
Delay Time
tRRD
tREF
Refresh Time
—
8
16
—
5
—
10
1
16
—
5
—
12
1
16
—
5
ms
ns
ns
Power-down Exit Set-up Time tPDE
Input Level Transition Time tT
1
9
¡ Semiconductor
MSM54V24632A
AC Characteristics 2
Note 1, 2
Parameter
Symbol
Unit Note
MSM54V24632A-8 MSM54V24632A-10 MSM54V24632A-12
CL
3
8
1
1
2
12
1
1
24
1
3
10
1
2
15
1
1
30
1
3
12
1
2
18
1
1
36
1
tCK
ns
CAS to CAS Delay Time (Min.) lCCD
Cycle
Cycle
Clock Disable Time from CKE
lCKE
1
1
1
1
1
1
1
1
Data Output High Impedance
Time from DQM
lDOZ
Cycle
Cycle
Cycle
Cycle
Cycle
2
0
0
2
3
2
0
0
2
3
2
0
0
1
3
2
0
0
2
3
2
0
0
2
3
2
0
0
1
3
2
0
0
2
3
2
0
0
2
3
2
0
0
1
3
Data Input Mask Time from
DQM
lDOD
lDWD
lROH
lMRD
Data Input Time from Write
Command
Data Output High Impedance Time from
Precharge Command
Active Command Input Time from Mode
Register Set Command Input (Min.)
9
MSM54V24632A
¡ Semiconductor
Notes : 1. AC measurements assume t = 1 ns.
T
2. The reference level for timing of input signals is 1.4 V.
3. Output load.
1.4 V
50 W
Z = 50 W
Output
30 pF
4. An access time is measured at 1.4 V.
5. If t is longer than 1ns, the reference level for timing of input signals is V and V .
T
IH
IL
11
¡ Semiconductor
MSM54V24632A
TIMING WAVEFORM
Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tRC
CKE
CS
tRP
RAS
tRCD
CAS
Ra
Ca0
Rb
Cb0
ADDR
A9
Ra
Rb
A8
tOH
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
DQ
tOHZ
tAC
tWR
WE
DQM0
~DQM3
Row Active Read Command
Row Active Write Command
Precharge Command
Precharge Command
11
MSM54V24632A
¡ Semiconductor
Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 2, Burst Length = 4
tCH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tCC
tCL
High
CKE
CS
tHI
tSI
tHI
RAS
lCCD
tHI
tSI
tSI
CAS
tSI
tSI
Ra
Ca
Cb
Cc
ADDR
tHI
tHI
BS
Ra
BS
BS
BS
BS
A9
A8
DQ
tAC
tHI
tSI
Qa
Db
Qc
tOLZ
tHI
tOH
tOHZ
tOWD
WE
tSI
DQM0
~DQM3
Row Active
Write Command
Precharge Command
Read Command
Read Command
13
¡ Semiconductor
MSM54V24632A
*Notes: 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CKE and DQM0,
DQM1, DQM2, DQM3 are invalid.
2. When issuing an active, read or write command, the bank is selected by A9.
A9
0
Active, read or write
Bank A
1
Bank B
3. The auto precharge function is enabled or disabled by the A8 input when the read or write command is
issued.
A8
0
A9
0
Operation
After the end of burst, bank A holds the active status.
After the end of burst, bank A is precharged automatically.
After the end of burst, bank B holds the active status.
After the end of burst, bank B is precharged automatically.
1
0
0
1
1
1
4. When issuing a precharge command, the bank to be precharged is selected by the A8 and A9 inputs.
A8
0
A9
0
Operation
Bank A is precharged.
0
1
Bank B is precharged.
1
X
Both banks A and B are precharged.
5. The input data and the write command are latched by the same clock (Write latency = 0).
6. The output is forced to high impedance by (1 CLK + tOHZ) after DQMi entry.
13
MSM54V24632A
¡ Semiconductor
Page Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
Bank A Active
RAS
CAS
lCCD
Ca0
Cb0
Cc0
Cd0
ADDR
A9
A8
Qa0 Qa1 Qb0 Qb1
Dc0 Dc1 Dd0
DQ
*Note2
tWR
WE
*Note1
DQM0
~DQM3
Read Command Read Command
Write Command Write Command
Precharge Command
*Notes: 1. Towritedatabeforeaburstreadends,DQMi shouldbeassertedthreecyclespriortothewritecommand,
to avoid bus contention.
2. To assert row precharge before a burst write ends, wait tWR after the last write data input.
Input data during the precharge input cycle will be masked internally.
15
¡ Semiconductor
MSM54V24632A
Read & Write Cycle with Auto Precharge @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
RAS
tRRD
CAS
Ra
Ra
Rb Ca
Cb
ADDR
A9
Rb
A8
WE
CAS Latency = 1
Qa0 Qa1 Qa2 Qa3
A-Bank Precharge Start
Db0 Db1 Db2 Db3
DQ
DQM0
~DQM3
CAS Latency = 2
Qa0 Qa1 Qa2 Qa3
A-Bank Precharge Start
Db0 Db1 Db2 Db3
DQ
DQM0
~DQM3
CAS Latency = 3
DQ
Qa0 Qa1 Qa2 Qa3
A-Bank Precharge Start
Db0 Db1 Db2 Db3
tWR
DQM0
~DQM3
Row Active
(A-Bank)
A Bank Read with
Auto Precharge
B Bank Write with
Auto Precharge
B Bank Precharge
Start Point
Row Active
(B-Bank)
15
MSM54V24632A
¡ Semiconductor
Bank Interleave Random Row Read Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
tRC
RAS
tRRD
CAS
RAa
CAa
RBb
CBb
RAc
CAc
ADDR
A9
RAa
RBb
RAc
A8
QAa0 QAa1 QAa2 QAa3
QBb1 QBb2 QBb3 QBb4
QAc0 QAc1 QAc2 QAc3
DQ
WE
DQM0
~DQM3
Row Active Read Command
(A-Bank) (A-Bank)
Read Command
(B-Bank)
Read Command
(A-Bank)
Row Active
(B-Bank)
Precharge Command
(B-Bank)
Precharge Command
(A-Bank)
Row Active
(A-Bank)
17
¡ Semiconductor
MSM54V24632A
Bank Interleave Random Row Write Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
RAS
CAS
RAa
CAa
RBb
CBb
RAc
CA
ADDR
A9
RAa
RBb
RAc
A8
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3
DAc0 DAc1
DQ
WE
DQM0
~DQM3
Row Active
(A-Bank)
Row Active
(B-Bank)
Precharge
Command
(A-Bank)
Write Command
(A-Bank)
Write Command
(A-Bank)
Write Command
(B-Bank)
Row Active
(A-Bank)
Precharge Command
(A-Bank)
Precharge Command
(B-Bank)
17
MSM54V24632A
¡ Semiconductor
Bank Interleave Page Read Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
*Note1
RAS
CAS
RAa
CAa
RBb
CBb
CAc
CBd
CAe
ADDR
A9
RAa
RAa
A8
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
DQ
lROH
WE
DQM0
~DQM3
Row Active
(A-Bank)
Row Active
(B-Bank)
Read Command
(B-Bank)
Precharge Command
(A-Bank)
Read Command
(A-Bank)
Read Command
(B-Bank)
Read Command
(A-Bank)
Read Command
(A-Bank)
*Note:
1. CS is ignored when RAS, CAS and WE are high at the same cycle.
19
¡ Semiconductor
MSM54V24632A
Bank Interleave Page Write Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
RAS
CAS
RAa
CAa
RBb
CBb
CAc
CBd
ADDR
A9
RAa
RAb
A8
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0
DQ
WE
DQM0
~DQM3
Row Active
(A-Bank)
Row Active
(B-Bank)
Write Command
(B-Bank)
Write Command
(A-Bank)
Write Command
(B-Bank)
Write Command
(A-Bank)
Precharge Command
(Both Bank)
19
MSM54V24632A
¡ Semiconductor
Bank Interleave Random Row Read/Write Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
RAS
CAS
RAa
CAa
RBb
RBb
CBb
RAc
CAc
ADDR
A9
RAa
RAc
A8
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1 QAc2 QAc3
DQ
WE
DQM0
~DQM3
Row Active
(A-Bank)
Write Command
(B-Bank)
Read Command
(A-Bank)
Row Active
(B-Bank)
Read Command
(A-Bank)
Precharge Command
(A-Bank)
Row Active
(A-Bank)
21
¡ Semiconductor
MSM54V24632A
Bank Interleave Page Read/Write Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
RAS
CAS
CAa0
CBb0
CAc0
ADDR
A9
A8
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1 QAc2 QAc3
DQ
WE
DQM0
~DQM3
Read Command
(A-Bank)
Write Command
(B-Bank)
Read Command
(A-Bank)
21
MSM54V24632A
¡ Semiconductor
Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
*Note1
*Note1
CKE
CS
RAS
CAS
Ra
Ra
Ca
Cb
Cc
ADDR
A9
A8
Qa0 Qa1
Qa2
Qa2
Qb0 Qb1
Qb0 Qb1
Dc0
Dc2
DQ0 - 7
tOHZ
tOHZ
*Note3
*Note4
DQ8 - 15
Qa0
Qa3
Dc0 Dc1
*Note2
WE
DQM0
*Note4
DQM1
Row Active
Read
DQM
CLOCK
Suspension
Read
Command
Write
DQM
Write
DQM
Read DQM
Read
Write
CLOCK
Read DQM
Command
Command Suspension
*Notes: 1. When CKE is deactivated, the next clock cycle will be ignored.
2. When DQMs are asserted, the read data after two clock cycles will be masked.
3. When DQMs are asserted, the write data in the same clock cycle will be masked.
4. When DQM0 is set High, the input/output data of DQ0 - DQ7 will be masked.
When DQM2 is set High, the input/output data of DQ8 - DQ15 will be masked.
When DQM3 is set High, the input/output data of DQ16 - DQ23 will be masked.
When DQM4 is set High, the input/output data of DQ24 - DQ31 will be masked.
23
¡ Semiconductor
MSM54V24632A
Read Interruption by Precharge Command @ Burst Length = 8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
High
CKE
CS
RAS
CAS
Ra
Ra
Ca
ADDR
A9
A8
WE
CAS Latency = 1
*Note1
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5
DQ
DQM0
~DQM3
CAS Latency = 2
*Note2
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5
DQ
DQM0
~DQM3
CAS Latency = 3
*Note2
Qa0 Qa1 Qa2 Qa3 Qa4
DQ
DQM0
~DQM3
Row Active
Read Command
Precharge Command
*Notes: 1. When CAS latency = 1, and if row precharge is esserted before a burst read ends, then the read data will
not output after the next clock cycle of precharge command.
2. If row precharge is asserted before burst read ends when CAS latency = 2 or 3, then the read data will
not output after the second clock cycle of the precharge command.
23
MSM54V24632A
¡ Semiconductor
Power Down Mode @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
*Note2
tPDE
tSI
*Note1
tSI
tSI
CKE
CS
tREF(min.)
RAS
CAS
Ra
Ca
ADDR
A9
Ra
A8
Qa0 Qa1 Qa2
DQ
WE
DQM0
~DQM3
Row Active
Power-down Clock
Clock
Suspention
Exit
Precharge
Command
Power-down
Entry
Exit
Suspention
Entry
Read
Command
*Notes: 1. When both banks are in precharge state, and if CKE is set low, then the MSM54V24632A enters power-
down mode and maintains the mode while CKE is low.
2. To release the circuit from power-down mode, set CKE high for longer than tPDE, and the inputs will be
set within the same cycle.
25
¡ Semiconductor
MSM54V24632A
Self Refresh Cycle
0
1
2
CLK
tRCmin.
CKE
CS
tSI
tPDE
RAS
CAS
Ra
BS
Ra
ADDR
A9
A8
DQ
Hi - Z
Hi - Z
WE
DQM0
~DQM3
Self
Self
Row
Refresh
Entry
Refresh
Exit
Active
25
MSM54V24632A
¡ Semiconductor
Mode Register Set Cycle
Auto Refresh Cycle
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
High
lMRD
High
CKE
CS
tRC
RAS
CAS
key
Ra
ADDR
DQ
Hi - Z
Hi - Z
WE
DQM0
~DQM3
MRS
New Command
Auto Refresh
Auto Refresh
27
¡ Semiconductor
MSM54V24632A
FUNCTION TRUTH TABLE (Table 1) (1/2)
Current State1 CS RAS CAS WE BA ADDR
Action
Idle
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
NOP
NOP
BA
BA
BA
BA
X
X
ILLEGAL 2
ILLEGAL 2
Row Active
NOP 4
X
H
L
CA
RA
A8
X
H
H
L
L
L
H
L
Auto-Refresh or Self-Refresh 5
L
L
OP Code Mode Register write
Row Active
X
H
H
H
L
X
H
L
X
X
H
L
X
X
X
X
NOP
NOP
BA
BA
BA
BA
X
CA, A8 Read
CA, A8 Write
L
H
H
L
H
L
RA
A8
X
ILLEGAL 2
L
Precharge
ILLEGAL
L
X
X
H
L
Read
X
H
H
H
H
L
X
H
H
L
X
X
NOP (Continue Row Active after Burst ends)
NOP (Continue Row Active after Burst ends)
Reserved
X
X
BA
BA
BA
BA
BA
X
X
H
L
CA, A8 Term Burst, start new Burst Read
CA, A8 Term Burst, start new Burst Write
L
H
H
L
H
L
RA
A8
X
ILLEGAL 2
L
Term Burst, execute Row Precharge
ILLEGAL
L
X
X
H
L
Write
X
H
H
H
H
L
X
H
H
L
X
X
NOP (Continue Row Active after Burst ends)
NOP (Continue Row Active after Burst ends)
Reserved (Term Burst) --> Row Active
X
X
BA
BA
BA
BA
BA
X
X
H
L
CA, A8 Term Burst, Start new Burst Read
CA, A8 Term Burst, start new Burst write
L
H
H
L
H
L
RA
A8
X
ILLEGAL 2
L
Term Burst, executo Row Precharge
ILLEGAL
L
X
X
H
L
Read with
X
H
H
H
H
L
X
H
H
L
X
X
NOP (Continue Burst to End and enter Row Precharge)
NOP (Continue Burst to End and enter Row Precharge)
ILLEGAL 2
Auto Precharge
X
X
BA
BA
X
X
H
L
CA, A8 ILLEGAL 2
ILLEGAL
RA, A8 ILLEGAL 2
L
X
H
L
X
X
X
H
L
BA
X
L
X
X
X
X
ILLEGAL
Write with
X
H
H
H
H
L
X
H
H
L
X
NOP (Continue Burst to End and enter Row Precharge)
NOP (Continue Burst to End and enter Row Precharge)
ILLEGAL 2
Auto Precharge
X
BA
BA
X
H
L
CA, A8 ILLEGAL 2
ILLEGAL
RA, A8 ILLEGAL 2
ILLEGAL
L
X
H
L
X
X
BA
X
L
X
27
MSM54V24632A
¡ Semiconductor
FUNCTION TRUTH TABLE (Table 1) (2/2)
Current State1 CS RAS CAS WE BA ADDR
Action
Precharge
Write Recovery
Row Active
Refresh
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
NOP --> Idle after tRP
NOP --> Idle after tRP
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
NOP 4
BA
BA
BA
BA
X
X
X
H
L
CA
RA
A8
X
H
H
L
L
L
X
X
H
L
ILLEGAL
X
H
H
H
L
X
H
H
L
X
X
NOP
X
X
NOP
BA
BA
BA
BA
X
X
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
ILLEGAL
X
H
L
CA
RA
A8
X
H
H
L
L
L
X
X
H
L
X
H
H
H
L
X
H
H
L
X
X
NOP --> Row Active after tRCD
NOP --> Row Active after tRCD
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
X
X
BA
BA
BA
BA
X
X
X
H
L
CA
RA
A8
X
H
H
L
L
ILLEGAL 2
L
X
X
X
X
X
X
X
H
L
ILLEGAL
X
H
H
L
X
H
L
X
X
NOP --> Idle after tRC
NOP --> Idle after tRC
ILLEGAL
X
X
X
X
H
L
X
X
ILLEGAL
L
X
X
ILLEGAL
Mode Register
Access
X
H
H
H
L
X
H
H
L
X
X
NOP
X
X
NOP
X
X
ILLEGAL
X
X
X
X
ILLEGAL
X
X
X
ILLEGAL
ABBREVIATIONS
RA = Row Address
CA = Column Address
BA = Bank Address
AP = Auto Precharge
NOP = No OPeration command
Notes:
1. All inputs will be enabled when CKE is set high for at least 1 cycle prior to the inputs.
2. Illegaltobankinspecifiedstate,butmaybelegalinsomecasesdependingonthestateofbank
selection.
3. Satisfy the timing of tCCD and tWR to prevent bus contention.
4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A8.
5. Illegal if any bank is not idle.
29
¡ Semiconductor
MSM54V24632A
FUNCTION TRUTH TABLE for CKE (Table 2)
Current State (n) CKEn-1
Self Refresh 6
CKEn CS RAS CAS WE ADDR
Action
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
x
H
H
H
H
H
L
X
H
L
L
L
L
X
X
H
L
L
L
L
X
X
H
L
L
L
L
L
L
X
X
X
X
X
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
Exit Self Refresh --> ABI
Exit Self Refresh --> ABI
ILLEGAL
X
X
X
X
X
H
L
ILLEGAL
X
X
X
X
H
H
L
ILLEGAL
X
X
X
H
H
H
L
NOP (Maintain Self Refresh)
INVALID
Power Down 6
X
H
H
H
H
H
L
Exit Power Down --> ABI
Exit Power Down --> ABI
ILLEGAL
X
X
X
X
X
H
L
ILLEGAL
ILLEGAL 7
X
X
X
X
H
H
L
X
X
X
H
H
H
L
NOP (Continue power down mode)
Refer to Table 1
Enter Power Down
Enter Power Down
ILLEGAL
All Banks Idle 7
(ABI)
H
L
L
L
L
X
L
ILLEGAL
L
H
L
ILLEGAL
L
L
H
L
Enter Self Refresh
ILLEGAL
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP
Any State Other
H
L
Refer to Operations in Table 1
Begin Clock Suspend Next Cycle
Enaole Clock of Next Cycle
Continue Clock Suspension
than Listed Above
H
L
Notes:
6. If a minimam set-up time tPDE is satisfied when CKE transitions from "L" to "H", CKE
operates asynchronously so that a command can be input in the same internal clock cycle.
7. Power-down and self refresh can be entered only when all the banks are in an idle state.
29
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