MSM54V25632A [OKI]
131,072-Word x 32-Bit x 2-Bank Synchronous Graphics RAM; 131,072字×32位× 2行同步图形RAM
| 型号： | MSM54V25632A |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 131,072-Word x 32-Bit x 2-Bank Synchronous Graphics RAM |
| 文件： | 总67页 (文件大小：850K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2L0068-19-61
This version: Jun. 1999
Previous version: Sep. 1998
¡ Semiconductor
MSM54V25632A
131,072-Word ¥ 32-Bit ¥ 2-Bank Synchronous Graphics RAM
DESCRIPTION
The MSM54V25632A is a synchronous graphics random access memory organized as 128 K words
¥ 32 bits ¥ 2 banks.
This device can operate up to 100 MHz by using synchronous interface. In addition, it has 8-column
Block Write function and Write per bit function which improves performance in graphics
systems.
FEATURES
• 131,072 words ¥ 32 bits ¥ 2 banks memory
• Single 3.3 V ±0.3 V power supply
• LVTTL compatible inputs and outputs
• All input signals are latched at rising edge of system clock
• Auto precharge and controlled precharge
• Internal pipelined operation: column address can be changed every clock cycle
• Dual internal banks controlled by A9 (Bank Address: BA)
• Independent byte operation via DQM0 to DQM3
• 8-column Block Write function
• Persistent write per bit function
• Programmable burst sequence (Sequential/Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable CAS latency (1, 2 and 3)
• Burst stop function (full-page burst)
• Power Down operation and Clock Suspend operation
• Auto refresh and self refresh capability
• 1,024 refresh cycles/16 ms
• Package:
100-pin plastic QFP
(QFP100-P-1420-0.65-BK4)
(Product : MSM54V25632A-xxAGBK4)
xx indicates speed rank.
PRODUCT FAMILY
Clock Frequency
Family
Package
MHz (Max.)
MSM54V25632A-10
MSM54V25632A-12
100
83
100-pin Plastic QFP (14 ¥ 20 mm)
1/66
¡ Semiconductor
MSM54V25632A
PIN CONFIGURATION (TOP VIEW)
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ3
DQ28
VCC
DQ27
DQ26
VSSQ
DQ25
DQ24
VCCQ
DQ15
DQ14
VSSQ
DQ13
DQ12
VCCQ
VSS
VCC
DQ11
DQ10
VSSQ
DQ9
DQ8
VCCQ
NC
2
VCC
Q
Q
3
DQ4
DQ5
4
5
VSS
Q
6
DQ6
DQ7
7
8
VCC
Q
9
DQ16
DQ17
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
Q
DQ18
DQ19
VCC
Q
VCC
VSS
DQ20
DQ21
VSS
Q
DQ22
DQ23
VCC
Q
DQM0
DQM2
WE
CAS
RAS
DQM3
DQM1
CLK
CKE
DSF
NC
CS
BA (A9)
NC
A8
100-Pin Plastic QFP
Function
Address Inputs
Function
Pin Name
Pin Name
DQ Mask Enable
Special Function Enable
Clock Enable
A0 - A9
A0 - A8
A0 - A7
A9
DQM0 - DQM3
Row Address Inputs
Column Address Inputs
Bank Address
DSF
CKE
CLK
VCC
VSS
System Clock Input
Supply Voltage
Ground
Data Inputs/Outputs
Chip Select
DQ0 - DQ31
CS
Row Address Strobe
Column Address Strobe
Write Enable
Supply Voltage for DQ
Ground for DQ
RAS
VCC
VSS
Q
Q
CAS
No Connection
WE
NC
Note:
The same power supply voltage must be provided to every V pin and V Q pin.
CC CC
The same GND voltage level must be provided to every V pin and V Q pin.
SS
SS
2/66
¡ Semiconductor
MSM54V25632A
BLOCK DIAGRAM
CLK
CKE
CS
Refresh
Counter
Timing
Generator
RAS
CAS
WE
4Mb
DSF
A0
A1
A2
Memory Cells
Bank - A
VCC
VSS
Sense Amplifiers
Column Decoders
32
DQ0 to 31
I/O Buffers
A9
4Mb
Memory Cells
Bank - B
32
DQM0 to 3
Color
Register
(32 bits)
Sense Amplifiers
Column Decoders
32
Mask
Register
(32 bits)
3/66
¡ Semiconductor
MSM54V25632A
PIN DESCRIPTION
CLK
Fetches all inputs at the "H" edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
CS
DQM0, DQM1, DQM2 and DQM3.
CKE
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Address
BA (A9)
Row address: RA0 – RA8
Column address: CA0 – CA7
Selects bank to be activated during row address latch time and selects bank for precharge and read/
write during column address latch time. A9 = "L" : Bank A, A9 = "H" : Bank B
RAS
CAS
WE
Functionality depends on the combination. For details, see the function truth table.
DSF
DSF is part of the inputs of graphics command of the MSM54V25632A.
If DSF is inactive (Low level), MSM54V25632A operates just like SDRAM.
Masks the read data of two clocks later when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal.
Masks the write data of the same clock when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal.
Data inputs/outputs are multiplexed on the same pin.
DQM0 -
DQM3
DQi
*Notes: 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE, DQM0,
DQM1, DQM2, and DQM3 are invalid.
2. When issuing an active, read or write command, the bank is selected by A9.
A9
0
Active, read or write
Bank A
1
Bank B
3. The auto precharge function is enabled or disabled by the A8 input when the read or write command is
issued.
A8
0
A9
0
Operation
After the end of burst, bank A holds the active status.
After the end of burst, bank A is precharged automatically.
After the end of burst, bank B holds the active status.
After the end of burst, bank B is precharged automatically.
1
0
0
1
1
1
4. When issuing a precharge command, the bank to be precharged is selected by the A8 and A9 inputs.
A8
0
A9
0
Operation
Bank A is precharged.
0
1
Bank B is precharged.
1
X
Both banks A and B are precharged.
4/66
¡ Semiconductor
MSM54V25632A
COMMAND OPERATION
Mode Register Set Command (CS, RAS, CAS, WE, DSF = "Low")
The MSM54V25632A has the mode register that defines the operation mode "CAS Latency,
Burst Length, Burst Sequence". The mode register is composed of ten bits of memories
corresponding to address inputs A0 - A8 and BA. The Mode Register Set command should be
executed just after the MSM54V25632A is powered on. Before entering this command, all banks
must be precharged. Next command can be issued after t
.
RSC
Special Mode Register Set Command (CS, RAS, CAS, WE = "Low", DSF = "High")
The MSM54V25632A has the 32-bit color register for block write operation and the 32-bit mask
register for write per bit operation. The Special Mode Register Set command performs loading
mask register or color register. When A5 is "high", The mask data presented on the DQ0 - DQ31
islatchedintothemaskregister. WhenA6is"high", ThecolordatapresentedontheDQ0-DQ31
is latched into the color register. The Special Mode Register Set command must be executed
before Masked Block Write and Write Per Bit operations. Next command can be issued after
t
.
RSC
Auto Refresh Command (CS, RAS, CAS, DSF = "Low", WE, CKE = "High")
TheAutoRefreshcommandperformsrefreshautomaticallybytheaddresscounter. Therefresh
operationmustbeperformed1024timeswithin16msandthenextcommandcanbeissuedafter
t
from last Auto Refresh command. Before entering this command, all banks must be
RC
precharged.
Self Refresh Entry/Exit Command (CS, RAS, CAS, DSF, CKE = "Low", WE = "High")
The self refresh operation continues after the Self Refresh Entry command is entered, with CKE
level left "low". This operation terminates by making CKE level "high". The self refresh
operation is performed automatically by the internal address counter on the MSM54V25632A
chip. In self refresh mode, no external refresh control is required. Before entering self refresh
mode, all banks must be precharged. Next command can be issued after t
.
RC
Single Bank Precharge Command (CS, RAS, WE, DSF, A8 = "Low", CAS = "High")
The Single Bank Precharge command triggers bank precharge operation. Precharge bank is
selected by BA.
All Banks Precharge Command (CS, RAS, WE, DSF = "Low", CAS, A8 = "High")
The All Bank Precharge command triggers precharge of both bank A and bank B.
5/66
¡ Semiconductor
MSM54V25632A
Bank Active and Masked Write Disable Command (CS, RAS, DSF = "Low", CAS, WE =
"High")
The Bank Active command activates the bank selected by BA. The Bank Active command
corresponds to conventional DRAM's RAS falling operation. Row addresses "A0 - A8 and BA"
are strobed. After this command, the write command and block write command for that bank
works as the no write per bit operation.
Bank Active and Masked Write Enable Command (CS, RAS = "Low", CAS, WE, DSF =
"High")
The Bank Active command activates the bank selected by BA. The Bank Active command
corresponds to conventional DRAM's RAS falling operation. Row addresses "A0 - A8 and BA"
are strobed. After this command, the write command and block write command for that bank
works as the write per bit operation.
Write Command (CS, CAS, WE, DSF, A8 = "Low", RAS = "High")
The Write command is required to begin burst write operation. Then burst access initial bit
column address is strobed.
Write with Auto Precharge Command (CS, CAS, WE, DSF = "Low", RAS, A8 = "High")
The Write with Auto Precharge command is required to begin burst write operation with
automatic precharge after the burst write. Any command that interrupts this operation cannot
be issued.
Masked Block Write Command (CS, CAS, WE, A8 = "Low", RAS, DSF = "High")
The Masked Block Write command is required to begin block write operation with column
mask. The masked block write operation performs writing in the 8 memory cells selected by
column addresses "A3 - A7". In this operation, data in color register is written to memory cells
with the column mask functions. At the same time, this command can perform write per bit
operation. The block write operation is not bursted.
6/66
¡ Semiconductor
MSM54V25632A
Block Write Function
Color Register
I/O Mask
11001110
11111010
10010011
Column Mask
8 Column ¥ 8 DQ
Column 7
Column 6
Column 5
Column 4
Column 3
Column 2
Column 1
Column 0
1
1
*
*
1
*
*
1
1
1
*
*
1
*
*
1
0
0
*
*
0
*
*
0
0
0
*
*
0
*
*
0
1
1
*
*
1
*
*
1
*
*
*
*
*
*
*
*
1
1
*
*
1
*
*
1
*
*
*
*
*
*
*
*
Note : Location "*" can not be loaded.
Remark: 1. This diagram shows only for DQ0 - 7. The other DQ is similar as this.
Column Mask
DQ0 - 7 : Column Mask for DQ0 - 7
DQ8 - 15 : Column Mask for DQ8 - 15
DQ16 - 23: Column Mask for DQ16 - 23
DQ24 - 31: Column Mask for DQ24 - 31
Write per Bit
Mask data = Mask Register + DQMi
DQMi is prior to data of Mask Register.
7/66
¡ Semiconductor
MSM54V25632A
Masked Block Write with Auto Precharge Command (CS, CAS, WE = "Low", RAS, DSF,
A8 = "High")
The Masked Block Write with Auto Precharge command performs precharging at the bank
selected by BA automatically after Masked Block Write.
Read Command (CS, CAS, DSF, A8 = "Low", RAS, WE = "High")
The Read command is required to begin burst read operation. Then burst access initial bit
column address is strobed.
Read with Auto Prechaege Command (CS, CAS, DSF = "Low", RAS, WE, A8 = "High")
The Read with Auto Precharge command is required to begin burst read operation with auto
precharge after the burst read. Any command that interrupts this operation cannot be issued.
No Operation Command (CS, DSF = "Low", RAS, CAS, WE = "High")
The No Operation command does not trigger any operation.
Device Deselect Command (CS = "High")
The Device Deselect command disables the RAS, CAS, WE, DSF and Address input. This
command does not trigger any operation.
Data Write/Output Enable Command (DQMi = "Low")
The Data Write/Output Enable command enables DQ0 - DQ31 in read or write.
The each DQM0, 1, 2 and 3 corresponds to DQ0 - DQ7, DQ8 - DQ15, DQ16 - DQ23 and DQ24
- DQ31 respectively.
Data Mask/Output Disable Command (DQMi = "High")
The Data Mask/Output Disable command disables DQ0 - DQ31. In read cycle output buffers
are disabled after 2 clocks . In write cycle input buffers are disabled at the same clock. The each
DQM0, 1, 2 and 3 corresponds to DQ0 - DQ7, DQ8 - DQ15, DQ16 - DQ23 and DQ24 - DQ31
respectively.
Burst Stop Command (CS, WE, DSF = "Low", RAS, CAS = "High")
The Burst Stop command stops burst access when the access is in full page. After the Burst Stop
command is entered, the output buffer goes into high impedance state.
8/66
¡ Semiconductor
MSM54V25632A
TRUTH TABLE
Command Truth Table
Function
Address
CS
RAS
CAS
WE
DSF
A9
¥
A8
¥
A7 - A0
¥
Device Deselect
H
L
L
L
L
L
L
L
L
¥
H
H
H
H
H
H
H
H
¥
H
H
L
L
L
L
L
L
¥
H
L
H
H
L
L
L
L
¥
L
L
L
L
L
L
H
H
No Operation
¥
¥
¥
Burst Stop in Full Page
Read
¥
¥
¥
BA
BA
BA
BA
BA
BA
L
CA
CA
CA
CA
CA
CA
Read with Auto Precharge
Write
H
L
Write with Auto Precharge
Masked Block Write
Masked Block Write with Auto
Precharge
H
L
H
Bank Activate
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
L
L
L
L
L
H
L
L
L
H
BA
RA
RA
L
Bank Activate with WPB Enable
Precharge Select Bank
Precharge All Banks
Mode Register Set
Special Register Set
BA
BA
¥
¥
¥
H
OP. CODE
OP. CODE
L
DQM Truth Table
Function
DQMi
Data Write/Output Enable
Data Mask/Output Disable
L
H
9/66
¡ Semiconductor
MSM54V25632A
Function Truth Table (1/5)
Note 1
Current State CS RAS CAS WE DSF Address
Action
Note
Idle
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
¥
H
H
H
H
H
H
H
L
¥
¥
¥
¥NOP or Power Down
NOP or Power Down
ILLEGAL
H
H
H
L
H
L
¥
¥
H
L
¥
¥
¥
2
2
L
ILLEGAL
H
H
L
H
L
ILLEGAL
L
BA, CA, A8 ILLEGAL
BA, CA, A8 ILLEGAL
BA, CA, A8 ILLEGAL
2
2
2
L
H
L
L
L
H
H
H
H
L
H
H
L
H
L
BA, RA
Row Active with WPB
L
BA, RA
Row Active
ILLEGAL
NOP
L
H
L
¥
L
L
BA, A8
3
4
L
H
H
L
H
L
¥
¥
ILLEGAL
L
L
Auto Refresh/Self refresh
L
L
H
L
Op-Code Special Register Write
Op-Code Mode Register Write
L
L
L
Row Active
(ACT)
¥
H
H
H
H
H
H
H
L
¥
¥
¥
H
L
¥
¥NOP
H
H
H
L
H
L
¥
NOP
¥
¥
¥
ILLEGAL
ILLEGAL
ILLEGAL
L
2
H
H
L
H
L
L
BA, CA, A8 Read
L
H
L
BA, CA, A8 Block Write
BA, CA, A8 Write
L
L
H
H
H
H
L
H
H
L
H
L
BA, RA
ILLEGAL
ILLEGAL
ILLEGAL
Precharge
ILLEGAL
ILLEGAL
2
2
L
BA, RA
L
H
L
¥
L
L
BA, A8
L
H
H
L
H
L
¥
¥
L
L
L
L
H
L
Op-Code Special Register Write
Op-Code ILLEGAL
L
L
L
10/66
¡ Semiconductor
MSM54V25632A
Function Truth Table (2/5)
Note 1
Current State CS RAS CAS WE DSF Address
Action
Note
Read
(RD)
H
L
L
L
¥
H
H
H
¥
H
H
H
¥
H
L
L
¥
¥
H
L
¥
¥
¥
¥
NOP (Continue Row Active after Burst ends)
NOP (Continue Row Active after Burst ends)
ILLEGAL
1, 2, 4, 8 Burst Length; ILLEGAL
Full Page Burst; Burst Stop Æ Bank Active
ILLEGAL
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
H
H
H
L
L
L
H
H
L
H
L
¥
BA, CA, A8 Term Burst, new Read
BA, CA, A8 Term Burst, start Block Write
BA, CA, A8 Term Burst, start Write
L
H
L
L
L
H
H
H
H
L
H
H
L
H
L
BA, RA
ILLEGAL
2
2
L
BA, RA
ILLEGAL
L
H
L
¥
ILLEGAL
L
L
BA, A8
Term Burst, execute Row Precharge
L
H
H
L
H
L
¥
¥
ILLEGAL
ILLEGAL
L
L
L
L
H
L
Op-Code ILLEGAL
Op-Code ILLEGAL
L
L
L
Write/Block Write
(WT/BW)
¥
H
H
H
¥
H
H
H
¥
H
L
¥
¥
H
L
¥
¥
¥
¥
NOP (Continue Row Active after Burst ends)
NOP (Continue Row Active after Burst ends)
ILLEGAL
L
1, 2, 4, 8 Burst Length; ILLEGAL
Full Page Burst; Burst Stop Æ Row Active
ILLEGAL
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
L
H
L
¥
BA, CA, A8 Term Burst, start Read
BA, CA, A8 Term Burst, new Block Write
BA, CA, A8 Term Burst, new Write
H
L
L
H
H
L
H
L
BA, RA
ILLEGAL
2
2
BA, RA
ILLEGAL
H
L
¥
ILLEGAL
L
BA, A8
Term Burst, execute Row Precharge
H
H
L
H
L
¥
¥
ILLEGAL
ILLEGAL
H
L
Op-Code ILLEGAL
Op-Code ILLEGAL
L
11/66
¡ Semiconductor
MSM54V25632A
Function Truth Table (3/5)
Note 1
Current State CS RAS CAS WE DSF Address
Action
Note
Read with Auto
Precharge
(RAP)
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
¥
H
H
H
H
H
H
H
L
¥
H
H
H
L
¥
H
L
¥
¥
H
L
¥
¥
¥
¥
¥
NOP (Continue Burst to End and enter Row Precharge)
NOP (Continue Burst to End and enter Row Precharge)
ILLEGAL
ILLEGAL
ILLEGAL
L
H
H
L
H
L
L
BA, CA, A8 ILLEGAL
BA, CA, A8 ILLEGAL
BA, CA, A8 ILLEGAL
L
H
L
L
L
H
H
H
H
L
H
H
L
H
L
BA, RA
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
2
2
L
BA, RA
L
H
L
¥
L
L
BA, A8
2
L
H
H
L
H
L
¥
¥
L
L
L
L
H
L
Op- Code ILLEGAL
Op- Code ILLEGAL
L
L
L
Write/Block
Write with Auto
Precharge
¥
H
H
H
H
H
H
H
L
¥
H
H
H
L
¥
H
L
¥
¥
H
L
¥
¥
¥
¥
¥
NOP (Continue Burst to End and enter Row Precharge)
NOP (Continue Burst to End and enter Row Precharge)
ILLEGAL
ILLEGAL
ILLEGAL
(WAP/BWAP)
L
H
H
L
H
L
L
BA, CA, A8 ILLEGAL
BA, CA, A8 ILLEGAL
BA, CA, A8 ILLEGAL
L
H
L
L
L
H
H
H
H
L
H
H
L
H
L
BA, RA
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
2
2
L
BA, RA
L
H
L
¥
L
L
BA, A8
2
L
H
H
L
H
L
¥
¥
L
L
L
L
H
L
Op- Code ILLEGAL
Op- Code ILLEGAL
L
L
L
12/66
¡ Semiconductor
MSM54V25632A
Function Truth Table (4/5)
Note 1
Current State CS RAS CAS WE DSF Address
Action
Note
Precharging
(PRE)
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
¥
H
H
H
H
H
H
H
L
¥
¥
¥
¥NOP Æ Idle after tRP
NOP Æ Idle after tRP
ILLEGAL
H
H
H
L
H
L
¥
¥
H
L
¥
¥
¥
L
ILLEGAL
2
H
H
L
H
L
ILLEGAL
L
BA, CA, A8 ILLEGAL
BA, CA, A8 ILLEGAL
BA, CA, A8 ILLEGAL
2
2
2
2
2
L
H
L
L
L
H
H
H
H
L
H
H
L
H
L
BA, RA
ILLEGAL
L
BA, RA
ILLEGAL
L
H
L
¥
ILLEGAL
L
L
BA, A8
NOP Æ Idle after tRP
ILLEGAL
3
L
H
H
L
H
L
¥
¥
L
L
ILLEGAL
L
L
H
L
Op-Code Special Register Write
Op-Code ILLEGAL
L
L
L
Refreshing
(REF)
¥
H
H
H
H
H
H
H
L
¥
¥
¥
H
L
¥
¥
NOP Æ Idle after tRC
H
H
H
L
H
L
¥
NOP Æ Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
¥
¥
¥
L
H
H
L
H
L
L
BA, CA, A8
BA, CA, A8
BA, CA, A8
BA, RA
BA, RA
¥
L
H
L
L
L
H
H
H
H
L
H
H
L
H
L
L
L
H
L
L
L
BA, A8
¥
L
H
H
L
H
L
L
L
¥
L
L
H
L
Op-Code
Op-Code
L
L
L
13/66
¡ Semiconductor
MSM54V25632A
Function Truth Table (5/5)
Note 1
Current State CS RAS CAS WE DSF Address
Action
Note
Mode Register
Access
(MRA)
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
¥
H
H
H
H
H
H
H
L
¥
H
H
H
L
¥
H
L
¥
¥
H
L
¥
¥
¥
¥
¥
NOP
NOP
ILLEGAL
ILLEGAL
ILLEGAL
L
H
H
L
H
L
L
BA, CA, A8 ILLEGAL
BA, CA, A8 ILLEGAL
BA, CA, A8 ILLEGAL
L
H
L
L
L
H
H
H
H
L
H
H
L
H
L
BA, RA
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
L
BA, RA
L
H
L
¥
L
L
BA, A8
L
H
H
L
H
L
¥
¥
L
L
L
L
H
L
Op-Code ILLEGAL
Op-Code ILLEGAL
L
L
L
Special Mode
Register
Access
¥
H
H
H
H
H
H
H
L
¥
H
H
H
L
¥
H
L
¥
¥
H
L
¥
¥
¥
¥
¥
NOP
NOP
ILLEGAL
ILLEGAL
ILLEGAL
(SMRA)
L
H
H
L
H
L
L
BA, CA, A8 ILLEGAL
BA, CA, A8 ILLEGAL
BA, CA, A8 ILLEGAL
L
H
L
L
L
H
H
H
H
L
H
H
L
H
L
BA, RA
BA, RA
¥
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
L
L
H
L
L
L
BA, A8
¥
L
H
H
L
H
L
L
L
¥
L
L
H
L
Op-Code
Op-Code
L
L
L
ABBREVIATIONS
RA = Row Address
CA = Column Address
BA = Bank Address
AP = Auto Precharge
NOP = No OPeration command
¥ = High or Low level (Don't care)
Notes:
1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs.
2. Illegaltobankinspecifiedstate,butmaybelegalinsomecasesdependingonthestateofbank
selection.
3. NOP to bank precharging or in idle state. Precharges activated bank by BA or A8.
4. Illegal if any bank is not idle.
14/66
¡ Semiconductor
MSM54V25632A
Function Truth Table for CKE
Current State (n) CKEn-1 CKEn CS RAS CAS WE DSF Address
Action
Note
Self Refresh
(SREF)
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
¥
H
H
H
H
H
L
¥
H
L
L
L
L
¥
¥
H
L
L
L
L
¥
¥
H
L
L
L
L
L
L
¥
¥
¥
¥
¥
¥
¥
H
H
H
L
¥
¥
H
H
L
¥
¥
H
L
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
L
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
INVALID
5
Exit Self Refresh Æ ABI
Exit Self Refresh Æ ABI
ILLEGAL
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
¥
¥
¥
¥
¥
H
L
ILLEGAL
¥
¥
¥
¥
H
H
L
ILLEGAL
¥
¥
¥
H
H
H
L
NOP (Maintain Self Refresh)
INVALID
Power Down
(PD)
¥
H
H
H
H
H
L
Exit Power Down Æ ABI
Exit Power Down Æ ABI
ILLEGAL
¥
¥
¥
¥
¥
H
L
ILLEGAL
¥
¥
¥
¥
H
H
L
ILLEGAL
¥
¥
¥
H
H
H
L
NOP (Continue power down mode)
Refer to Table
All Banks Idle
(ABI)
H
L
Enter Power Down
Enter Power Down
ILLEGAL
L
L
L
¥
L
ILLEGAL
L
H
L
ILLEGAL
L
L
H
L
Enter Self Refresh
ILLEGAL
L
L
L
L
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
NOP
Any State Other
H
L
Refer to Operations in Table
Begin Clock Suspend Next Cycle
Enable Clock of Next Cycle
Continue Clock Suspension
than Listed Above
H
L
Notes:
5. If the minimum set-up time tPDE is satisfied when CKE transitions from "L" to "H", CKE
operates asynchronously so that a command can be input in the same internal clock cycle.
6. Power-down and self refresh can be entered only when all the banks are in an idle state.
15/66
¡ Semiconductor
MSM54V25632A
Mode Set Address Keys
Operation Code
CAS Latency (CL)
A6 A5 A4 CL
Burst Type (BT)
Burst Length (BL)
A2 A1 A0 BT = 0
A8 A7
TM
A3
0
BT
BT = 1
0
0
1
1
0
1
0
1
Mode Setting
Reserved
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
1
Sequential
Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
2
4
8
1
2
4
8
2
3
Reserved
Reserved
Reserved
Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Write Burst Length
Length
A9
0
Burst
1
Single Bit
Special Mode Set Address Keys
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
LC LM
0
0
0
0
0
0
0
0
Load Color (LC)
Load Mask (LM)
A6
Function
Disable
Enable
A5
Function
Disable
Enable
0
1
0
1
Note :
If LC and LM are both high (1), data of Mask and Color register will be unknown.
POWER ON SEQUENCE
1. With CKE = "H", DQM = "H" and the other inputs in NOP state, turn on the power
supply and start the system clock.
2. After the V voltage has reached the specified level, pause for 200 ms or more with
CC
the input kept in NOP state.
3. Issue the precharge all bank command.
4. Apply an Auto-refresh eight or more times.
5. Enter the mode register setting command.
16/66
¡ Semiconductor
MSM54V25632A
Burst Length and Sequence
BL = 2
Starting Address
Sequential Type
Interleave Type
(column address A0, binary)
0
1
0, 1
1, 0
Not supported
Not supported
BL = 4
Starting Address
Sequential Type
Interleave Type
(column address A1 - A0, binary)
00
01
10
11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
BL = 8
Starting Address
Sequential Type
Interleave Type
(column address A2 - A0, binary)
000
001
010
011
100
101
110
111
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4 ,5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
BL = Full : Sequential only
17/66
¡ Semiconductor
MSM54V25632A
PRECHARGE
Read Interrupted by Precharge
CL = 1
CL = 2 or 3
: At the same clock as the last read data.
: One clock earlier than the last read data.
BL = 4
0
1
2
3
4
5
6
7
8
CLK
CL = 1
RD
RD
RD
PRE
Q4
Hi-Z
Hi-Z
DQ
Q1
Q2
Q1
Q3
Q2
Q1
CL = 2
PRE
Q3
DQ
Q4
PRE
Q3
CL = 3
Hi-Z
DQ
Q2
Q4
(tRAS is satisfied)
18/66
¡ Semiconductor
MSM54V25632A
AUTO PRECHARGE
Read with Auto Precharge
BL = 4
7 8
0
1
2
3
4
5
6
CLK
CL = 1
RAP
RAP
RAP
Auto precharge starts
Q3 Q4
Auto precharge starts
Hi-Z
Hi-Z
DQ
Q1
Q2
Q1
CL = 2
DQ
Q2
Q3
Q4
CL = 3
Auto precharge starts
Hi-Z
DQ
Q1
Q2
Q3
Q4
(tRAS is satisfied)
19/66
¡ Semiconductor
MSM54V25632A
Write with Auto Precharge
BL = 4
0
1
2
3
4
5
6
7
8
CLK
CL = 1
WAP
D1
Auto precharge starts
Hi-Z
DQ
D2
D2
D2
D3
D3
D3
D4
CL = 2
WAP
D1
Auto precharge starts
Hi-Z
DQ
D4
D4
CL = 3
WAP
D1
Auto precharge starts
Hi-Z
DQ
(tRAS is satisfied)
Block Write with Auto Precharge
0
1
2
3
4
5
CLK
tBWC
CL = 1
BWAP Auto precharge starts
Hi-Z
DQ
DB
CL = 2
BWAP
DB
Auto precharge starts
Hi-Z
DQ
CL = 3
BWAP
DB
Auto precharge starts
Hi-Z
DQ
(tRAS is satisfied)
20/66
¡ Semiconductor
MSM54V25632A
READ/WRITE COMMAND INTERVAL
Read to Read Command Interval
BL = 4, CL = 2
0
1
2
3
4
5
6
7
8
CLK
DQ
RD-A RD-B
Hi-Z
QA1 QB1 QB2 QB3 QB4
1 cycle
Write to Write Command Interval
BL = 4, CL = 2
0
1
2
3
4
5
6
7
8
CLK
DQ
WT-A WT-B
Hi-Z
DA1 DB1 DB2 DB3 DB4
1 cycle
21/66
¡ Semiconductor
MSM54V25632A
Write to Read Command Interval
BL = 4
0
1
2
3
4
5
6
7
8
CLK
CL = 1
WT-A RD-B
Hi-Z
DA1
DQ
QB1 QB2 QB3 QB4
1 cycle
CL = 2
WT-A RD-B
Hi-Z
DQ
DA1
QB1 QB2 QB3 QB4
CL = 3
WT-A RD-B
Hi-Z
DQ
DA1
QB1 QB2 QB3 QB4
22/66
¡ Semiconductor
MSM54V25632A
Block Write to Write/Block Write Command Interval
0
1
2
3
4
5
6
7
8
CLK
DQ
tBWC
BW-A
DA
BW-B
DB
CL = 2
Hi-Z
tBWC
BW-A
DA
WT-B
BL = 4, CL = 2
DQ
DB1 DB2 DB3 DB4
Block Write to Read Command Interval
0
1
2
3
4
5
6
7
8
CLK
tBWC
tBWC
tBWC
CL = 1
BW-A
DA
RD-B
Hi-Z
DQ
QB1 QB2 QB3 QB4
CL = 2
BW-A
DA
RD-B
Hi-Z
DQ
QB1 QB2 QB3 QB4
CL = 3
BW-A
DA
RD-B
Hi-Z
DQ
QB1 QB2 QB3 QB4
23/66
¡ Semiconductor
MSM54V25632A
Read to Write/Block Write Command Interval
CL = 1, 2, 3
0
1
2
3
4
5
6
7
8
CLK
RD-A WT-B
DQM
DQ
Hi-Z
DB1 DB2 DB3 DB4
1 cycle
BL = 8, CL = 1, 2
0
1
2
3
4
5
6
7
8
9
CLK
CL = 1
RD-A
WT-B
DQM
DQ
QA1 QA2 QA3 QA4
DB1 DB2 DB3
necessary
Hi-Z is
CL = 2
RD-A
WT-B
DQM
DQ
QA1 QA2 QA3
DB1 DB2 DB3
Hi-Z is
necessary
24/66
¡ Semiconductor
MSM54V25632A
ex.) CL = 3, BL = 4
0
1
2
3
4
5
6
7
8
CLK
RD-A
WT-B
DQM
DQ
QA1
DB1 DB2 DB3
necessary
Hi-Z is
ex.) CL = 1, BL = 4
0
1
2
3
4
5
6
7
8
9
CLK
WT-A
RD-B
DQM
DQ
Hi-Z
DA1 DA2 DA3
QB2 QB3 QB4
Note
Note : DQM can mask both data-in and data-out in this special case.
25/66
¡ Semiconductor
MSM54V25632A
BURST TERMINATION
Burst Stop Command in Full Page
BL = Full Page, CL = 1, 2, 3
0
1
2
3
4
5
6
7
8
CLK
RD
BST
Q3
CL = 1
Hi-Z
Q1
Q2
Q1
DQ
CL = 2
Hi-Z
Q2
Q3
Q2
DQ
Hi-Z
CL = 3
Q1
Q3
DQ
BL = Full Page, CL = 1, 2, 3
0
1
2
3
4
5
6
7
8
CLK
WT
BST
CL = 1, 2, 3
Hi-Z
D1
DQ
D2
D3
D4
26/66
¡ Semiconductor
MSM54V25632A
Precharge Termination in READ Cycle
BL = X, CL = 1
0
1
2
3
4
5
6
7
8
CLK
DQ
RD
PRE
Q4
ACT
Hi-Z
Q1
Q2
Q3
tRP
BL = X, CL = 2
0
1
2
3
4
5
6
7
8
CLK
DQ
RD
PRE
Q3
ACT
Hi-Z
Q1
Q2
Q4
tRP
BL = X, CL = 3
0
1
2
3
4
5
6
7
8
CLK
DQ
RD
PRE
Q2
ACT
Hi-Z
Q1
Q3
tRP
27/66
¡ Semiconductor
MSM54V25632A
Precharge Termination in WRITE Cycle
BL = X, CL = 1, 2
0
1
2
3
4
5
6
7
8
CLK
DQ
WT
D1
PRE
D5
ACT
Hi-Z
D2
D3
D4
tRP
Note : D5 data will not be written
BL = X, CL = 3
0
1
2
3
4
5
6
7
8
CLK
DQ
WT
D1
PRE
D5
ACT
Hi-Z
tRP
D2
D3
D4
Note : D5 data will not be written
28/66
¡ Semiconductor
MSM54V25632A
ELECTRICAL CHARACTERISTICS
Note : All voltages are referenced to V .
SS
Absolute Maximum Ratings
Parameter
Voltage on Power Supply Pin
Relative to GND
Symbol
Condition
Rating
Unit
V
CC, VCC
Q
—
–1.0 to 4.6
V
Voltage on Input Pin Relative to GND
Short Circuit Output Current
Power Dissipation
VT
IOS
PD
—
—
–1.0 to VCC + 0.5 £ 4.6
V
mA
W
50
1
Ta = 25°C
—
Operating Temperature
Storage Temperature
Topr
Tstg
0 to 70
–55 to 150
°C
°C
—
Caution:
Exposing the device to stress above those listed in Absolute Maximum Ratings could
causepermanentdamage. Thedeviceisnotmeanttobeoperatedunderconditions
outside the limits described in the operational section of this specification. Exposure to
Absolute Maximum Rating conditions for extended periods may affect devicereliability.
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Power Supply Voltage
Input High Voltage
Symbol
VCC
Min.
3.0
Typ.
3.3
—
Max.
Unit
3.6
CC + 0.3
0.8
V
V
V
VIH
2.0
V
Input Low Voltage
VIL
–0.3
—
Capacitance
(VCC = 3.3 V 0.3 V, Ta = 25°C, f = 1 MHꢀ)
Parameter
Input Capacitance (A0 - A9)
Input Capacitance
Symbol
Min.
Max.
Unit
CI1
—
6
pF
CI2
—
6
7
pF
pF
(CLK, CKE, CS, RAS, CAS, WE, DSF, DQM)
Input/Output Capacitance
(DQ0 - DQ31)
CI/O
—
DC Characteristics 1
Parameter
Output High Voltage
Output Low Voltage
Symbol
VOH IOH = –2 mA
VOL IOL = 2 mA
0 V £ VI £ 3.6 V;
Test Condition
Min.
2.4
Max.
—
Unit
V
—
0.4
V
Input Leakage Current
Output Leakage Current
ILI
–10
–10
10
10
mA
mA
All other pins not under test = 0 V
ILO
DOUT is disabled, 0 V £ VO £ 3.6 V
29/66
¡ Semiconductor
MSM54V25632A
DC Characteristics 2
-10
-12
Parameter
Symbol
Test Condition
Unit Note
Max.
Max.
Burst length = 1, tRAS ≥ tRAS (MIN.)
,
Operating Current
ICC1
175
155
mA
mA
1
tRP ≥ tRP (MIN.), IO = 0 mA
Precharge Standby Current ICC2P CKE £ VIL (MAX.), tCK = 15 ns
4
3
4
3
in Power Down Mode
ICC2PS CKE £ VIL (MAX.), tCK = •
CKE ≥ VIH (MIN.), tCK = 15 ns,
ICC2N CS ≥ VIH (MIN.)
,
60
60
Precharge Standby Current
in Non Power Down Mode
Input signals are changed one time during 30 ns.
CKE ≥ VIH (MIN.), tCK = •,
mA
mA
mA
I
CC2NS
30
30
Input signals are stable.
Active Standby Current ICC3P CKE £ VIL (MAX.), tCK = 15 ns
in Power Down Mode ICC3PS CKE £ VIL (MAX.), tCK = •
CKE ≥ VIH (MIN.), tCK = 15 ns,
4
3
4
3
ICC3N CS ≥ VIH (MIN.)
,
70
70
Active Standby Current
Input signals are changed one time during 30 ns.
CKE ≥ VIH (MIN.), tCK = •,
in Non Power Down Mode
I
CC3NS
35
35
Input signals are stable.
CAS Latency = 1
130
180
240
165
3
120
170
230
145
3
Operating Current
(Burst Mode)
tCK ≥ tCK (MIN.),
ICC4
CAS Latency = 2
CAS Latency = 3
mA
2
3
IO = 0 mA
Refresh Current
ICC5 tRC ≥ tRC (MIN.)
ICC6 CKE £ 0.2 V
mA
mA
Self Refresh Current
Operating Current
(Block Write Mode)
tCK ≥ tCK (MIN.), IO = 0 mA,
ICC7
240
240
mA
CAS cycle = 20 ns
Notes 1.
I
dependsonoutputloadingandcyclerates.Specifiedvaluesareobtainedwiththe
CC1
output open. In addition to this, I
is measured on condition that addresses are
CC1
changed only one time during t
.
CK (MIN.)
2.
3.
I
dependsonoutputloadingandcyclerates.Specifiedvaluesareobtainedwiththe
CC4
output open. In addition to this, I
is measured on condition that addresses are
CC4
changed only one time during t
.
CK (MIN.)
I
ismeasuredonconditionthataddressesarechangedonlyonetimeduringt
CC5
CK
.
(MIN.)
30/66
¡ Semiconductor
MSM54V25632A
AC Characteristics
Test conditions
• AC measurements assume t = 1 ns.
T
• Reference level for measuring timing of input signals is 1.4 V. Transition times are measured
between V and V .
IH
IL
• If t is longer than 1 ns, reference level for measuring timing of input signals is V
and V
T
IH (MIN.)
IL
.
(MAX)
• An access time is measured at 1.4 V.
tCK
tCH
tCL
2.8 V
CLK 1.4 V
VSS
tSetup tHold
2.8 V
Input 1.4 V
VSS
tAC
tOH
1.4 V
Output
1.4 V
31/66
¡ Semiconductor
MSM54V25632A
Synchronous Characteristics
MSM54V25632A
-10
MSM54V25632A
-12
Parameter
Symbol
Unit Note
Min.
10
15
30
—
—
—
3.5
3.5
3
Max.
Min.
12
18
36
—
—
—
4
Max.
CAS Latency = 3 tCK3
CAS Latency = 2 tCK2
CAS Latency = 1 tCK1
CAS Latency = 3 tAC3
(100 MHꢀ)
(83 MHꢀ)
ns
ns
ns
Clock Cycle Time
(66 MHꢀ)
(55 MHꢀ)
(33 MHꢀ)
9
(28 MHꢀ)
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
Access Time from CLK CAS Latency = 2 tAC2
CAS Latency = 1 tAC1
13
27
—
—
—
—
8
15
32
CLK High Level Width
CLK Low Level Width
Data-out Hold Time
tCH
tCL
tOH
tLZ
—
4
—
3
—
Data-out Low-impedance Time
0
0
—
CAS Latency = 3 tHZ3
3
3
8
Data-out
CAS Latency = 2 tHZ2
3
12
26
—
—
—
—
—
—
3
12
High-impedance Time
CAS Latency = 1 tHZ1
3
3
26
Data-in Setup Time
Data-in Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
tDS
tDH
3
3.5
1.5
3.5
1.5
3.5
1.5
—
1
—
tAS
3
—
tAH
1
—
tCKS
tCKH
3
—
CKE Hold Time
1
—
Command (CS, RAS, CAS, WE, DSF,
DQM) Setup Time
tCMS
tCMH
3
1
—
—
3.5
1.5
—
—
ns
ns
Command (CS, RAS, CAS, WE, DSF,
DQM) Hold Time
Note 1. Output load.
1.4 V
50 W
Z = 50 W
Output
30 pF
32/66
¡ Semiconductor
MSM54V25632A
Asynchronous Characteristics
MSM54V25632A
-10
MSM54V25632A
-12
Parameter
Symbol
Unit Note
Min.
90
60
30
30
20
20
20
20
5
Max.
—
Min.
108
72
36
36
24
24
24
24
5
Max.
—
REF to REF/ACT Command Period
ACT to PRE Command Period
PRE to ACT Command Period
tRC
tRAS
tRP
ns
ns
120,000
—
120,000
—
ns
Delay Time ACT to READ/WRITE Command tRCD
ACT (0) to ACT (1) Command Period tRRD
—
—
ns
—
—
ns
CAS Latency = 3 tDPL3
CAS Latency = 2 tDPL2
CAS Latency = 1 tDPL1
—
—
ns
Data-in to PRE
—
—
ns
Command Period
—
—
ns
Data-in to ACT (REF) CAS Latency = 3 tDAL3
—
—
CLK
CLK
CLK
ns
Command Period
(Auto Precharge)
Block Write Cycle Time
Block Write Data-in
to PRE Command
Period
CAS Latency = 2 tDAL2
CAS Latency = 1 tDAL1
tBWC
3
—
3
—
2
—
2
—
20
30
30
30
6
—
24
36
36
36
6
—
CAS Latency = 3 tBPL3
CAS Latency = 2 tBPL2
CAS Latency = 1 tBPL1
CAS Latency = 3 tBAL3
CAS Latency = 2 tBAL2
CAS Latency = 1 tBAL1
—
—
ns
—
—
ns
—
—
ns
Block Write Data-in
Active (REF)
Command Period
(Auto Precharge)
—
—
CLK
CLK
CLK
ns
4
—
4
—
2
—
2
—
Mode Register Set Cycle Time
CKE Setup Time
tRSC
20
—
20
—
tPDE
8
—
10
—
ns
(Precharge Power Down Exit)
Transition Time
tT
1
30
16
1
30
16
ns
Refresh Time
tREF
—
—
ms
33/66
¡ Semiconductor
MSM54V25632A
TIMING WAVEFORM
AC Parameters for Read Timing (BL = 2, CL = 2)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
tCK
CLK
tCH tCL
tCKS
tCMS tCMH
Auto Precharge
Start for Bank B
CKE
tCKH
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
tAS
tAH
tCMH
tAC
tCMS
DQM
0 - 3
tAC
tHZ
tOH
tRC
Hi-Z
DQ
tRCD
tLZ
tOH
tRAS
tRRD
tRP
ACT-A
RD-A
ACT-B
RAP-B
PRE-A
ACT-A
34/66
¡ Semiconductor
MSM54V25632A
AC Parameters for Write Timing (BL = 4, CL = 2)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
Auto Precharge
Auto Precharge
tCKS
tCMS CMH
tCKH
Start for Bank A Start for Bank B
t
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
tAS
tAH
tDS
tRCD
tCMH
tCMS
DQM
0 - 3
tDH
Hi-Z
DQ
tRRD
tDAL
tDPL
tRP
tRC
ACT-A WAP-A ACT-B WAP-B ACT-A
WAP-A
PRE-A ACT-A
35/66
¡ Semiconductor
MSM54V25632A
Relationship between Frequency and Latency
Rate
Clock Cycle Time [ns]
Frequency [MHꢀ]
CAS Latency
MSM54V25632A-10
MSM54V25632A-12
18
10
100
3
15
66
2
30
33
1
12
83
3
36
28
1
55
2
[tRCD
]
3
2
1
3
2
1
RAS Latency
6
4
2
6
4
2
(CAS Latency + [tRCD])
[tRC
[tRAS
[tRRD
[tRP
]
9
6
2
3
2
5
6
4
2
2
2
3
3
2
1
1
1
2
9
6
2
3
2
5
6
4
2
2
2
3
3
2
1
1
1
2
]
]
]
[tDPL
]
[tDAL
]
36/66
¡ Semiconductor
MSM54V25632A
Power on Sequence and Auto Refresh (Initialization)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
High level is necessary
8 refresh cycles are necessary
RAS
CAS
WE
DSF
A9
(BA)
A8
ADDRESS KEY
ADD
DQM
0 - 3
High level is necessary
Hi-Z
DQ
REF
REF
MRA
PRE
(All Banks)
tRC
tRC
37/66
¡ Semiconductor
MSM54V25632A
Mode Register Set (BL = 4, CL = 2)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
tRSC (20 ns)
H
RAS
CAS
WE
DSF
A9
(BA)
A8
ADDRESS KEY
ADD
DQM
0 - 3
Hi-Z
DQ
PRE
(All Banks)
MRA
ACT
tRP
38/66
¡ Semiconductor
MSM54V25632A
Auto Refresh (CL = 2)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
DQM
0 - 3
L
DQ
Q1
PRE
REF
REF
ACT
RD
tRP
tRC
tRC
39/66
¡ Semiconductor
MSM54V25632A
Self Refresh (Entry and Exit)
0
1
2
3
4
7
8
9
10 11 12
17 18 19 20 21
CLK
CKE
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
ADD
DQM
0 - 3
L
DQ
PRE
SREF
entry
SREF
Exit
SREF
entry
or
SREF
Exit
ACT
(ACT)
Next
clock
enable
Next clock
enable
tRP
tRC
tRC
40/66
¡ Semiconductor
MSM54V25632A
Auto Precharge after Read Burst (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
RAa
RBa
RBb
RBb
A8
ADD
RAa
CAa RBa
CBa
CAb
CBb
DQM
0 - 3
L
Hi-Z
DQ
QAa1 QAa2 QAa3 QAa4 QBa1 QBa2 QBa3 QBa4 QAb1 QAb2 QAb3 QAb4
QBb1 QBb2
ACT-A
ACT-B
RD-A
RAP-A
RAP-B
AP-A
RAP-B
AP-B
ACT-B
41/66
¡ Semiconductor
MSM54V25632A
Auto Precharge after Write Burst (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
RAa
RBa
RBb
RBb
A8
ADD
RAa
CAa RBa
CBa
CAb
CBb
DQM
0 - 3
L
Hi-Z
DQ
DAa1 DAa2 DAa3 DAa4 DBa1 DBa2 DBa3 DBa4 DAb1 DAb2 DAb3 DAb4
DBb1 DBb2 DBb3 DBb4
ACT-A
ACT-B
WAP-A
ACT-B
WAP-B
WT-A
WAP-B
AP-B
AP-A
42/66
¡ Semiconductor
MSM54V25632A
Full Page READ Cycle (CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
RAa
RBa
RBb
A8
ADD
RAa
CAa
RBa
CBa
RBb
DQM
0 - 3
L
Hi-Z
DQ
QAa QAa+1 QAa–3 QAa–2 QAa–1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+5
ACT-B
ACT-A
RD-A
RD-B
Burst cannot
end in Full
PRE-B
ACT-B
Burst stop
Command
Page mode
tRP
43/66
¡ Semiconductor
MSM54V25632A
Full Page WRITE Cycle (CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
H
CKE
CS
RAS
CAS
WE
DSF
A9
(BA)
RAa
RBa
RBa
RBb
A8
ADD
RAa
CAa
CBa
RBb
DQM
0 - 3
L
Hi-Z
DQ
DAa DAa+1 DAa+2 DAa+3 DAa–1 DAa DAa+1 DBa DBa+1 DBa+2 DBa+3 DBa+4
ACT-B
ACT-A
WT-A
Burst cannot
end in Full
Page mode
WT-B
PRE-B
ACT-B
Burst stop
Command
tRP
44/66
¡ Semiconductor
MSM54V25632A
PRE (Precharge) Termination of Burst (BL = 2, 4, 8, Full, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
RAb
RAc
RAc
ADD
RAa
L
CAa
RAb
CAb
DQM
0 - 3
Hi-Z
DQ
DAa1 DAa2
QAb1 QAb2 QAb3
ACT-A
WT-A
RD-A
PRE-A
ACT-A
PRE-A
ACT-A
PRE Command
Termination
tRCD
PRE Command
Termination
tRAS
tDPL
tRP
tRP
45/66
¡ Semiconductor
MSM54V25632A
Clock Suspension during Burst Read (using CKE Function) (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
RAa
ADD
CAa
DQM
0 - 3
L
DQ
QAa1 QAa2
QAa3
QAa4
ACT-A
RD-A
1-CLOCK
2-CLOCK
3-CLOCK
SUSPENDED
SUSPENDED SUSPENDED
Hi-Z
(turn off)
at end of burst
46/66
¡ Semiconductor
MSM54V25632A
Clock Suspension during Burst Write (using CKE Function) (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
RAa
ADD
CAa
DQM
0 - 3
L
DQ
DAa1
DAa2
DAa3
DAa4
ACT-A
1-CLOCK
2-CLOCK
3-CLOCK
SUSPENDED SUSPENDED
SUSPENDED
WT-A
47/66
¡ Semiconductor
MSM54V25632A
Power Down Mode and Clock Suspension (BL = 4, CL = 2)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
tCKS
tPDE
VALID
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
RAa
ADD
CAa
DQM
0 - 3
L
DQ
QAa1 QAa2
QAa3
QAa4
ACT-A
RD-A
PRE-A
PD Entry
PD Exit
Clock Mask
Start
Clock Mask
End
PD
PD
ACTIVE STANDBY
PRECHARGE STANDBY
48/66
¡ Semiconductor
MSM54V25632A
CLOCK Suspend Exit & Power Down Exit
1) Clock Suspend (= Active Power Down) Exit
CLK
2) Power Down (= Precharge Power Down) Exit
CLK
Note 3
(CASE 1)
CKE
CKE
tCKS
≥ tPDE
Internal
CLK
Internal
CLK
Note 1
Note 2
Note 2
RD
ACT
Note 4
Command
Command
(CASE 2)
CKE
Internal
CLK
< tPDE
Command
NOP ACT
Notes: 1. Active power down: one or both bank active state.
2. Precharge power down: both bank precharge state.
3.
t
: Asynchronous AC parameter. Time for Power Down Exit Setup Time. Only
PDE
valid at precharge power down exit.
4.
t
< t
, NOP should be issued. And new command can be issued after 1 Clock.
PDE
CKS
49/66
¡ Semiconductor
MSM54V25632A
Byte Read/Write Operation (by DQM) (BL = 4, CL = 2)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
RBa
RBa
A8
ADD
CBa
CBb
CBc
DQM0
DQM1
DQ
QBa1 QBa2 QBa3
DBb2 DBb3
DBb1 DBb2
QBc2 QBc3
0 - 7
DQ
QBa2 QBa3 QBa4
DBb4
QBc1 QBc2 QBc3 QBc4
8 - 15
ACT-B RD-B Byte of
DQ8 - 15
Byte of
DQ0 - 7
not Read
Byte of RD-B Byte of
Byte of
DQ0 - 7
not Read
DQ8 - 15
not Write
DQ0 - 7
not Read
not Read
Byte of DQ0 - 7
not Write
Byte of DQ0 - 7
not Write
WT-B
50/66
¡ Semiconductor
MSM54V25632A
Burst Read and Single Write (BL = 4, CL = 2)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
RBa
RBa
A8
CBa
CBb
CBc
CBd
CBe
DBe
ADD
DQM0
DQM1
Write
Masking
DQ
QBa1 QBa2 QBa3 QBa4
DBb
0 - 7
DQ
DBc
QBd1
8 - 15
ACT-B RD-B
Single Single
WT WT
RD
Single
WT
51/66
¡ Semiconductor
MSM54V25632A
Special Mode Register Set (BL = 4, CL = 2)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
tRSC (20 ns)
RAS
CAS
WE
DSF
A9
(BA)
A8
ADDRESS KEY
ADD
DQM
0 - 3
Color or Mask data
Hi-Z
DQ
PRE
SMRA
ACT
(All Banks)
is valid
tRP
Remark Special Register Set command can be input at any state.
52/66
¡ Semiconductor
MSM54V25632A
Random Row Write with WPB (BL = 8, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
RAa
RAa
RBa
RBa
RAb
A8
ADD
CAa
CBa
RAb
CAb
DQM
0 - 3
L
DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DBa1 DBa2 DBa3 DBa4 DBa5 DBa6 DBa7 DBa8 DAb1 DAb2 DAb3
DQ
ACT-A
WT-A
ACT-B
WT-B
PRE-A
ACT-A
WT-A
PRE-B
with WPB WPB is enabled.
WPB is disabled.
WPB is disabled.
tRCD
tDPL
tRP
tDPL
53/66
¡ Semiconductor
MSM54V25632A
Block Write (Page at Same Bank) (CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
RBa
RBb
A8
RBa
CBa
I/O Mask
CBb
CBc
CBd
I/O Mask
RBb
CBc
I/O Mask
ADD
I/O Mask I/O Mask
DQM
0 - 3
L = No I/O Mask
CM
CM
CM
CM
CM
DQ
ACT-B
BW-B
BW-B
BW-B
BW-B
PRE-B
ACT-B
BW-B
with WPB WPB is enabled.
tRCD
tBWC
tBWC
tBWC
tBPL
tRP tRCD
54/66
¡ Semiconductor
MSM54V25632A
Block Write (Page at Same Bank) Changing Color and Mask Data (CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
RBa
RBb
A8
RBa
CBa
I/O Mask
20h
CBb
I/O Mask
40h
CBc
I/O Mask
CBd
I/O Mask
RBb
ADD
DQM
0 - 3
CM
Mask
CM
Color
CM
CM
DQ
ACT-B
BW-B
SMRA
BW-B
SMRA
BW-B
BW-B
PRE-B
ACT-B
with WPB
(Mask data)
(Color data)
tRCD
tBWC
tRSC (20 ns)
tBWC
tRSC (20 ns)
tBWC
tBPL
tRCD
55/66
¡ Semiconductor
MSM54V25632A
Interleaved Block Write (CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
RAa
RBa
RBb
ADD
CAa RBa
CBa
CAb
CBb
CM
RBb
DQM
0 - 3
L
Column Mask
CM
CM
CM
DQ
ACT-A
ACT-B
PRE-B
ACT-B
BW-A
BW-B
BW-A
BW-B
tRCD
tRCD
tBWC
tBWC
tBPL
tRP
56/66
¡ Semiconductor
MSM54V25632A
Random Column Read (Page with Same Bank) (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
RAa
RAa
RAa
A8
CAa
CAb
CAc
RAa
CAa
ADD
DQM
0 - 3
L
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
DQ
ACT-A
RD-A
RD-A
PRE-A
ACT-A
RD-A
RD-A
tRP
57/66
¡ Semiconductor
MSM54V25632A
Random Column Write (Page with Same Bank) (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
A8
RBa
RBa
RBd
CBa
CBb
CBc
RBd
CBd
ADD
DQM
0 - 3
L
DBa1 DBa2 DBa3 DBa4 DBb1 DBb2 DBc1 DBc2 DBc3 DBc4
DBd1
DQ
ACT-B
WT-B
WT-B
PRE-B
ACT-B
WT-B
WT-B
tRP
58/66
¡ Semiconductor
MSM54V25632A
Random Row Read (BL = 8, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
A8
RBa
RBa
RAa
RAa
RBb
CBa
CAa
RBb
CBb
ADD
DQM
0 - 3
L
QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QAa8
DQ
ACT-B
RD-B
ACT-A
RD-A PRE-B
ACT-B
RD-B PRE-A
tRP
tRCD
CL
59/66
¡ Semiconductor
MSM54V25632A
Random Row Write (BL = 8, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
RAa
RAa
RBa
RBa
RAb
A8
ADD
CAa
CBa
RAb
CAb
DQM
0 - 3
L
DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DBa1 DBa2 DBa3 DBa4 DBa5 DBa6 DBa7 DBa8 DAb1 DAb2 DAb3
DQ
ACT-A
WT-A
ACT-B
WT-B PRE-A
tDPL
ACT-A
WT-A PRE-B
tDPL
tRCD
tRP
60/66
¡ Semiconductor
MSM54V25632A
READ and WRITE (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
RAa
A8
RAa
CAa
CAb
CAc
ADD
Write latency = 0
DQM
0 - 3
Write Masking
QAa1 QAa2 QAa3 QAa4
DAb1 DAb2
DAb4
QAc1 QAc2
DQ
Hi-Z
ACT-A
RD-A
WT-A
RD-A
0-clock latency
Hi-Z at the end of Burst function
2-clock latency
61/66
¡ Semiconductor
MSM54V25632A
Interleaved Column READ Cycle (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
RAa
RBa
CAb
CAa RBa
CBa
CBb
CBc
ADD
DQM
0 - 3
L
QAa1 QAa2 QAa3 QAa4 QBa1 QBa2 QBb1 QBb2 QBc1 QBc2 QAb1 QAb2 QAb3 QAb4
DQ
ACT-A
RD-A
RD-B
RD-B
RD-B
RD-A PRE-B
PRE-A
ACT-B
tRCD
CL
tRRD
62/66
¡ Semiconductor
MSM54V25632A
Interleaved Column WRITE Cycle (BL = 4, CL = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
A8
RAa
RAa
RBa
CAa RBa
CBa
CBb
CBc
CAb
CBd
ADD
DQM
0 - 3
L
DAa1 DAa2 DAa3 DAa4 DBa1 DBa2 DBb1 DBb2 DBc1 DBc2 DAb1 DAb2 DBd1 DBd2 DBd3 DBd4
DQ
ACT-A
WT-A
WT-B
WT-B
WT-B
WT-A
WT-B
PRE-B
ACT-B
PRE-A
tRCD
tDPL
tDPL
tRRD
63/66
¡ Semiconductor
MSM54V25632A
Full Page Random Column Read (BL = Full Page, CL = 2)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
RAa
RAa
RBa
A8
RBa CAa CBa CAb
tRCD
tRRD
CBb
CAc
CBc
ADD
DQM
0 - 3
tRCD
L
QAa1 QBa1 QAb1 QAb2 QBb1 QBb2 QAc1 QAc2 QAc3 QBc1 QBc2 QBc3
DQ
Hi-Z
ACT-A ACT-B RD-B
RD-A
RD-A
RD-B
RD-A
RD-B
PRE-B
(PRE Termination)
64/66
¡ Semiconductor
MSM54V25632A
Full Page Random Column Write (BL = Full Page, CL = 2)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
CLK
CKE
CS
H
RAS
CAS
WE
DSF
A9
(BA)
RAa
RAa
RBa
A8
RBa CAa CBa CAb
tRCD
tRRD
CBb
CAc
CBc
ADD
DQM
0 - 3
tRCD
L
DAa1 DBa1 DAb1 DAb2 DBb1 DBb2 DAc1 DAc2 DAc3 DBc1 DBc2 DBc3
DQ
ACT-A ACT-B WT-B
WT-B
WT-A
WT-B
PRE-B
(PRE Termination)
WT-A
WT-A
65/66
¡ Semiconductor
PACKAGE DIMENSIONS
QFP100-P-1420-0.65-BK4
MSM54V25632A
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Epoxy resin
42 alloy
Solder plating
Solder plate thickness
Package weight (g)
5 mm or more
1.54 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
ontheproductname,packagename,pinnumber,packagecodeanddesiredmountingconditions
(reflow method, temperature and times).
66/66
E2Y0002-29-11
NOTICE
1.
The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.
4.
When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.
6.
Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.
Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
thelegalityofexportoftheseproductsandwilltakeappropriateandnecessarystepsattheir
own expense for these.
8.
9.
No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.
MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
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