MSM54V32126 [OKI]
131,072-Word x 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO; 131,072字×32位动态RAM ：快速页模式输入与EDO
| 型号： | MSM54V32126 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 131,072-Word x 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
| 文件： | 总25页 (文件大小：300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2L0046-17-Y1
Preliminary
This version: Jan. 1998
Previous version: Dec. 1996
¡ Semiconductor
MSM54V32126/8
131,072-Word ¥ 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM54V32126/8 is a new generation Graphics DRAM organized in a 131,072-word ¥ 32-bit
configuration. The technology used to fabricate the MSM54V32126/8 is OKI's CMOS silicon gate
process technology. The device operates with a single 3.3 V power supply.
FEATURES
• 131,072-word ¥ 32-bit organization
• Single 3.3 V power supply, ±0.3 V tolerance
• Refresh: 512 cycles/8 ms
• Fast Page Mode with Extended Data Out (EDO)
• Write per bit (MSM54V32128 only)
• Byte write, Byte read
• RAS only refresh
• CAS before RAS refresh
• CAS before RAS self-refresh
• Hidden refresh
• Package:
64-pin 525 mil plastic SSOP (SSOP64-P-525-0.80-K)
(Product : MSM54V32126-xxGS-K)
(Product : MSM54V32128-xxGS-K)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.)
Power Dissipation
Cycle Time
Family
(Min.)
110 ns
130 ns
tRAC tAA tCAC tOEA
50 ns 25 ns 15 ns 15 ns
60 ns 30 ns 18 ns 18 ns
Operating (Max.) Standby (Max.)
MSM54V32126/8-50
MSM54V32126/8-60
504 mW
3.1 mW
486 mW
1/25
¡ Semiconductor
MSM54V32126/8
PIN CONFIGURATION (TOP VIEW)
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
1
2
3
4
5
6
7
8
9
64 VSS
63 DQ31
62 DQ30
61 DQ29
60 DQ28
59 VCC
58 DQ27
57 DQ26
56 DQ25
55 DQ24
54 VSS
DQ7 10
VSS 11
DQ8 12
DQ9 13
DQ10 14
DQ11 15
VCC 16
53 DQ23
52 DQ22
51 DQ21
50 DQ20
49 VCC
DQ12 17
DQ13 18
DQ14 19
DQ15 20
VSS 21
48 DQ19
47 DQ18
46 DQ17
45 DQ16
44 VSS
NC 22
NC 23
NC 24
43 CAS1
42 CAS2
41 CAS3
40 CAS4
39 OE
WB* / WE 25
RAS 26
NC 27
38 A8
A0 28
37 A7
A1 29
36 A6
A2 30
35 A5
A3 31
34 A4
VCC 32
33 VSS
64-Pin Plastic SSOP
Pin Name
Function
A0 - A8
DQ0 - DQ31
RAS
Address Input
Data Input / Data Output
Row Address Strobe
Column Address Strobe
CAS1 - CAS4
WB* / WE
OE
Write Per Bit* / Write Enable
Output Enable
VCC
Power Supply (3.3 V)
Ground (0 V)
VSS
NC
No Connection
Note:
*:
The same power supply voltage must be provided to every V pin, and the same GND
CC
voltage level must be provided to every V pin.
SS
MSM54V32128 only
2/25
WB / WE
OE
Timing
RAS
Generator
Output
Buffers
I/O
Controller
8
8
8
8
8
8
8
8
CAS1
DQ0 - DQ7
I/O
Controller
Input
Buffers
CAS2
CAS3
CAS4
I/O
Controller
Output
Buffers
I/O
Controller
DQ8 - DQ15
Column
Input
Buffers
8
9
8
Column Decoders
Sense Amps
Address
Buffers
I/O
Selector
Internal
Address
Counter
32
32
Refresh
Control Clock
A0 - A8
Input
Buffers
8
8
8
8
8
8
8
8
Row
Row
Deco-
ders
9
Address
Buffers
Word
Drivers
Memory
Cells
DQ16 - DQ23
Output
Buffers
VCC
Input
Buffers
On-chip
BB Generator
DQ24 - DQ31
V
Output
Buffers
VSS
¡ Semiconductor
MSM54V32126/8
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to VSS
Short Circuit Output Current
Power Dissipation
Symbol
VT
Rating
–0.5 to 4.5
50
Unit
V
IOS
mA
W
PD
1
Operating Temperature
Storage Temperature
Topr
Tstg
0 to 70
–55 to 150
°C
°C
Recommended Operating Conditions
(Ta = 0°C to 70°C)
Parameter
Symbol
VCC
Min.
3.0
0
Typ.
3.3
0
Max.
Unit
3.6
0
V
V
V
V
Power Supply Voltage
VSS
Input High Voltage
Input Low Voltage
VIH
3.0
–0.3
—
3.6
0.3
VIL
—
Capacitance
(VCC = 3.3 V 0.3 Vꢀ Ta = 25°Cꢀ f = 1 MHꢁ)
Parameter
Input Capacitance
Symbol
CIN
Typ.
Max.
Unit
pF
—
—
7
7
Input / Output Capacitance
CIO
pF
4/25
¡ Semiconductor
DC Characteristics
Parameter
MSM54V32126/8
(VCC = 3.3 V 0.3 Vꢀ Ta = 0°C to 70°C)
MSM54V32126/8 MSM54V32126/8
-50 -60
Symbol
Condition
Unit Note
Min.
2.0
0
Max.
VCC
Min.
2.0
0
Max.
VCC
Output High Voltage
Output Low Voltage
VOH
VOL
IOH = –0.1 mA
V
V
I
OL = 0.1 mA
0.8
0.8
0 V < VIN < VCC
;
All other pins not
under test = 0 V
Input Leakage Current
Output Leakage Current
ILI
–10
–10
—
10
10
–10
–10
—
10
10
mA
0 V < VOUT < 3.6 V
Output Disable
ILO
mA
Average Power
Supply Current
(Operating)
RASꢀ CAS cyclingꢀ
ICC1
ICC2
ICC3
130
110
mA 1ꢀ 2ꢀ 3
mA
tRC = Min.
Power Supply
Current (Standby)
RASꢀ CAS ≥ VCC – 0.2 V
—
—
850
130
—
—
850
110
Average Power
Supply Current
(RAS Only Refresh)
RAS = cyclingꢀ
CAS = VIHꢀ
mA 1ꢀ 2ꢀ 3
tRC = Min.
Average Power
Supply Current
(Fast Page Mode)
RAS = VILꢀ
ICC4
ICC5
ICCS
—
—
—
140
130
950
—
—
—
135
110
950
mA 1ꢀ 2ꢀ 4
mA 1ꢀ 2ꢀ 4
CAS cyclingꢀ
tHPC = Min.
Average Power
Supply Current
(CAS before RAS Refresh)
RAS = cyclingꢀ
CAS before RAS
Average Power Supply
Current (CAS before RAS
Self-Refresh)
RAS = VILꢀ
CAS = VIL
mA
1ꢀ 2
Notes: 1. Specified values are obtained with minimum cycle time.
2. I is dependent on output loading. Specified values are obtained with the output
CC
open.
3. Address can be changed once or less while RAS = V .
IL
4. Address can be changed once or less while CAS = V
.
IH
5/25
¡ Semiconductor
MSM54V32126/8
AC Characteristics (1/2)
(VCC = 3.3 V 0.3 Vꢀ Ta = 0°C to 70°C) Note 1ꢀ 2ꢀ 3
MSM54V32126/8 MSM54V32126/8
-50
-60
Parameter
Symbol
Unit Note
Min.
110
145
22
70
—
—
—
—
3
Max.
—
—
—
—
50
25
15
30
20
20
35
—
10k
100k
—
—
10k
35
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
130
170
24
80
—
—
—
—
3
Max.
—
—
—
—
60
30
18
35
20
20
35
—
10k
100k
—
—
10k
42
30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Random Read or Write Cycle Time
Read Modify Write Cycle
tRC
tRWC
tHPC
tPRWC
tRAC
tAA
ns
ns
Fast Page Mode Cycle Time
ns
Fast Page Mode Read-Modify-Write Cycle Time
Access Time from RAS
ns
ns 4ꢀ 9ꢀ 10
ns 4ꢀ 10
ns 4ꢀ 9
ns 4ꢀ 13
Access Time from Column Address
Access Time from CAS
tCAC
tCPA
tREZ
tCEZ
tT
Access Time from CAS Precharge
Output Buffer Turn-off Delay Time from RAS
Output Buffer Turn-off Delay Time from CAS
Transition Time (Rise and Fall)
RAS Precharge Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5
3
3
3
3
3
tRP
54
50
50
14
50
8
64
60
60
14
60
9
RAS Pulse Width
tRAS
tRASP
tRSH
tCSH
tCAS
tRCD
tRAD
tRAL
tCRP
tCP
RAS Pulse Width (Hyper Page Mode Only)
RAS Hold Time
CAS Hold Time
CAS Pulse Width
RAS to CAS Delay Time
20
15
24
6
20
15
28
8
9
RAS to Column Address Delay Time
Column Address to RAS Lead Time
CAS to RAS Precharge Time
CAS Precharge Time (Hyper Page Mode)
Row Address Set-up Time
10
13
15
8
9
tASR
tRAH
tASC
tCAH
tAR
0
0
Row Address Hold Time
7
9
Column Address Set-up Time
Column Address Hold Time
0
0
12
12
8
10
40
0
Column Address Hold Time referenced to RAS
Read Command Set-up Time
Read Command Hold Time
35
0
tRCS
tRCH
tRRH
tCRL
tRCL
tDOH
tWCS
tWCH
12
0
0
ns 6ꢀ 12
Read Command Hold Time referenced to RAS
CAS "H" to RAS "H" Lead Time
RAS "H" to CAS "H" Lead Time
Data Output Hold after CAS Low
Write Command Set-up Time
Write Command Hold Time
0
0
ns
ns
ns
ns
6
0
0
0
0
3
3
11
0
0
ns 8ꢀ 12
8
10
ns
12
6/25
¡ Semiconductor
MSM54V32126/8
AC Characteristics (2/2)
(VCC = 3.3 V 0.3 Vꢀ Ta = 0°C to 70°C) Note 1ꢀ 2ꢀ 3
MSM54V32126/8 MSM54V32126/8
-50
-60
Parameter
Symbol
Unit Note
Min.
35
9
Max.
—
—
—
—
20
—
—
—
—
—
—
—
—
—
15
20
—
—
—
—
—
—
—
—
—
—
8
Min.
40
10
10
10
3
Max.
—
—
—
—
20
—
—
—
—
—
—
—
—
—
18
20
—
—
—
—
—
—
—
—
—
—
8
Write Command Hold Time referenced to RAS
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Output Buffer Turn-off Delay Time from WE
Data Set-up Time
tWCR
tWP
ns
ns
ns
tRWL
tCWL
tWEZ
tDS
9
9
ns
ns
14
5
3
0
0
ns 7ꢀ 12
ns 7ꢀ 12
ns
Data Hold Time
tDH
8
10
40
12
80
50
40
0
Data Hold Time referenced to RAS
OE to Data-in Delay Time
tDHR
tOED
tRWD
tAWD
tCWD
tDZC
tDZO
tOEA
tOEZ
tOEH
tROH
tOCH
tCHO
tOEP
tWPE
tCSR
tCHR
tRPC
tCPT
tREF
tWSR
tRWH
tMS
35
12
70
45
35
0
ns
RAS to WE Delay Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ms
ns
ns
8
8
8
Column Address to WE Delay Time
CAS to WE Delay Time
Data to CAS Delay Time
Data to OE Delay Time
0
0
Access Time from OE
—
3
—
3
Output Buffer Turn-off Delay Time from OE
OE Command Hold Time
5
9
10
12
10
10
12
12
10
10
10
30
—
0
RAS Hold Time referenced to OE
OE "L" to CAS "H" Lead Time
10
10
10
10
10
8
CAS "H" to OE "L" Lead Time
High-Z Command Pulse Width
WB/WE Pulse Width (Output Disable)
CAS Set-up Time for CAS before RAS Cycle
CAS Hold Time for CAS before RAS Cycle
RAS Precharge to CAS Active Time
CAS Precharge Time (Refresh Counter Test)
Refresh Period
12
13
12
15
8
10
25
—
0
WB Set-up Time
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16
16
16
16
WB Hold Time
7
8
Write-Per-Bit Mask Data Set-up Time
Write-Per-Bit Mask Data Hold Time
RAS Pulse Width (CAS before RAS Self-Refresh)
RAS Precharge Time (CAS before RAS Self-Refresh)
CAS Hold Time (CAS before RAS Self-Refresh)
0
0
tMH
8
10
100
130
0
tRASS
tRPS
tCHS
100
110
0
7/25
¡ Semiconductor
MSM54V32126/8
Notes: 1. An initial pause of 200 ms is required after power-up followed by any 8 RAS cycles
(Example : RAS only refresh) before proper device operation is achieved. In case of
usinginternalrefreshcounter,aminimumof8CASbeforeRAScyclesinsteadof8RAS
cycles are required.
2. The AC characteristics assume at t = 3 ns.
T
3. V (Min.) and V (Max.) are reference levels for measuring timing of input signals.
IH
IL
Also,transitiontimesaremeasuredbetweenV andV .InputlevelsattheACtesting
IH
IL
are 3.0 V/0 V.
4. Data outputs are measured with a load of 30 pF.
DOUT reference levels : V /V = 2.0 V/0.8 V.
OH
OL
5. t
(Max.), t
(Max.), t
(Max.) and t (Max.) define the time at which the
REZ
CEZ
WEZ
OEZ
outputsachievetheopencircuitconditionandarenotreferencedtooutputvoltage
levels. This parameter is sampled and not 100% tested.
6. Either t
or t
must be satisfied for a read cycle.
RCH
RRH
7. TheseparametersarereferencedtoCASleadingedgeofearlywritecyclesandtoWE
leading edge in OE controlled write cycles and read modify write cycles.
8. t
, t
, t
and t
are not restrictive operating parameters. They are included
WCS RWD CWD
AWD
in the data sheet as electrical characteristics only. If t
≥ t
(Min.), the cycle is an
WCS
WCS
early write cycle and the data out pin will remain open circuit throughout the entire
cycle; If t ≥ t (Min.), t ≥ t (Min.) and t ≥ t (Min.), the cycle is
RWD
RWD
CWD
CWD
AWD
AWD
areadmodifywritecycleandthedataoutwillcontaindatareadfromtheselectedcell:
If neither of the above sets of conditions is satisfied, the condition of the data out is
indeterminate.
9. Operation within the t
(Max.) limit ensures that t
(Max.) can be met.
is greater than the specified
RCD
RAC
t
t
(Max.) is specified as a reference point only: If t
(Max.) limit, then access time is controlled by t
RCD
RCD
.
RCD
CAC
10. Operationwithinthet
(Max.)limitensuresthatt
(Max.)canbemet. t
(Max.)
(Max.)
RAD
RAC
RAD
RAD
is specified as a reference point only: If t
is greater than the specified t
RAD
limit, then access time is controlled by t
.
AA
11. This is guaranteed by design. (t
= t
- output transition time) This parameter is
DOH
CAC
not 100% tested.
12. Theseparameters aredeterminedby the earliestfalling edge ofCAS1, CAS2, CAS3, or
CAS4.
13. These parameters are determined by the latest rising edge of CAS1, CAS2, CAS3, or
CAS4.
CWL
14. t
should be satisfied by all CASes.
15. t and t
are determined by the time that all CASes are high.
CPT
CP
16. Only MSM54V32128.
8/25
¡ Semiconductor
MSM54V32126/8
CASn-DQ FUNCTION TABLE
CAS1
CAS2
CAS3
CAS4
DQ0-7
DQ8-15
DQ16-23
DQ24-31
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
L
H
L
*
*
*
*
*
*
*
Enable
*
H
L
*
*
Enable
Enable
*
L
*
*
Enable
*
H
H
L
H
L
*
Enable
Enable
Enable
Enable
*
L
*
*
Enable
*
L
H
L
*
Enable
Enable
*
L
L
*
Enable
*
H
H
H
H
L
H
H
L
H
L
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
L
*
*
Enable
*
L
H
L
*
Enable
Enable
*
L
L
*
Enable
*
L
H
H
L
H
L
Enable
Enable
Enable
Enable
L
L
*
Enable
*
L
L
H
L
Enable
Enable
L
L
L
Enable
Enable
*
Read cycle
Write cycle
Valid Data-out
Write Data
High-Z
Don't Care
WRITE CYCLE FUNCTION TABLE
RAS falling edge
CAS or WB / WE falling edge
CODE
A
WB / WE
L
B
C
Function
DQ
DQ
RWM (*1)
Write per bit
Normal write
Write mask
Don't care
Write data
Write data
RW
H (*2)
Write mask : 'L' = Mask, 'H' = No mask
(*1):
(*2):
MSM54V32128 only.
In case of MSM54V32126, don't care.
9/25
¡ Semiconductor
MSM54V32126/8
TIMING WAVEFORM
Read Cycle (Outputs Controlled by RAS)
tRC
tRP
tRAS
RAS
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
CAS1
|
tCRL
tRAD
tASR tRAH
CAS4
tRAL
tASC
Column
tRCS
tCAH
Row
Address
tAR
tRRH
tRCH
WB / WE
tROH
tOEA
tCAC
OE
tREZ
tOEZ
Valid Data-out
tAA
Open
DQ0 - DQ31
tRAC
"H" or "L"
10/25
¡ Semiconductor
MSM54V32126/8
Read Cycle (Outputs Controlled by CAS)
tRC
tRP
tRAS
RAS
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
CAS1
|
tRAD
tASR tRAH
CAS4
tRAL
tASC
Column
tRCS
tCAH
tRCL
Row
Address
tRCH
tAR
tRRH
WB / WE
tROH
tOEA
tCAC
OE
tCEZ
tOEZ
Valid Data-out
tAA
Open
DQ0 - DQ31
tRAC
"H" or "L"
11/25
¡ Semiconductor
MSM54V32126/8
Write Cycle (Early Write)
tRC
tRAS
tRP
tAR
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
CAS1
|
CAS4
tRAD
tRAH
tRAL
tASR
Row
tWSR tRWH
A
tASC
tCAH
Address
WB / WE
OE
Column
tCWL
tRWL
tWP
tWCH
tWCS
tWCR
tMS
tMH
tDS
tDH
DQ0 - DQ31
B
C
tDHR
"H" or "L"
12/25
¡ Semiconductor
MSM54V32126/8
Write Cycle (OE Control Write)
tRC
tRAS
tRP
tAR
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
CAS1
|
CAS4
tRAD
tRAH
tRAL
tASR
Row
tASC
tCAH
Column
Address
WB / WE
OE
tCWL
tRWL
tWP
tRCS
tWSR tRWH
A
tWCR
tOEH
tOED
tDHR
tMS
tMH
tDS
tDH
DQ0 - DQ31
B
C
"H" or "L"
13/25
¡ Semiconductor
MSM54V32126/8
Read Modify Write Cycle
tRWC
tRAS
tRP
tAR
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
CAS1
|
CAS4
tRAD
tRAH
tRAL
tASR
Row
tASC
tCAH
Address
WB / WE
OE
Column
tCWL
tRWL
tWP
tCWD
tRCS
tWSR tRWH
A
tAWD
tRWD
tOEA
tOEH
tDZO
tOED
tOEZ
tMS
tMH
tAA
tDS tDH
DQ0 - DQ31
B
OUT
C
tDZC tCAC
tRAC
"H" or "L"
14/25
¡ Semiconductor
MSM54V32126/8
Fast Page Mode Read Cycle with EDO
tRC
tRASP
tRP
tAR
RAS
tCSH
tHPC
tCAS
tRSH
tCAS
tCRP
tCRP
tRCD
tRAD
tCP
tCP
CAS1
|
CAS4
tCAS
tRAL
tASC
tASR
Row
tASC
tCAH
tCAH
tCAH
tASC
tRAH
Column
Column
tRCS
Column
tRCS
tRCH
Address
tRRH
tRCS
tRCH
tRCH
WB / WE
tOEA
OE
tCAC
tAA
tCAC
tCAC
tREZ
tOEZ
tDOH
tDOH
Valid
Data-out
Valid
Data-out
Valid
Data-out
Open
DQ0 - DQ31
tRAC
tAA
tCPA
tAA
tCPA
"H" or "L"
15/25
¡ Semiconductor
MSM54V32126/8
Fast Page Mode Write Cycle (Early Write)
tRC
tRASP
tRP
tAR
RAS
tCSH
tHPC
tCAS
tRSH
tCAS
tRAL
tCRP
tRCD
tCRP
tCP
tCP
tCAS
CAS1
|
CAS4
tRAD
tASC
tASR tRAH
Row
tASC
Column
tCWL
tWCH
tCAH
tCAH
tASC tCAH
Column
Column
Address
tCWL
tCWL
tWCH
tWSR tRWH tWCS
tWCS
tWCS
tWCH
tWP
tWP
tWP
A
WB / WE
tWCR
tRWL
OE
tDHR
tMS
tDS
tDS
tDS
tDH
tMH
tDH
tDH
B
C
C
C
DQ0 - DQ31
"H" or "L"
16/25
¡ Semiconductor
MSM54V32126/8
Fast Page Mode Read Modify Write Cycle
tRC
tRASP
tRP
tAR
RAS
tCSH
tPRWC
tCAS
tRSH
tCAS
tRAL
tCRP
tRCD
tCRP
tCP
tCP
tCAS
CAS1
|
CAS4
tRAD
tASC
tASR tRAH
Row
tASC
tCAH
tCAH
tASC tCAH
Column
tCWD
Column
tCWD
Column
Address
tRWL
tCWL
tCWD
tWSR tRWH tRCS
A
tCWL
tCWL
WB / WE
tAWD
tOEA
tRWD
tAWD
tOEA
tAWD
tOEA
tWP
tWP
tWP
tROH
tOEH
OE
tOED
tOEZ
tOED
tOEZ
tOED
tOEZ
tAA
tAA
tAA
tDH
tDH
tDH
C
tMS
tMH
tDS
OUT
tDS
OUT
tDS
OUT
B
C
C
DQ0 - DQ31
tCAC
tRAC
tCAC
tCAC
"H" or "L"
17/25
¡ Semiconductor
MSM54V32126/8
RAS Only Refresh Cycle
tRC
tRP
tRAS
RAS
tRPC
tCRP
CAS1
|
CAS4
tASR tRAH
Row
Address
"H" or "L"
Note: DQs are openꢀ WB / WEꢀ OE = "H" or "L"
18/25
¡ Semiconductor
MSM54V32126/8
CAS before RAS Refresh Cycle
tRC
tRP
tRP
tRAS
RAS
tRPC
tCP
tCSR
tCHR
CASn
tCEZ
Open
DQ0 - DQ31
Note: WB / WEꢀ OEꢀ A0 - A8 = "H" or "L"
19/25
¡ Semiconductor
MSM54V32126/8
Hidden Refresh Read Cycle
tRC
tRC
tRAS
tRP
tRP
tRAS
RAS
tCRP
tRSH
tRCD
tCHR
CAS1
|
CAS4
tRAD
tRAL
tCAH
tASR tRAH
tASC
Address
Row
Column
tAR
tRCS
tRRH
WB / WE
tROH
OE
tOEA
tCAC
tOEZ
tREZ
DQ0 - DQ31
Valid Data-out
tAA
tRAC
"H" or "L"
20/25
¡ Semiconductor
MSM54V32126/8
Hidden Refresh Write Cycle
tRC
tRAS
tRC
tRAS
tRP
tRP
RAS
tCRP
tRCD
tRSH
tCHR
CAS1
|
CAS4
tRAL
tCAH
tRAD
tASC
tASR
tRAH
Row
Column
Address
tAR
tWCS
tWSR tRWH
A
tWCH
tWP
WB / WE
tRWL
tWCR
OE
tMS
tMH tDS
tDH
B
C
DQ0 - DQ31
tDHR
"H" or "L"
21/25
¡ Semiconductor
MSM54V32126/8
CAS before RAS Refresh Counter Test Cycle
tRAS
tRP
RAS
tCSR
tCHR
tCPT
tRSH
CAS1
|
tCAS
CAS4
tASC
tCAH
Column
Address
tRAL
tRRH
tRCH
Read Cycle
WB / WE
OE
tRCS
tCAC
tROH
tAA
tOEA
tCEZ
tAA
tOEZ
Valid Data-out
Open
DQ0 - DQ31
tRWL
tCWL
tWCH
tWP
Write Cycle
tWCS
WB / WE
OE
tDS
tDH
Open
DQ0 - DQ31
Valid Data-in
tRWL
tCWL
tAWD
Read Modify Write Cycle
tRCS
tCWD
tWP
WB / WE
tOEA
OE
tOED
tOEZ
tCAC
tDS tDH
tAA
Valid
Data-out
Valid
Data-in
Open
DQ0 - DQ31
"H" or "L"
22/25
¡ Semiconductor
MSM54V32126/8
CAS before RAS Self-Refresh Cycle
tRASS
tRPS
tRP
tRPC
tCP
RAS
tRPC
tCHS
tCSR
CASn
tCEZ
Open
Note: WB / WEꢀ OEꢀ A0 - A8 = "H" or "L"
DQ0 - DQ31
"H" or "L"
23/25
tRC
tRP
tRASP
tAR
tCSH
RAS
tHPC
tRSH
tCRP
tRCD
tCP
tCP
tCP
tCRP
tCAS
tCAS
tCAS
tCAS
tRAL
CAS1
|
CAS4
tRAD
tASR tRAH
Row
tASC
tCAH
tASC tCAH
Column
tASC tCAH
Column
tASC tCAH
Column
Column
Address
WB / WE
OE
tRRH
tRCS
tRCH
tRCS
tRCH
tRAC
tCHO
tOEP
tOCH
tWPE
tOEA
tCAC
tAA
tOEP
tCAC
tCAC
tAA
tCPA
tDOH
tAA
tCAC
tAA
tOEZ
tOEA
tOEZ tOEA
tWEZ
tREZ
Valid
Data-out
Valid
Data-out
Valid*
Data-out
Valid*
Data-out
Valid
Data-out
Open
DQ0 - DQ31
* : Same Data
"H" or "L"
¡ Semiconductor
PACKAGE DIMENSIONS
SSOP64-P-525-0.80-K
MSM54V32126/8
(Unit : mm)
Mirror finish
Package material
Lead frame material
Pin treatment
Epoxy resin
42 alloy
Solder plating
Solder plate thickness
Package weight (g)
5 mm or more
1.34 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
25/25
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