MK31VT864 [OKI]
8,388,608 Word x 64 Bit SYNCHRONOUS DYNAMIC RAM MODULE (1BANK); 8,388,608字×64位同步动态RAM模块（ 1BANK ）
| 型号： | MK31VT864 |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 8,388,608 Word x 64 Bit SYNCHRONOUS DYNAMIC RAM MODULE (1BANK) |
| 文件： | 总11页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MK31VT864-10YE (98.09.03)
Semiconductor
MK31VT864-10YE
8,388,608 Word x 64 Bit SYNCHRONOUS DYNAMIC RAM MODULE (1BANK):
DESCRIPTION
The Oki MK31VT864-10YE is a fully decoded, 8,388,608 x 64bit synchronous dynamic
random access memory composed of eight 64Mb DRAMs (8Mx8) in TSOP packages
mounted with decoupling capacitors on a 144-pin glass epoxy Small-outline Dual-in-Line
Package supports any application where high density and large capacity of storage
memory are required, like for example Mobile PC or PDAs.
FEATURES
•
•
•
•
•
•
•
8-Meg Word x 64-bit (1Bank 8Byte) organization
144-pin Small-Outline Dual Inline Memory Module
Single 3.3V power supply, ±0.3V tolerance
Input
:LVTTL compatible
Output :LVTTL compatible
Refresh : 4,096 cycles / 64 ms
Programmable data transfer mode
• /CAS latency (2, 3)
• Burst length (2, 4, 8)
• Data scramble (sequential, interleave)
/CAS before /RAS auto-refresh, Self-refresh capability
Serial Presence Detect (SPD) With EEPROM
•
•
PRODUCT ORGANIZATION
Operation
Access Time (Max.)
Product Name
Frequency (Max.)
tAC2
tAC3
MK31VT864-10YE
100 MHz
9.0ns
9.0ns
Note. Specification are subject to change without notice.
Page 1/11
MK31VT864-10YE (98.09.03)
BLOCK DIAGRAM
CKE0
/CS0
DQMB0
DQ0
/CS CKE
DQMB4
DQ32
/CS CKE
DQMB
DQ0
DQMB
DQ0
1
5
DQ7
DQ7
DQ7
DQ39
DQMB1
DQ8
DQMB5
DQ40
/CS CKE
/CS CKE
DQMB
DQ0
DQMB
DQ0
2
6
DQ7
DQ7
DQ15
DQ47
/CS CKE
/CS CKE
DQMB2
DQ16
DQMB6
DQ48
DQMB
DQ0
DQMB
DQ0
3
7
DQ23
DQ55
DQ7
DQ7
DQMB3
DQ24
DQMB7
DQ56
/CS CKE
/CS CKE
DQMB
DQ0
DQMB
DQ0
4
8
DQ31
DQ63
DQ7
DQ7
9
SDA
SCL
A0 A1 A2
1
5
2
6
3
4
8
CLK1
CLK0
7
Vcc
Vss
/RAS,/CAS,/WE
A0-A11,BA0,BA1
SDRAMs
1
8
0.22uF x8
Note. The Value of all resistors is 10Ω.
MODULE OUTLINE
59 61
60 62
1
2
143
144
(Front)
(Back)
Page 2/11
MK31VT864-10YE (98.09.03)
PIN CONFIGURATION
Front
Back side
Front side
Back side
Pin No. Pin name Pin No. Pin name
Pin No. Pin name Pin No. Pin name
1
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
Vss
DQMB0
DQMB1
Vcc
A0
A1
A2
Vss
DQ8
DQ9
DQ10
DQ11
Vcc
DQ12
DQ13
DQ14
DQ15
Vss
2
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
Vss
DQMB4
DQMB5
Vcc
A3
A4
A5
Vss
DQ40
DQ41
DQ42
DQ43
Vcc
DQ44
DQ45
DQ46
DQ47
Vss
N.C
N.C
CKE0
Vcc
/CAS
CKE1
N.C
73
N.C
74
CLK1
3
4
75
Vss
76
Vss
5
7
9
6
8
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
N.C
N.C
Vcc
78
80
82
84
86
88
90
92
N.C
N.C
Vcc
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DQ16
DQ17
DQ18
DQ19
Vss
DQ20
DQ21
DQ22
DQ23
Vcc
A6
A8
Vss
A9
DQ48
DQ49
DQ50
DQ51
Vss
DQ52
DQ53
DQ54
DQ55
Vcc
A7
BA0
Vss
BA1
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
A10
Vcc
A11
Vcc
DQMB2
DQMB3
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
SDA
Vcc
DQMB6
DQMB7
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
N.C
N.C
CLK0
Vcc
/RAS
/WE
/CS0
/CS1
SCL
Vcc
N.C
Pin Name
Function
Power Supply (3.3V)
Ground (0V)
Pin Name
/RAS
/CAS
/WE
Function
Vcc
Vss
Row Address Strobe
Column Address Strobe
Write Enable
CLK#
/CS#
System Clock
Chip Select
DQMB#
DQ#
Data Input / Output Mask
Data Input / Output
Data I/O for SPD
CKE#
A0-A11
Clock Enable
Address
SDA
BA0, BA1
Bank Select Address
SCL
CLK input for SPD
No Connection
N.C
Page 3/11
MK31VT864-10YE (98.09.03)
SERIAL PRESENCE DETECT
Byte
SPD
Remark
Notes
No.
Hex Value
Defines the number of bytes written into
SPD memory
0
80
128 byte
1
2
08
04
0C
Total number of bytes of SPD memory
Fundamental memory type
Number of rows
256 byte
SDRAM
12 rows
3
4
09
01
40
00
Number of columns
9 columns
1 bank
64 bits
0 bits
LVTTL
5
Number of module banks
Data width of this assembly
... Data width continuation
Voltage interface level
6
7
8
01
9
A0
90
00
80
08
00
01
0E
04
06
01
01
00
06
F0
90
00
00
1E
14
1E
3C
10
30
10
30
10
00-00
02
5A
Cycle time (CL=3)
CL=3 tCC=10ns
CL=3 tAC3=9ns
Non Parity
Normal / Self
x8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
Access time from CLK (CL=3)
DIMM configuration type
Refresh rate / type
Primary SDRAM width
Error checking SDRAM width
Minimum CLK delay
Burst lengths supported
Number of banks on each SDRAM
/CAS latency
/CS latency
/WE latency
SDRAM module attributes
SDRAM device attributes : General
Cycle time (CL=2)
Access time from CLK (CL=2)
Cycle time (CL=1)
Access time from CLK (CL=1)
Minimum ROW pulse width
/RAS to /RAS bank delay
/RAS to /CAS delay
Minimum /RAS precharge time
Density of each bank on module
Command and Address Signal Input Setup Time
Command and Address Signal Input Hold Time
tCCD: 1 CLK
2, 4, 8
4 banks
2,3
0
0
CL=2 tCC2=15ns
CL=2 tAC2=9ns
Not support
Not support
tRP=30ns
tRRD=20ns
tRCD=30ns
tRAS=60ns
64MB
3ns
1ns
3ns
1ns
Data Signal Input Setup Time
Data Signal Input Hold Time
R.F.U
0.2
SPD data revision code
Checksum for byte 0-62
Manufacturer’s JEDEC ID code
Manufacturing location
64-71
72
41,45,20,20,20,20,20,20
01 / 06
73-90 4D,4B,33,31,56,54,38,36,34, Manufacturer’s part number
2D,31,30,59,45,20,20,20,20
MK31VT864-10YE
91, 92
93-125
126
20, 20
XX-XX
66
06
FF-FF
Revision code
R.F.U
Intel specification frequency
Intel specification /CAS latency
Unused storage locations
66MHz
CL=2, 3
127
128-255
Page 4/11
MK31VT864-10YE (98.09.03)
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Rating
Voltage on any pin relative to Vss
Vcc supply voltage
Symbol
Value
Unit
V
VIN, VOUT
-0.5 to Vcc + 0.5
V
, V
cc cc
Q
-0.5 to 4.6
V
Storage temperature
Power dissipation
T
- 55 to 125
°C
W
stg
P
8
D*
Short circuit current
IOS
50
mA
°C
Operating temperature
T
0 to 70
opr
*: Ta=25
°C
Recommended Operating Conditions
(Voltages referenced to Vss = 0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power supply voltage
Input high voltage
Input low voltage
Vcc, VccQ
VIH
3.0
2.0
3.3
3.6
Vcc + 0.3
0.8
V
V
V
-
-
VIL
-0.3
Capacitance
(Vcc = 3.3V ± 0.3 V , Ta = 25°C f = 1MHz)
Parameter
Input capacitance(A0-A11, BA0, BA1)
Symbol
CIN1
Max.
40
Unit
pF
Input capacitance(/CS0, /RAS, /CAS, /WE, CKE0, DQMB0-7
I/O capacitance(DQ0 - DQ63 )
CIN2
40
pF
CI/O
56
pF
Page 5/11
MK31VT864-10YE (98.09.03)
DC CHARACTERISTICS
(Vcc = 3.3V ± 0.3V, Ta = 0 to 70°C)
Condition
Others
Module Spec.
Parameter
Symbol
Unit
Note
CKE
Min.
Max.
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
VOH
VOL
ILI
-
-
-
-
IOH = -2.0mA
IOL = 2.0mA
2.4
-
-80
-10
-
V
V
µA
µA
0.4
80
10
-
-
ILO
tCC=min.
Average Power Supply
Current
(Operating)
ICC1
CKE ≥ V
t
RC=min.
1, 2
3
-
-
-
920
320
120
mA
mA
mA
IH
IH
No Burst
Power Supply Current
(Stand by)
ICC
2
CKE ≥ V
tCC=min.
Average Power
Supply Current
(Clock Suspension)
Average Power
Supply Current
(Active Stand by)
Power Supply
Current (Burst)
Power Supply
Current
(Auto-Refresh)
Average Power
Supply Current
(Self-Refresh)
Average Power
Supply Current
(Power down)
ICC3S
CKE ≤ V
tCC=min.
tCC=min.
2
IL
,
CKE ≥ V
IH
ICC3
3
1, 2
2
-
-
-
640
1240
1480
mA
mA
mA
/CS ≥ V
IH
ICC
4
CKE ≥ V
tCC=min.
tCC=min.
IH
IH
ICC5
ICC6
ICC7
CKE ≥ V
t
RC=min.
tCC=min.
tCC=min.
CKE ≤ 0.2V
-
-
16
16
mA
mA
CKE ≤ V
IL
Notes: 1.
Measured with the output open.
2.
3.
Address and data can be changed once or not be changed during one cycle.
Address and data can be changed once or not be changed during two cycle.
MODE SET ADDRESS KEYS
/CAS Latency
A6 A5 A4 CL
Burst Type
Burst Length
A2 A1 A0 BT=0
Reserved Reserved
A3
BT
BT=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
0
1
Sequential
Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
8
2
4
8
3
Reserved
Reserved
Reserved
Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Note:
A7, A8, A9, A10, A11, BA0, BA1 should stay "L" during mode set cycle.
Page 6/11
MK31VT864-10YE (98.09.03)
POWER ON SEQUENCE
1. With inputs in NOP state, turn on the power supply and enter the system clock.
2. After the Vcc voltage has reached the specified level, take a pause of 200 s or more
µ
with the input being NOP.
3. Enter the precharge all bank command.
4. Apply CBR auto-refresh eight or more times.
5. Enter the mode register setting command.
Page 7/11
MK31VT864-10YE (98.09.03)
AC CHARACTERISTIC
(V = 3.3V ± 0.3V, Ta = 0 ~ 70°C)
cc
NOTE 1, 2
.
Parameter
Symbol
tCC
Module Spec.
Min. Max.
Unit Note
10
CL=3
CL=2
CL=3
CL=2
-
ns
ns
Clock Cycle Time
15
-
tAC
-
9
ns
ns
3, 4
3, 4
Access Time from Clock
-
9
tCH
tCL
3
Clock "H" Pulse Time
-
ns
3
Clock "L" Pulse Time
-
ns
tSI
3
Input Setup Time
-
ns
tHI
1
Input Hold Time
-
ns
tOLZ
tOHZ
tOH
3
Output Low Impedance Time from Clock
Output High Impedance Time from Clock
Output Hold from Clock
/RAS Cycle Time
-
ns
-
8
ns
3
-
ns
3
tRC
90
-
ns
tRP
30
/RAS Precharge Time
-
ns
tRAS
tRCD
tWR
tRRD
tREF
tPDE
tT
60
/RAS Active Time
1,000,000
ns
30
/RAS to /CAS Delay Time
Write Recovery Time
-
-
ns
15
ns
20
/RAS to /RAS Bank Active Delay Time
Refresh Time
-
ns
-
64
-
ms
ns
tSI+1CLK
-
Power-down Exit Set-up Time
Input Level Transition Time
/CAS to /CAS Delay Time (Min)
Clock Disable Time from CKE
3
ns
ICCD
ICKE
IDOZ
IDOD
IDWD
1
1
2
0
0
Cycle
Cycle
Cycle
Cycle
Cycle
Data Output High Impedance Time from UDQM, LDQM
Data Input Mask Time from DQMB
Data Input Time from Write Command
Data Output High Impedance Time from Precharge
Command.
Active Command Input Time from MODE
Register Set Command Input (Min)
IROH
IMRD
2
Cycle
3
2
Cycle
Cycle
IOWD
Write Command Input Time from Output
NOTES:
1) AC measurements assume tT=1ns.
2) The reference level for timing of input signals is 1.4V.
3) This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF
(RLoad is 50ohm).
4) An access time is measured at 1.4V.
5) If tT is longer than 1ns, the reference level for timing of input signals are VIH and VIL.
1.4v
50
Ω
OUTPUT
OUTPUT LOAD
50pF
Page 8/11
MK31VT864-10YE (98.09.03)
FUNCTION TRUTH TABLE (Table1) (1/2)
Current State
/CS
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
/RAS
X
H
H
H
L
/CAS
X
H
H
L
/WE BA
ADDR
X
Action
Idle
X
H
L
X
H
L
H
L
X
X
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
X
X
NOP
NOP
X
X
CA
RA
A10
X
BA
BA
BA
BA
X
L
X
X
BA
BA
BA
BA
X
ILLEGAL 2
ILLEGAL 2
Row Active
NOP 4
H
H
L
L
L
L
X
H
H
H
L
Auto-Refresh or Self-Refresh 5
L
OP Code Mode Register write
Row Active
X
H
L
X
X
NOP
NOP
CA, A10 Read
CA, A10 Write
L
H
H
L
X
H
H
L
RA
A10
X
X
X
ILLEGAL 2
Precharge
L
L
ILLEGAL
Read
X
H
H
H
H
L
X
X
NOP (Continue Row Active after Burst ends)
NOP (Continue Row Active after Burst ends)
Burst Stop
BA
BA
BA
BA
BA
X
X
CA, A10 Term Burst, start new Burst Read 3
CA, A10 Term Burst, start new Burst Write 3
L
H
H
L
X
H
H
L
RA
A10
X
X
X
ILLEGAL 2
L
L
Term Burst, execute Row Precharge
ILLEGAL
Write
X
H
H
H
H
L
X
X
NOP (Continue Row Active after Burst ends)
NOP (Continue Row Active after Burst ends)
Burst Stop
BA
BA
BA
BA
BA
X
X
CA, A10 Term Burst, start new Burst Read 3
CA, A10 Term Burst, start new Burst Write 3
L
H
H
L
X
H
H
L
L
H
L
X
H
H
L
L
H
L
RA
A10
X
X
X
ILLEGAL 2
L
L
Term Burst, execute Row Precharge 3
ILLEGAL
Read with
Auto Precharge
X
H
H
H
H
L
X
X
NOP (Continue Burst to End and enter Row Precharge)
NOP (Continue Burst to End and enter Row Precharge)
ILLEGAL 2
BA
BA
X
BA
X
X
H
L
CA, A10 ILLEGAL 2
X
ILLEGAL
X
X
X
H
L
H
L
X
X
RA, A10 ILLEGAL 2
L
X
X
X
X
ILLEGAL
Write with
Auto Precharge
X
H
H
H
H
L
X
X
NOP (Continue Burst to End and enter Row Precharge)
NOP (Continue Burst to End and enter Row Precharge)
ILLEGAL 2
BA
BA
X
BA
X
CA, A10 ILLEGAL 2
ILLEGAL
RA, A10 ILLEGAL 2
ILLEGAL
X
L
X
Page 9/11
MK31VT864-10YE (98.09.03)
FUNCTION TRUTH TABLE (Table1) (2/2)
Current State
/CS
H
L
/RAS
X
H
H
H
L
/CAS
X
H
H
L
/WE BA
ADDR
X
Action
Precharge
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
X
X
X
X
X
H
L
X
X
NOP Idle after t
RP
X
X
CA
RA
A10
X
X
X
X
CA
RA
A10
X
X
X
NOP Idle after t
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
NOP 4
ILLEGAL
NOP
NOP
RP
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
BA
BA
BA
BA
X
H
H
L
X
H
H
L
H
H
L
X
H
H
L
H
H
L
X
H
L
H
L
X
H
H
L
L
L
Write
Recovery
X
H
H
H
L
X
X
BA
BA
BA
BA
X
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
ILLEGAL
L
L
Row Active
X
H
H
H
L
L
L
X
H
H
L
X
X
NOP Row Active after t
NOP Row Active after t
ILLEGAL 2
RCD
RCD
BA
BA
BA
BA
X
X
X
X
X
X
X
X
X
X
CA
RA
A10
X
X
X
X
X
X
X
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
ILLEGAL
Refresh
NOP Idle after t
NOP Idle after t
ILLEGAL
ILLEGAL
ILLEGAL
NOP
NOP
ILLEGAL
RC
RC
L
Auto Resister
Access
X
H
H
H
L
X
X
L
L
L
X
X
X
X
X
X
ILLEGAL
ILLEGAL
X
ABBREVIATIONS
RA = Row Address
CA = Column Address
BA = Bank Address
AP = Auto Precharge
NOP = No Operation command
Notes:
1. All inputs will be enabled when CKE is set high for at least 1 cycle prior to the inputs.
2. Illegal to bank in specified state, but may be legal in some cases depending on the state of
bank selection.
3. Satisfy the timing of tCCD and tWR to prevent bus contention.
4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10.
5. Illegal if any bank is not idle.
Page 10/11
MK31VT864-10YE (98.09.03)
FUNCTION TRUTH TABLE (CKE) (Table2)
Current State(n) CKEn-1 CKEn
/CS
X
H
L
/RAS /CAS
/WE
X
X
H
L
ADDR
X
Action
INVALID
Exit Self Refresh ABI
Exit Self Refresh ABI
ILLEGAL
Self Refresh
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
X
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
X
X
H
H
H
L
X
X
X
H
H
H
X
X
X
X
H
H
H
L
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
L
H
L
L
X
X
X
X
X
X
X
X
L
L
L
X
X
H
L
L
L
X
X
X
X
X
H
L
X
X
X
X
X
X
X
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Power Down ABI
Exit Power Down ABI
ILLEGAL
Power Down
X
X
X
X
X
H
L
X
X
X
X
X
X
X
ILLEGAL
L
ILLEGAL 6
X
X
H
L
L
L
L
L
L
X
X
X
X
X
NOP (Continue power down mode)
Refer to Table 1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
ILLEGAL
Enter Self Refresh
ILLEGAL
NOP
All Banks idle 6
(ABI)
X
L
X
X
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Any State
Other than
Listed Above
H
H
L
H
L
H
L
Refer to Operations in Table 1
Begin Clock Suspend Next Cycle
Enable Clock of Next Cycle
Continue Clock Suspension
L
X
Notes:
6. Power-down and self refresh can be entered only when all the banks are in an idle state.
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