MK31VT864A [OKI]
8,388,608 Word x 64 Bit SYNCHRONOUS DYNAMIC RAM MODULE (1BANK); 8,388,608字×64位同步动态RAM模块（ 1BANK ）
| 型号： | MK31VT864A |
| 厂家： | 
OKI ELECTRONIC COMPONETS |
| 描述： | 8,388,608 Word x 64 Bit SYNCHRONOUS DYNAMIC RAM MODULE (1BANK) |
| 文件： | 总11页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MK31VT864A-8YC 98.07.17
Semiconductor
MK31VT864A-8YC
8,388,608 Word x 64 Bit SYNCHRONOUS DYNAMIC RAM MODULE (1BANK):
DESCRIPTION
The Oki MK31VT864A-8YC is a fully decoded, 8,388,608 x 64bit synchronous dynamic
random access memory composed of eight 64Mb DRAMs (8Mx8) in TSOP packages
mounted with decoupling capacitors on a 168-pin glass epoxy Dual-in-Line Package
supports any application where high density and large capacity of storage memory are
required, like for example PCs or servers.
FEATURES
•
•
•
•
•
•
•
•
8-Meg Word x 64-Bit (1Bank 8 Byte) organization
168-pin Dual Inline Memory Module
All DQ Pins have 10Ω Damping Resister
Single 3.3V power supply, ±0.3V tolerance
Input
:LVTTL compatible
Output :LVTTL compatible
Refresh : 4,096 cycles/64 ms
Programmable data transfer mode
(2, 3)
• /CAS latency
• Burst length (1, 2, 4, 8, Full page)
• Data scramble(sequential, interleave)
/CAS before /RAS auto-refresh, Self-refresh capability
Serial Presence Detect (SPD) With EEPROM
•
•
PRODUCT ORGANIZATION
Operation
Access Time (Max.)
Product Name
Frequency (Max.)
tAC2
tAC3
MK31VT864A - 8YC
125 MHz
10.0ns
6.0ns
Note. Specification are subject to change without notice.
Page 1/11
MK31VT864A-8YC 98.07.17
BLOCK DIAGRAM
CKE0
/CS0
DQMB0
/CS2
DQMB2
DQM /CS CKE
DQ0
DQM /CS CKE
DQ0
DQ16
DQ0
3
1
DQ23
DQ7
DQ7
DQ7
DQMB3
DQMB1
DQM /CS CKE
DQ0
DQM /CS CKE
DQ0
DQ24
DQ8
2
4
DQ7
DQ7
DQ31
DQ15
DQMB4
DQMB6
DQM /CS CKE
DQ0
DQM /CS CKE
DQ0
DQ32
DQ48
5
7
DQ39
DQ55
DQ7
DQ7
DQMB5
DQMB7
DQM /CS CKE
DQ0
DQM /CS CKE
DQ0
DQ40
DQ47
DQ56
DQ63
6
8
DQ7
DQ7
Serial PD
SDA
WP
9
SCL
A0 A1 A2
Ω
47K
SA0 SA1 SA2
1
2
5
6
3
4
7
8
CLK1
CLK3
CLK0
CLK2
10pF
3.3pF
3.3pF
Vcc
Vss
Two Decoupling Capacitors
per SDRAM
/RAS,/CAS,/WE
A0-A15 & BA0,BA1
8
1
0.1uF
0.33uF
Note. The Value of all resistors is 10Ω expect WP
MODULE OUTLINE
10 11
94 95
1
84
(Front)
(Back)
40 41
124 125
168
85
Page 2/11
MK31VT864A-8YC 98.07.17
PIN CONFIGURATION
Front side
Back side
Front side
Back side
Pin No. Pin name Pin No. Pin name
Pin No. Pin name Pin No. Pin name
1
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
N.C
85
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
N.C
N.C
VSS
N.C
N.C
VCC
/CAS
DQMB4
DQMB5
N.C
/RAS
VSS
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VSS
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
VSS
CKE0
N.C
DQMB6
DQMB7
N.C
VCC
N.C
N.C
N.C
N.C
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
N.C
2
86
N.C
3
4
5
6
7
8
9
87
88
89
90
91
92
93
94
95
96
97
98
/CS2
DQMB2
DQMB3
N.C
VCC
N.C
N.C
N.C
N.C
VSS
DQ16
DQ17
DQ18
DQ19
VCC
DQ20
N.C
N.C
N.C
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
N.C
N.C
VSS
N.C
VSS
N.C
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
N.C
VCC
/WE
DQMB0
DQMB1
/CS0
N.C
VSS
A0
A2
A4
A6
A8
A10
A1
A3
A5
A7
A9
BA0
A11
VCC
CLK1
N.C
CLK2
N.C
WP
SDA
SCL
CLK3
N.C
SA0
SA1
SA2
BA1
VCC
VCC
CLK0
VCC
VCC
Pin Name
Function
Pin Name
Function
VCC
VSS
CLK#
Power Supply (3.3V)
Ground (0V)
System Clock
/WE
DQMB#
DQ#
WP
Write Enable
Data Input / Output Mask
Data Input / Output
Write Protect
/CS#
Chip Select
CKE#
A0-A11
BA0, BA1
/RAS
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
SDA
SCL
SA#
Data I/O for SPD
CLK input for SPD
Socket Position Address for SPD
No Connection
N.C
/CAS
Page 3/11
MK31VT864A-8YC 98.07.17
SERIAL PRESENCE DETECT
Byte
SPD
Remark
Notes
No.
Hex Value
Defines the number of bytes written into
SPD memory
0
80
128 byte
1
2
08
04
0C
Total number of bytes of SPD memory
Fundamental memory type
Number of rows
256 byte
SDRAM
12 rows
3
4
09
01
40
00
Number of columns
9 columns
1 bank
64 bits
5
Number of module banks
Data width of this assembly
... Data width continuation
Voltage interface level
6
7
0
8
01
LVTTL
9
80
60
00
80
08
00
01
8F
04
06
01
01
00
0E
C0
A0
00
00
1E
10
14
30
10
20
10
20
10
00-00
12
49
Cycle time (CL=3)
CL=3 tCC3=8ns
CL=3 tAC3=6ns
None Parity
Normal / Self
x8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
72
Access time from CLK (CL=3)
DIMM configuration type
Refresh rate / type
Primary SDRAM width
Error checking SDRAM width
Minimum CLK delay
Burst lengths supported
Number of banks on each SDRAM
/CAS latency
/CS latency
/WE latency
SDRAM module attributes
SDRAM device attributes : General
Cycle time (CL=2)
Access time from CLK (CL=2)
Cycle time (CL=1)
Access time from CLK (CL=1)
Minimum ROW pulse width
/RAS to /RAS bank delay
/RAS to /CAS delay
Minimum /RAS precharge time
Density of each bank on module
Command and address signal input setup time
Command and address signal input hold time
tCCD: 1 CLK
1, 2, 4, 8, F
4 banks
2, 3
0
0
CL=2 tCC2=12ns
CL=2 tAC2=10ns
Not support
Not support
tRP=30ns
tRRD=16ns
tRCD=20ns
tRAS=48ns
64MB
2ns
1ns
2ns
1ns
Data signal input setup time
Data signal input hold time
R.F.U
1.2
SPD data revision code
Checksum for byte 0-62
Manufacturer’s JEDEC ID code
Manufacturing location
41,45,20,20,20,20,20,20
01 / 06
73-90 4D,4B,33,31,56,54,38,36,34, Manufacturer’s part number
41,2D,38,59,43,20,20,20,202
MK31VT864A-8YC
91, 92
93-125
126
20, 20
00-00
64
A5
FF-FF
Revision code
R.F.U
Intel specification frequency
Intel specification /CAS latency
Unused storage locations
100MHz
(CLK0-2, CL=3)
127
128-255
Page 4/11
MK31VT864A-8YC 98.07.17
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Rating
Voltage on any pin relative to Vss
Vcc supply voltage
Symbol
Value
Unit
V
VIN, VOUT
-0.5 to Vcc+0.5
-0.5 to 4.6
V
, V
cc cc
Q
V
Storage temperature
T
- 55 to 125
°C
stg
Power dissipation
PD
*
8
W
Short circuit current
IOS
50
mA
°C
Operating temperature
T
0 to 70
opr
*: Ta=25
°C
Recommended Operating Conditions
(Voltages referenced to Vss = 0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power supply voltage
Input high voltage
Input low voltage
Vcc, VccQ
VIH
3.0
2.0
3.3
3.6
Vcc+0.3
0.8
V
V
V
-
-
VIL
-0.3
Capacitance
(Vcc=3.3V ± 0.3V, Ta=25 °C f=1MHz)
Parameter
Symbol
CIN1
CIN2
Max.
54
34
Unit
pF
pF
pF
pF
pF
pF
Input capacitance (A0-A11, BA0, BA1, /RAS, /CAS, /WE)
Input capacitance (/CS0, /CS2)
Input capacitance (DQMB0-DQMB7)
Input capacitance (CKE0)
CIN3
16
CIN4
58
I/O capacitance (DQ0-DQ63)
CI/O
18
Input capacitance (CLK0, CLK2)
CCLK
50
Page 5/11
MK31VT864A-8YC 98.07.17
DC CHARACTERISTICS
(Vcc=3.3V ± 0.3V, Ta = 0 to 70 °C)
Condition
Others
IOH = -2.0mA
Module Spec.
Unit
Note
Parameter
Symbol
CKE
Min.
Max.
VOH
VOL
ILI
Output High Voltage
Output Low Voltage
Input Leakage Current
-
-
-
2.4
-
-
V
V
I
OL = 2.0mA
-
0.4
40
-40
µA
Output Leakage
Current
ILO
-
-
-5
5
µA
Average Power Supply
Current
(Operating)
tCC=min.
tRC=min.
No Burst
ICC
1
CKE ≥ V
1, 2
3
-
1000
240
48
mA
IH
IH
Power Supply Current
(Stand by)
ICC
2
CKE ≥ V
tCC=min.
-
-
mA
mA
Average Power
Supply Current
(Clock Suspension)
Average Power
Supply Current
(Active Stand by)
Power Supply
Current (Burst)
Power Supply
Current
(Auto-Refresh)
Average Power
Supply Current
(Self-Refresh)
Average Power
Supply Current
(Power down)
ICC
3S
CKE ≤ V
tCC=min.
2
IL
CKE ≥ V
/CS ≥ V
IH
,
ICC
3
tCC=min.
3
1, 2
2
-
-
-
480
1320
1480
mA
mA
mA
IH
ICC
4
CKE ≥ V
tCC=min.
tCC=min.
IH
IH
ICC
5
CKE ≥ V
t
RC=min.
ICC
6
tCC=min.
tCC=min.
CKE ≤ 0.2V
-
-
8
mA
mA
ICC
7
CKE ≤ V
16
IL
Notes: 1.
Measured with the output open.
2.
3.
Address and data can be changed once or not be changed during one cycle.
Address and data can be changed once or not be changed during two cycle.
MODE SET ADDRESS KEYS
Write Burst
Write Burst
Burst Write
Single bit Write
/CAS Latency
A6 A5 A4 CL
Burst Type
BT
Burst Length
A2 A1 A0 BT=0
Reserved Reserved
A9
0
1
A3
0
1
BT=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
Sequential
Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
8
2
4
8
3
Reserved
Reserved
Reserved
Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full page Reserved
Note:
A7, A8, A10, A11, BA0, BA1 and All should stay "L" during mode set cycle.
Page 6/11
MK31VT864A-8YC 98.07.17
POWER ON SEQUENCE
1. With inputs in NOP state, turn on the power supply and enter the system clock.
2. After the V voltage has reached the specified level, take a pause of 200 s or more
CC
µ
with the input being NOP.
3. Enter the precharge all bank command.
4. Apply CBR auto-refresh eight or more times.
5. Enter the mode register setting command.
Page 7/11
MK31VT864A-8YC 98.07.17
AC CHARACTERISTIC
(
)
Vcc=3.3V ± 0.3V, Ta = 0 to 70 °C
NOTE 1, 2
.
Module Spec.
Unit Note
Parameter
Symbol
Min.
Max.
Clock Cycle Time
CL=3
8
12
-
-
ns
ns
t
CC
CL=2
CL=3
CL=2
-
Access Time from Clock
6
ns
3, 4
3, 4
t
AC
-
10
ns
Clock "H" Pulse Time
Clock "L" Pulse Time
Input Setup Time
Input Hold Time
3
-
ns
t
CH
3
-
ns
t
CL
2
-
ns
t
SI
HI
1
-
ns
t
Output Low Impedance Time from Clock
Output High Impedance Time from Clock
Output Hold from Clock
3
-
ns
t
OLZ
OHZ
-
8
ns
t
3
-
ns
3
t
OH
/RAS Cycle Time
80
30
48
20
8
-
ns
t
RC
/RAS Precharge Time
-
ns
t
RP
/RAS Active Time
100,000
ns
t
RAS
RCD
/RAS to /CAS Delay Time
Write Recovery Time
-
-
ns
t
ns
t
WR
/RAS to /RAS Bank Active Delay Time
Refresh Time
16
-
-
ns
t
RRD
64
-
ms
ns
t
REF
PDE
Power-down Exit Set-up Time
Input Level Transition Time
/CAS to /CAS Delay Time (Min)
Clock Disable Time from CKE
Data Output High Impedance Time from
t
t +1CLK
SI
-
3
ns
t
T
1
1
2
Cycle
Cycle
Cycle
I
CCD
I
CKE
I
DOZ
Data Input Mask Time from DQMB
0
0
3
2
2
2
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
I
DOD
Data Input Time from Write Command
I
DWD
Data Output High Inpedance
CL=3
CL=2
I
ROH
Time from Precharge Command
Active Command Input Time from MODE
Write Command Input Time from Output
I
MRD
t
OWD
NOTES:
1) AC measurements assume tT=1ns.
2) The reference level for timing of input signals is 1.4V.
3) This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF
(RLoad is 50ohm).
4) An access time is measured at 1.4V.
5) If tT is longer than 1ns, the reference level for timing of input signals are VIH and VIL.
50Ω
OUTPUT LOAD
Page 8/11
MK31VT864A-8YC 98.07.17
FUNCTION TRUTH TABLE (Table1)(1/2)
Current State
/CS
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
/RAS
X
H
H
H
L
/CAS
X
H
H
L
/WE BA
ADDR
X
Action
Idle
X
H
L
X
H
L
H
L
X
X
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
X
X
NOP
NOP
X
X
CA
RA
A10
X
BA
BA
BA
BA
X
L
X
X
BA
BA
BA
BA
X
ILLEGAL 2
ILLEGAL 2
Row Active
NOP 4
H
H
L
L
L
L
X
H
H
H
L
Auto-Refresh or Self-Refresh 5
L
OP Code Mode Register write
Row Active
X
H
L
X
X
NOP
NOP
CA, A10 Read
CA, A10 Write
L
H
H
L
X
H
H
L
RA
A10
X
X
X
ILLEGAL 2
Precharge
L
L
ILLEGAL
Read
X
H
H
H
H
L
X
X
NOP (Continue Row Active after Burst ends)
NOP (Continue Row Active after Burst ends)
Burst Stop
BA
BA
BA
BA
BA
X
X
CA, A10 Term Burst, start new Burst Read 3
CA, A10 Term Burst, start new Burst Write 3
L
H
H
L
X
H
H
L
RA
A10
X
X
X
ILLEGAL 2
L
L
Term Burst, execute Row Precharge
ILLEGAL
Write
X
H
H
H
H
L
X
X
NOP (Continue Row Active after Burst ends)
NOP (Continue Row Active after Burst ends)
Burst Stop
BA
BA
BA
BA
BA
X
X
CA, A10 Term Burst, start new Burst Read 3
CA, A10 Term Burst, start new Burst Write 3
L
H
H
L
X
H
H
L
L
H
L
X
H
H
L
L
H
L
RA
A10
X
X
X
ILLEGAL 2
L
L
Term Burst, execute Row Precharge 3
ILLEGAL
NOP (Continue Burst to End and enter Row Precharge)
Read with
Auto Precharge
X
H
H
H
H
L
X
X
NOP (Continue Burst to End and enter Row Precharge)
BA
BA
X
BA
X
X
ILLEGAL 2
H
L
CA, A10 ILLEGAL 2
X
ILLEGAL
X
X
X
H
L
H
L
X
X
RA, A10 ILLEGAL 2
L
X
X
X
X
ILLEGAL
NOP (Continue Burst to End and enter Row Precharge)
Write with
Auto Precharge
X
H
H
H
H
L
X
X
NOP (Continue Burst to End and enter Row Precharge)
BA
BA
X
BA
X
ILLEGAL 2
CA, A10 ILLEGAL 2
X
ILLEGAL
RA, A10 ILLEGAL 2
ILLEGAL
L
X
Page 9/11
MK31VT864A-8YC 98.07.17
FUNCTION TRUTH TABLE (Table1)(2/2)
Current State
/CS
H
L
/RAS
X
H
H
H
L
/CAS
X
H
H
L
/WE BA
ADDR
X
Action
Precharge
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
X
X
X
X
X
H
L
X
X
NOP Idle after t
RP
X
X
CA
RA
A10
X
X
X
X
CA
RA
A10
X
X
X
NOP Idle after t
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
NOP 4
ILLEGAL
NOP
NOP
RP
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
BA
BA
BA
BA
X
H
H
L
X
H
H
L
H
H
L
X
H
H
L
H
H
L
X
H
L
H
L
X
H
H
L
L
L
Write
Recovery
X
H
H
H
L
X
X
BA
BA
BA
BA
X
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
ILLEGAL
L
L
Row Active
X
H
H
H
L
L
L
X
H
H
L
X
X
NOP Row Active after t
NOP Row Active after t
ILLEGAL 2
RCD
RCD
BA
BA
BA
BA
X
X
X
X
X
X
X
X
X
X
CA
RA
A10
X
X
X
X
X
X
X
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
ILLEGAL
Refresh
NOP Idle after t
NOP Idle after t
ILLEGAL
ILLEGAL
ILLEGAL
NOP
NOP
ILLEGAL
RC
RC
L
Auto Resister
Access
X
H
H
H
L
X
X
L
L
L
X
X
X
X
X
X
ILLEGAL
ILLEGAL
X
ABBREVIATIONS
RA = Row Address
CA = Column Address
BA = Bank Address
AP = Auto Precharge
NOP = No Operation command
Notes:
1. All inputs will be enabled when CKE is set high for at least 1 cycle prior to the inputs.
2. Illegal to bank in specified state, but may be legal in some cases depending on the state of
bank selection.
3. Satisfy the timing of I
and t
to prevent bus contention.
CCD
WR
4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10.
5. Illegal if any bank is not idle.
Page 10/11
MK31VT864A-8YC 98.07.17
FUNCTION TRUTH TABLE (CKE) (Table2)
Current State(n) CKEn-1 CKEn
/CS
X
H
L
/RAS /CAS
/WE
X
X
H
L
ADDR
X
Action
INVALID
Exit Self Refresh ABI
Exit Self Refresh ABI
ILLEGAL
Self Refresh
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
X
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
X
X
H
H
H
L
X
X
X
H
H
H
X
X
X
X
H
H
H
L
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
L
H
L
L
X
X
X
X
X
X
X
X
L
L
L
X
X
H
L
L
L
X
X
X
X
X
H
L
X
X
X
X
X
X
X
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Power Down ABI
Exit Power Down ABI
ILLEGAL
Power Down
X
X
X
X
X
H
L
X
X
X
X
X
X
X
ILLEGAL
L
ILLEGAL 6
X
X
H
L
L
L
L
L
L
X
X
X
X
X
NOP (Continue power down mode)
Refer to Table 1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
ILLEGAL
Enter Self Refresh
ILLEGAL
NOP
All Banks idle 6
(ABI)
X
L
X
X
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Any State
Other than
Listed Above
H
H
L
H
L
H
L
Refer to Operations in Table 1
Begin Clock Suspend Next Cycle
Enable Clock of Next Cycle
Continue Clock Suspension
L
X
Notes:
6. Power-down and self refresh can be entered only when all the banks are in an idle state.
Page 11/11
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