MK31VT872A-8YC [OKI]
8,388,608 Word x 72 Bit SYNCHRONOUS DYNAMIC RAM MODULE (1BANK); 8388608字X 72位同步动态RAM模块( 1BANK )型号: | MK31VT872A-8YC |
厂家: | OKI ELECTRONIC COMPONETS |
描述: | 8,388,608 Word x 72 Bit SYNCHRONOUS DYNAMIC RAM MODULE (1BANK) |
文件: | 总11页 (文件大小:106K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MK31VT872A-8YC 98.06.26
Semiconductor
MK31VT872A-8YC
8,388,608 Word x 72 Bit SYNCHRONOUS DYNAMIC RAM MODULE (1BANK):
DESCRIPTION
The Oki MK31VT872A-8YC is a fully decoded, 8,388,608 x 72bit synchronous dynamic
random access memory composed of eight 64Mb DRAMs(8Mx9) in TSOP packages
mounted with decoupling capacitors on a 168-pin glass epoxy Dual-in-Line Package
supports any application where high density and large capacity of storage memory are
required, like for example PCs or servers.
FEATURES
•
•
•
•
•
•
•
•
8-Meg Word x 72-Bit (1Bank 8 Byte) organization
168-pin Dual Inline Memory Module
All DQ Pins have 10Ω Damping Resister
Single 3.3V power supply, ±0.3V tolerance
Input
:LVTTL compatible
Output :LVTTL compatible
Refresh : 4,096 cycles/64 ms
Programmable data transfer mode
(2, 3)
• /CAS latency
• Burst length(1,2,4,8,Full page)
• Data scramble(sequential,interleave)
/CAS before /RAS auto-refresh, Self-refresh capability
Serial Presence Detect (SPD) With EEPROM
•
•
PRODUCT ORGANIZATION
Operation
Access Time(Max.)
Product Name
Frequency(Max.)
tAC2
tAC3
MK31VT872A - 8YC
125 MHz
10.0ns
6.0ns
MK31VT872A-8YC 98.06.26
BLOCK DIAGRAM
CKE0
/CS0
DQMB0
/CS2
DQMB2
DQM /CS CKE
DQ0
DQM /CS CKE
DQ0
DQ16
DQ0
6
1
DQ23
DQ7
DQ7
DQ7
DQMB3
DQMB1
DQM /CS CKE
DQ0
DQM /CS CKE
DQ0
DQ24
DQ8
2
7
DQ7
DQ7
DQ31
DQ15
DQMB4
DQMB6
DQM /CS CKE
DQ0
DQM /CS CKE
DQ0
DQ48
DQ32
3
8
DQ7
DQ39
DQ55
DQ7
DQMB5
DQMB7
DQM /CS CKE
DQ0
DQM /CS CKE
DQ0
DQ56
DQ63
DQ40
4
9
DQ7
DQ7
DQ47
DQMB1
Serial PD
DQM /CS CKE
DQ0
SDA
WP
CB0
CB7
10
A0 A1 A2
SCL
5
DQ7
Ω
47K
SA0 SA1 SA2
1
2
3
4
5
3
4
CLK1
CLK3
CLK2
CLK0
7
8
10pF
3.3pF
Vcc
Vss
Two Decoupling Capacitors
per SDRAM
/RAS,/CAS,/WE
A0-A15 & BA0,BA1
9
1
0.1uF
0.33uF
Note. The Value of all resistors is 10Ω expect WP
MODULE OUTLINE
10 11
94 95
1
84
(Front)
(Back)
40 41
124 125
168
85
MK31VT872A-8YC 98.06.26
PIN CONFIGURATION
Front side
Back side
Front side
Back side
Pin No. Pin name Pin No. Pin name
Pin No. Pin name Pin No. Pin name
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
CB0
CB1
VSS
N.C
85
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
CB4
CB5
VSS
N.C
N.C
VCC
/CAS
DQMB4
DQMB5
N.C
/RAS
VSS
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VSS
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
VSS
CKE0
N.C
DQMB6
DQMB7
N.C
VCC
N.C
N.C
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
N.C
2
3
4
5
6
7
8
9
86
N.C
87
88
89
90
91
92
93
94
95
96
97
98
/CS2
DQMB2
DQMB3
N.C
VCC
N.C
N.C
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VCC
DQ20
N.C
N.C
N.C
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
N.C
N.C
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
N.C
VCC
/WE
DQMB0
DQMB1
/CS0
N.C
VSS
A0
A2
A4
A6
A8
A10
A1
A3
A5
A7
A9
BA0
A11
VCC
CLK1
N.C
CLK2
N.C
WP
SDA
SCL
CLK3
N.C
SA0
SA1
SA2
BA1
VCC
VCC
CLK0
VCC
VCC
Pin Name
Function
Pin Name
Function
VCC
VSS
CLK#
/CS#
Power Supply (3.3V)
Ground (0V)
System Clock
/WE
DQMB#
DQ# , CB#
WP
Write Enable
Data Input / Output Mask
Data Input / Output
Write Protect
Chip Select
CKE#
A0-A11
BA0,BA1
/RAS
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
SDA
SCL
SA#
N.C
Data I/O for SPD
CLK input for SPD
Socket Position Address for SPD
No Connection
/CAS
MK31VT872A-8YC 98.06.26
SERIAL PRESENCE DETECT
Byte
SPD
Remark
Notes
No.
Hex Value
Defines the number of bytes written into
SPD memory
0
80
128 byte
1
2
08
04
0C
09
01
48
00
01
80
60
02
80
08
08
01
8F
04
06
01
01
00
0E
C0
A0
00
00
1E
10
14
30
10
20
Total number of bytes of SPD memory
Fundamental memory type
Number of rows
256 byte
SDRAM
12 rows
9 columns
1 bank
3
4
Number of columns
5
Number of module banks
Data width of this assembly
... Data width continuation
Voltage interface level
6
72 bits
0
7
8
LVTTL
CL=3 tCC=8ns
CL=3 tAC3=6ns
ECC
Normal/ Self/
x8
9
Cycle time (CL=3)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
72
Access time from CLK (CL=3)
DIMM configuration type
Refresh rate / type
Primary SDRAM width
Error checking SDRAM width
Minimum CLK delay
Burst lengths supported
Number of banks on each SDRAM
/CAS latency
/CS latency
/WE latency
SDRAM module attributes
SDRAM device attributes : General
Cycle time (CL=2)
Access time from CLK (CL=2)
Cycle time (CL=1)
Access time from CLK (CL=1)
Minimum ROW pulse width
/RAS to /RAS bank delay
/RAS to /CAS delay
Minimum /RAS precharge time
Density of each bank on module
Command and address signal input setup time
Command and address signal input hold time
x8
tCCD: 1 CLK
1,2,4,8,F
4 banks
2,3
0
0
CL=2 tCC2=12ns
CL=2 tAC2=10ns
Not support
Not support
tRP=30ns
tRRD=16ns
tRCD=20ns
tRAS=48ns
64MB
2ns
1ns
2ns
1ns
10
20
10
00-00
Data signal input setup time
Data signal input hold time
R.F.U
1.2
12
SPD data revision code
Checksum for byte 0-62
Manufacturer’s JEDEC ID code
Manufacturing location
5B
41,45,20,20,20,20,20,20
01/06
73-90 4D,4B,33,31,56,54,38,37,32, Manufacturer’s part number
41,2D,38,59,43,20,20,20,202
MK31VT872A-8YC
91,92
93-125
126
20,20
00-00
64
A5
FF-FF
Revision code
R.F.U
Intel specification frequency
Intel specification /CAS latency
Unused storage locations
100MHz
(CLK0-2,CL=3)
127
128-255
MK31VT872A-8YC 98.06.26
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
, V
-0.5 to VCC+0.5
V
IN OUT
Vcc supply voltage
Storage temperature
Vcc,VccQ
-0.5 to 4.6
V
T
- 55 to 125
°C
stg
Power dissipation
P
9
W
D*
Short circuit current
Ios
50
mA
°C
Operating temperature
T
0 to 70
opr
*: Ta=25
°C
Recommended Operating Conditions
(Voltages referenced to Vss = 0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power supply voltage
Input high voltage
Input low voltage
Vcc,VccQ
VIH
3.0
2.0
3.3
3.6
VCC+0.3
0.8
V
V
V
-
-
VIL
-0.3
Capacitance
(Vcc=3.3V ± 0.3V,Ta=25 °C f=1MHz)
Parameter
Symbol
CIN1
CIN2
Max.
54
34
Unit
pF
pF
pF
pF
pF
pF
Input capacitance(A0-A11,BA0,BA1,/RAS, /CAS,/WE)
Input capacitance(/CS0,/CS2)
Input capacitance(DQMB0-DQMB7)
Input capacitance(CKE0)
CIN3
16
CIN4
58
I/O
C
I/O capacitance(DQ0-DQ63,CB0 - CB7)
Input capacitance(CLK0,CLK2)
18
CLK
C
50
MK31VT872A-8YC 98.06.26
DC CHARACTERISTICS
(Vcc=3.3V ± 0.3V,Ta = 0 to 70 °C)
Parameter
Symbol
Condition
Others
Module Spec.
Unit
Note
CKE
Min. Max.
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
V
I
= -2.0mA
2.4
-
-
-
-
-
V
V
uA
uA
OH
OH
V
I
= 2.0mA
-
0.4
40
5
OL
OL
I
-
-
-40
-5
LI
I
LO
t
t
=min.
=min.
Average Power Supply
Current
CC
RC
I
CKE≥V
CKE≥V
1,2
CC1
-
-
-
1125
320
54
mA
mA
IH
(Operating)
Power Supply Current
(Stand by)
Average Power
Supply Current
No Burst
t =min.
CC
I
3
2
CC2
IH
tCC=min.
I
CC3S
CKE≤V
CKE≥V
mA
mA
IL
(Clock Suspension)
Average Power
Supply Current
I
IH,
CC3
t
t
=min.
=min.
3
CC
CC
/CS≥V
IH
540
1485
1665
-
-
-
(Active Stand by)
Power Supply
Current (Burst)
I
I
CKE≥V
CKE≥V
mA
mA
CC4
CC5
IH
1,2
2
Power Supply
Current
t
t
t
=min.
=min.
=min.
CC
RC
CC
IH
(Auto-Refresh)
Average Power
Supply Current
CKE≤0.2V
I
I
CC6
CC7
mA
mA
-
-
9
(Self-Refresh)
Average Power
Supply Current
t
=min.
CC
CKE
V
IL
18
(Power down)
Notes: 1.
Measured with the output open.
2.
3.
Address and data can be changed once or not be changed during one cycle.
Address and data can be changed once or not be changed during two cycle.
MODE SET ADDRESS KEYS
Write Burst
Write Burst
Burst Write
Single bit Write
/CAS Latency
A6 A5 A4 CL
Burst Type
BT
Burst Length
A2 A1 A0 BT=0
Reserved Reserved
A9
0
1
A3
0
1
BT=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
Sequential
Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
8
2
4
8
3
Reserved
Reserved
Reserved
Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full page Reserved
Note:
A7,A8, A10,A11,BA0,BA1 and All should stay "L" during mode set cycle.
MK31VT872A-8YC 98.06.26
POWER ON SEQUENCE
1. With inputs in NOP state, turn on the power supply and enter the system clock.
2. After the V voltage has reached the specified level, take a pause of 200us or more
CC
with the input being NOP.
3. Enter the precharge all bank command.
4. Apply CBR auto-refresh eight or more times.
5. Enter the mode register setting command.
MK31VT872A-8YC 98.06.26
AC CHARACTERISTIC
(
)
Vcc=3.3V ± 0.3V,Ta = 0 to 70 °C
NOTE 1,2
.
Parameter
Symbol
tCC
Module Spec.
Unit Note
Min.
Max.
Clock Cycle Time
CL=3
8
-
ns
ns
CL=2
CL=3
CL=2
12
-
Access Time from Clock
tAC
-
6
ns
3,4
3,4
-
10
ns
Clock "H" Pulse Time
Clock "L" Pulse Time
Input Setup Time
Input Hold Time
tCH
tCL
3
-
ns
3
-
ns
tSI
2
-
ns
tHI
1
-
ns
Output Low Impedance Time from Clock
Output High Impedance Time from Clock
Output Hold from Clock
tOLZ
tOHZ
tOH
3
-
ns
-
8
ns
3
-
ns
3
/RAS Cycle Time
tRC
80
-
ns
/RAS Precharge Time
tRP
30
-
ns
/RAS Active Time
tRAS
tRCD
tWR
tRRD
tREF
tPDE
tT
48
100,000
ns
/RAS to /CAS Delay Time
20
-
-
ns
Write Recovery Time
8
ns
/RAS to /RAS Bank Active Delay Time
Refresh Time
16
-
ns
-
64
-
ms
Power-down Exit Set-up Time
Input Level Transition Time
/CAS to /CAS Delay Time (Min)
Clock Disable Time from CKE
Data Output High Impedance Time from
Data Input Mask Time from DQMB
Data Input Time from Write Command
tSI+1CLK
-
ns
3
ns
ICCD
ICKE
IDOZ
IDOD
IDWD
IROH
1
1
2
0
0
3
2
2
2
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Data Output High Inpedance
CL=3
CL=2
Time from Precharge Command
Active Command Input Time from MODE
Write Command Input Time from Output
IMRD
tOWD
NOTES:
1) AC measurements assume tT=1ns.
2) The reference level for timing of input signals is 1.4V.
3) This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF
(R Load is 50ohm).
4) An access time is measured at 1.4V.
5)
If tT is longer than 1ns, the reference level for timing of input signals are VIH and VIL.
50Ω
OUTPUT LOAD
MK31VT872A-8YC 98.06.26
FUNCTION TRUTH TABLE (Table1)(1/2)
Current State
/CS
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
/RAS
X
H
H
H
L
/CAS
X
H
H
L
/WE BA
ADDR
X
Action
Idle
X
H
L
X
H
L
H
L
X
X
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
X
X
NOP
NOP
X
X
CA
RA
A10
X
BA
BA
BA
BA
X
L
X
X
BA
BA
BA
BA
X
ILLEGAL 2
ILLEGAL 2
Row Active
NOP 4
H
H
L
L
L
L
X
H
H
H
L
Auto-Refresh or Self-Refresh 5
L
OP Code Mode Register write
Row Active
X
H
L
X
X
NOP
NOP
Read
CA,A10
CA,A10
RA
A10
L
Write
H
H
L
X
H
H
L
ILLEGAL 2
L
L
Precharge
ILLEGAL
X
X
X
X
Read
X
H
H
H
H
L
X
X
NOP(Continue Row Active after Burst ends)
NOP(Continue Row Active after Burst ends)
Burst Stop
BA
BA
BA
BA
BA
X
CA,A10
CA,A10
RA
A10
Term Burst,start new Burst Read 3
Term Burst,start new Burst Write 3
ILLEGAL 2
L
H
H
L
X
H
H
L
L
L
Term Burst,execute Row Precharge
ILLEGAL
X
X
X
X
Write
X
H
H
H
H
L
X
X
NOP(Continue Row Active after Burst ends)
NOP(Continue Row Active after Burst ends)
Burst Stop
BA
BA
BA
BA
BA
X
CA,A10
CA,A10
RA
A10
Term Burst,start new Burst Read 3
Term Burst,start new Burst Write 3
ILLEGAL 2
L
H
H
L
X
H
H
L
L
H
L
X
H
H
L
L
H
L
L
L
Term Burst,execute Row Precharge 3
ILLEGAL
X
X
X
X
NOP(Continue Burst to End and enter Row Precharge)
Read with
Auto Precharge
X
H
H
H
H
L
X
X
NOP(Continue Burst to End and enter Row Precharge)
BA
BA
X
BA
X
ILLEGAL 2
H
L
CA,A10
ILLEGAL 2
X
ILLEGAL
X
X
X
H
L
H
L
X
X
RA,A10
ILLEGAL 2
L
X
X
X
ILLEGAL
NOP(Continue Burst to End and enter Row Precharge)
Write with
Auto Precharge
X
H
H
H
H
L
X
X
NOP(Continue Burst to End and enter Row Precharge)
BA
BA
X
BA
X
X
CA,A10
X
RA,A10
X
ILLEGAL 2
ILLEGAL 2
ILLEGAL
ILLEGAL 2
ILLEGAL
L
MK31VT872A-8YC 98.06.26
FUNCTION TRUTH TABLE (Table1)(2/2)
Current State
/CS
H
L
/RAS
X
H
H
H
L
/CAS
X
H
H
L
/WE BA
ADDR
X
Action
Precharge
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
X
X
X
X
X
H
L
X
X
NOP Idle after tRP
X
X
CA
RA
A10
X
X
X
X
CA
RA
A10
X
X
X
NOP Idle after tRP
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
NOP 4
ILLEGAL
NOP
NOP
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
BA
BA
BA
BA
X
H
H
L
X
H
H
L
H
H
L
X
H
H
L
H
H
L
X
H
L
H
L
X
H
H
L
L
L
Write
Recovery
X
H
H
H
L
X
X
BA
BA
BA
BA
X
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
ILLEGAL
NOP Row Active after tRCD
NOP Row Active after tRCD
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
ILLEGAL 2
ILLEGAL
NOP Idle after tRC
NOP Idle after tRC
ILLEGAL
L
L
Row Active
X
H
H
H
L
L
L
X
H
H
L
X
X
BA
BA
BA
BA
X
X
X
X
X
X
X
X
X
X
CA
RA
A10
X
X
X
X
X
X
X
Refresh
ILLEGAL
ILLEGAL
NOP
NOP
L
Auto Resister
Access
X
H
H
H
L
X
X
L
ILLEGAL
L
L
X
X
X
X
X
X
ILLEGAL
ILLEGAL
X
ABBREVIATIONS
RA = Row Address
CA = Column Address
BA = Bank Address
AP = Auto Precharge
NOP = No Operation command
Notes:
1. All inputs will be enabled when CKE is set high for at least 1 cycle prior to the inputs.
2. Illegal to bank in specified state, but may be legal in some cases depending on the state of
bank selection.
3. Satisfy the timing of ICCD and tWR to prevent bus contention.
4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10.
5. Illegal if any bank is not idle.
MK31VT872A-8YC 98.06.26
FUNCTION TRUTH TABLE (CKE) (Table2)
Current State(n) CKEn-1 CKEn
/CS
X
H
L
/RAS /CAS
/WE
X
X
H
L
ADDR
X
Action
INVALID
Exit Self Refresh ABI
Exit Self Refresh ABI
ILLEGAL
Self Refresh
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
X
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
X
X
H
H
H
L
X
X
X
H
H
H
X
X
X
X
H
H
H
L
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
L
H
L
L
X
X
X
X
X
X
X
X
L
L
L
X
X
H
L
L
L
X
X
X
X
X
H
L
X
X
X
X
X
X
X
ILLEGAL
ILLEGAL
NOP(Maintain Self Refresh)
INVALID
Exit Power Down ABI
Exit Power Down ABI
ILLEGAL
Power Down
X
X
X
X
X
H
L
X
X
X
X
X
X
X
ILLEGAL
L
ILLEGAL 6
X
X
H
L
L
L
L
L
L
X
X
X
X
X
NOP(Continue power down mode)
Refer to Table 1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
ILLEGAL
Enter Self Refresh
ILLEGAL
NOP
All Banks idle 6
(ABI)
X
L
X
X
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Any State
Other than
Listed Above
H
H
L
H
L
H
L
Refer to Operations in Table 1
Begin Clock Suspend Next Cycle
Enable Clock of Next Cycle
Continue Clock Suspension
L
X
Notes:
6. Power-down and self refresh can be entered only when all the banks are in an idle state.
相关型号:
©2020 ICPDF网 联系我们和版权申明