TJA1022TK,118 [NXP]
TJA1022 - Dual LIN 2.2A/SAE J2602 transceiver SON 14-Pin;
| 型号： | TJA1022TK,118 |
| 厂家： | 
NXP |
| 描述： | TJA1022 - Dual LIN 2.2A/SAE J2602 transceiver SON 14-Pin |
| 文件： | 总26页 (文件大小：612K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TJA1022
Dual LIN 2.2A/SAE J2602 transceiver
Rev. 2 — 24 April 2013
Product data sheet
1. General description
The TJA1022 is a dual LIN transceiver that provides the interface between a Local
Interconnect Network (LIN) master/slave protocol controller and the physical bus in a LIN
network. It is primarily intended for in-vehicle subnetworks using baud rates up to 20 kBd
and is compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and SAE J2602. The TJA1022 is
pin compatible with the TJA1020, TJA1021 and TJA1027 (see Section 18). The TJA1022
and TJA1027 are also software compatible.
The transmit data streams generated by the protocol controller are converted by the
TJA1022 into optimized bus signals shaped to minimize ElectroMagnetic Emissions
(EME). The LIN bus output pins are pulled HIGH via internal termination resistors. For a
master application, an external resistor in series with a diode should be connected
between pin VBAT and each of the LIN pins. The receivers detect receive data streams on
the LIN bus input pins and transfer them via pins RXD1 and RXD2 to the microcontroller.
Power consumption is very low when both transceivers are in Sleep mode. However, the
TJA1022 can still be woken up via pins LIN1/LIN2 and SLP1_N/SLP2_N.
2. Features and benefits
2.1 General
Two LIN transceivers in a single package
LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and SAE J2602 compliant
Baud rate up to 20 kBd
Very low ElectroMagnetic Emissions (EME)
Very low current consumption in Sleep mode with remote LIN wake-up
Input levels compatible with 3.3 V and 5 V devices
Integrated termination resistors for LIN slave applications
Passive behavior in unpowered state
Operational during cranking pulse: full operation from 5 V upwards
Undervoltage detection
K-line compatible
Available in SO14 and HVSON14 packages
Leadless HVSON14 package (3.0 mm 4.5 mm) with improved Automated Optical
Inspection (AOI) capability
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
Pin-compatible with the TJA1020, TJA1021 and TJA1027 (see Section 18)
Software-compatible with the TJA1027
TJA1022
NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
2.2 Protection
Very high ElectroMagnetic Immunity (EMI)
Very high ESD robustness: 8 kV according to IEC 61000-4-2 for pins LIN1, LIN2 and
VBAT
Bus terminal and battery pin protected against transients in the automotive
environment (ISO 7637)
Bus terminal short-circuit proof to battery and ground
Thermally protected
Initial TXD dominant check when switching to Normal mode
TXD dominant time-out function
3. Quick reference data
Table 1.
Symbol Parameter
VBAT battery supply voltage
Quick reference data
Conditions
Min
0.3
5
Typ
Max Unit
limiting values
operating range
-
+42
18
V
-
V
IBAT
battery supply current
Sleep mode (both channels); bus recessive (both 2.5
channels); VLINx = VBAT; VSLPx_N = 0 V
7
10
A
Standby mode (both channels); bus recessive
(both channels); VLINx = VBAT; VSLPx_N = 0 V
2.5
7
10
A
Normal mode (both channels); bus recessive
300
1600 3200 A
(both channels); VTXDx = 5 V; VLINx = VBAT
VSLPx_N = 5 V
;
VLIN
VESD
Tvj
voltage on pin LIN
pins LIN1 and LIN2; limiting value; with respect
to GND and VBAT
42
8
-
-
-
+42
+8
V
electrostatic discharge voltage on pins LIN1, LIN2 and VBAT; according to IEC
61000-4-2
kV
virtual junction temperature
40
+150 C
4. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TJA1022T
SO14
plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
TJA1022TK
HVSON14 plastic, thermal enhanced very thin small outline package; no leads;
SOT1086-2
14 terminals; body 3 4.5 0.85 mm
TJA1022
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 24 April 2013
2 of 26
TJA1022
NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
5. Block diagram
TJA1022
POWER-ON RESET AND
10
13
V
BAT
UNDERVOLTAGE DETECTION
1
RXD1
BUS
TIMER
LIN1
2
SLP1_N
3
DOM
TIMER
TXD1
TEMPERATURE
PROTECTION
V
BAT
CONTROL
4
RXD2
BUS
TIMER
5
9
8
SLP2_N
LIN2
GND
7
DOM
TIMER
TXD2
015aaa288
Fig 1. Block diagram
TJA1022
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 24 April 2013
3 of 26
TJA1022
NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
6. Pinning information
6.1 Pinning
terminal 1
index area
TJA1022T
TJA1122TK
RXD1
1
2
3
4
5
6
7
14 n.c.
13 LIN1
12 n.c.
11 n.c.
1
2
3
4
5
6
7
14
13
12
11
10
9
RXD1
SLP1_N
TXD1
n.c.
LIN1
n.c.
n.c.
SLP1_N
TXD1
RXD2
SLP2_N
n.c.
RXD2
10
9
V
BAT
SLP2_N
n.c.
V
BAT
LIN2
GND
LIN2
GND
TXD2
8
8
TXD2
015aaa286
015aaa287
a. TJA1022T: SO14 package
Fig 2. Pin configuration diagrams
b. TJA1022TK: HVSON14 package
6.2 Pin description
Table 3.
Symbol
Pin description
Pin Description
RXD1
SLP1_N
TXD1
RXD2
SLP2_N
n.c.
1
receive data output 1 (open-drain); active LOW after a wake-up event
2
sleep control input 1 (active LOW); resets wake-up request on RXD1
3
transmit data input 1
4
receive data output 2 (open-drain); active LOW after a wake-up event
5
sleep control input 2 (active LOW); resets wake-up request on RXD2
6
not connected
TXD2
GND
LIN2
7
8[1]
transmit data input 2
ground
9
LIN bus line 2 input/output
battery supply
VBAT
10
11
12
13
14
n.c.
not connected
n.c.
not connected
LIN1
LIN bus line 1 input/output
not connected
n.c.
[1] For enhanced thermal and electrical performance, the exposed center pad of the HVSON14 package
should be soldered to board ground (and not to any other voltage level).
TJA1022
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 24 April 2013
4 of 26
TJA1022
NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
7. Functional description
The TJA1022 is the interface between the LIN master/slave protocol controller and the
physical bus in a LIN network. According to the Open System Interconnect (OSI) model,
this is the LIN physical layer.
The LIN transceivers are optimized for, but not limited to, automotive applications with
excellent ElectroMagnetic Compatibility (EMC) performance.
7.1 LIN 2.x/SAE J2602 compliant
The TJA1022 is fully LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and SAE J2602 compliant. The
LIN physical layer is independent of higher OSI model layers (e.g. the LIN protocol).
Consequently, nodes containing a LIN 2.2A-compliant physical layer can be combined,
without restriction, with LIN physical layer nodes that comply with earlier revisions
(LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3, LIN 2.0, LIN 2.1 and LIN 2.2).
7.2 Operating modes
The transceivers are fully operational in Normal mode. A low-power Sleep mode is also
supported, as well as a Reset mode. Standby mode facilitates the transition between
Sleep and Normal modes.
The transceivers operate independently (except in Reset mode), so one transceiver can
be in Normal mode while the other is Sleep or Standby etc. Power consumption is at a
minimum when both transceivers are in Sleep mode.
7.2.1 Normal mode
In Normal mode, the TJA1022 can transmit and receive data via the LIN bus lines. The
transceivers operate independently, so one can be active while the other is off.
A transceiver will switch from Sleep or Standby mode to Normal mode if SLPx_N is held
HIGH for tgotonorm. If SLPx_N is held LOW for tgotosleep, the transceiver will switch from
Normal to Sleep mode.
The receivers detect data streams on the LIN bus lines (via pins LIN1 and LIN2) and
transfer the input via pins RXD1 and RXD2 to the microcontroller (see Figure 6): HIGH for
a recessive level and LOW for a dominant level on the bus. The receivers have
supply-voltage related thresholds with hysteresis and integrated filters to suppress bus
line noise.
Transmit data streams from the protocol controller are detected on the TXDx pins and are
converted by the transmitters into optimized bus signals shaped to minimize EME. The
LIN bus output pins are pulled HIGH via internal slave termination resistors. For a master
application, an external resistor in series with a diode should be connected between pin
VBAT and the appropriate LINx pin (see Figure 6).
TJA1022
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 24 April 2013
5 of 26
TJA1022
NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
falling V
< V
th(POR)L
BAT
Reset
RXDx: floating
Transmitter: off
Normal x
RXDx: data output
(1)
Transmitter: on
rising V
> V
t
> t
BAT
th(POR)H
(SLPx_N = 1) gotonorm
t
> t
gotonorm
(SLPx_N = 1)
t
> t
gotosleep
(SLPx_N = 0)
Sleep x(2)
RXDx: floating
Transmitter: off
Standby x
(3)
RXDx: LOW
Transmitter: off
t
> t
wake(dom)LIN
(LINx = 0 → 1; after LINx = 0)
015aaa290
(1) A positive edge on SLPx_N triggers a transition to Normal mode in the corresponding LIN transceiver; the LIN transmitter is
enabled once TXDx goes HIGH; in the event of thermal shutdown, both LIN transceivers are disabled.
(2) Power dissipation is at a minimum when both transceivers are in Sleep mode.
(3) When a transceiver switches to Standby mode in response to a LIN bus wake-up event, the associated RXDx pin (RXD1 or
RXD2) will be LOW to indicate which LIN channel was the source of the wake-up request.
Fig 3. State diagram
7.2.2 Sleep mode
A transceiver will switch to Sleep mode from Normal mode if SLPx_N is held LOW for
tgotosleep. The relevant LIN transmit path is disabled as soon as SLPx_N goes LOW.
Power consumption is very low when both transceivers are in Sleep mode.
The voltage levels on LINx and TXDx have no effect on a transition to Sleep mode. So the
transceiver will still switch to Sleep mode even if TXDx is held LOW or there is a
continuous dominant level on LINx (e.g. due to a short circuit to ground).
Although current consumption is extremely low when both transceivers are in Sleep
mode, the TJA1022 can still be woken up remotely via the LIN bus pins or by the
microcontroller via pins SLPx_N. Filters on the receiver inputs (LIN1 and LIN 2) and on
pins SLPx_N prevent unwanted wake-up events occurring due to automotive transients or
radio frequency interference. To be valid, all wake-up events must be maintained for a
specific length of time (twake(dom)LIN for a remote wake-up and tgotonorm for a wake-up via
SLPx_N). Pin RXDx is floating when a transceiver is in Sleep mode.
TJA1022
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 24 April 2013
6 of 26
TJA1022
NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
If a remote wake-up event (see Figure 4) is detected on either of the LIN bus lines, the
associated transceiver will switch to Standby mode. A wake-up initiated by the
microcontroller (SLPx_N HIGH for tgotonorm) will cause the relevant transceiver to switch to
Normal mode while the other transceiver remains in its current state.
7.2.3 Standby mode
Standby mode is an intermediate mode between Sleep and Normal modes. A transceiver
will switch from Sleep mode to Standby mode in response to a LIN bus wake-up event.
Pin RXDx will go low to indicate to the microcontroller the source of the remote wake-up
(LIN1 or LIN2). A transceiver will switch from Standby to Normal mode if the
microcontroller holds SLPx_N HIGH for tgotonorm
.
7.2.4 Reset mode
When the TJA1022 is in Reset mode, all input signals are ignored and all output drivers
are off. The TJA1022 switches to Reset mode when the voltage on VBAT drops below the
LOW-level power-on reset threshold, Vth(POR)L. When the voltage on VBAT rises above the
HIGH-level power-on reset threshold, Vth(POR)H, the transceivers switch to Sleep mode.
Table 4.
Mode
Operating modes
SLPx_N RXDx
Transmitter x
Description
Reset
x
floating
off
all inputs ignored; all output
drivers off
Sleep x[1]
Standby x[2]
0
0
floating
LOW[3]
off
off
no wake-up request detected
remote wake-up request
detected
Normal x
1
HIGH: recessive
LOW: dominant
on/off[4]
bus signal shaping enabled
[1] Both transceivers enter Sleep mode after a power-on reset (e.g. after switching on VBAT).
[2] The appropriate transceiver will switch automatically to Standby x mode if a remote LINx wake-up event is
detected in Sleep x mode.
[3] RXDx will be LOW to indicate the source of the remote wake-up request; RXDx will go HIGH in response to
a positive edge on pin SLPx_N.
[4] A positive edge on SLPx_N will trigger a transition to Normal mode; the transmitter will be off if TXDx is
LOW and will be enabled as soon as TXDx goes HIGH.
TJA1022
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 24 April 2013
7 of 26
TJA1022
NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
7.3 Transceiver wake-up
7.3.1 Remote wake-up via the LIN bus
A falling edge on pin LINx followed by a LOW level maintained for twake(dom)LIN followed by
a rising edge on pin LINx triggers a remote wake-up (see Figure 4). It should be noted that
the time period twake(dom)LIN is measured either in Normal mode while TXDx is HIGH, or in
Sleep mode irrespective of the status of pin TXDx.
LIN recessive
V
BUSrec
V
V
t
wake(dom)LIN
BUSdom
LINx
LIN dominant
sleep mode
ground
standby mode
015aaa297
Fig 4. Remote wake-up behavior
7.3.2 Wake-up via SLPx_N
If SLPx_N is held HIGH for tgotonorm, the transceiver will switch from Sleep mode to
Normal mode.
7.4 Operation during automotive cranking pulses
TJA1022 remains fully operational during automotive cranking pulses because the LIN
transceivers are fully specified down to VBAT = 5 V.
7.5 Operation when supply voltage is outside specified operating range
If VBAT > 18 V or VBAT < 5 V, the TJA1022 may remain operational, but parameter values
cannot be guaranteed to remain within the operating ranges specified in Table 7 and
Table 8.
In Normal mode:
• If the input level on pin TXDx is HIGH, the LIN transmitter output on pin LINx will be
recessive.
• If the input level on pin LINx is recessive, the receiver output on pin RXDx will be
HIGH.
• If the voltage on pin VBAT rises to 27 V (e.g. during an automotive jump-start), the total
LIN network pull-up resistance should be greater than 680 and the total LIN network
capacitance should be less than 6.8 nF to ensure reliable LIN data transfer.
• If the voltage on pin VBAT drops below the LOW-level VBAT LOW threshold, Vth(VBATL)L
the active LIN transmit path(s) is interrupted and both LIN outputs will be recessive.
The previously active LIN transmit path(s) is switched on again when VBAT rises
above Vth(VBATL)H and the associated TXDx pin is HIGH.
,
TJA1022
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 24 April 2013
8 of 26
TJA1022
NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
If the voltage on pin VBAT drops below the LOW-level power-on reset threshold, Vth(POR)L
,
the TJA1022 switches to Reset mode (i.e. all output drivers are disabled and all inputs are
ignored). The TJA1022 switches to Sleep mode if VBAT > Vth(POR)H
.
7.6 Fail-safe features
Pin TXDx is pulled down to ground in order to force a predefined level on the transmit data
input if the pin is disconnected.
Pin SLPx_N is pulled down to ground to ensure the transceiver is forced to Sleep x mode
if SLPx_N is disconnected.
Pins RXD1 and RXD2 are set floating if VBAT is disconnected.
The current in the transmitter output stage is limited in order to protect the transmitter
against short circuits to pins VBAT or GND.
A loss of power (pins VBAT and GND) has no impact on the bus lines or on the
microcontroller. No reverse current will flow from the bus lines into the LINx pins. The
current path from VBAT to LINx via the integrated LIN slave termination resistors remains.
The TJA1022 can be disconnected from the power supply without influencing the LIN
busses.
The output drivers on pins LIN1 and LIN2 are protected against overtemperature
conditions. If the junction temperature exceeds the shutdown junction temperature, Tj(sd)
the thermal protection circuit disables the output drivers. The drivers are enabled again
when the junction temperature falls below Tj(sd) and pin TXDx is HIGH.
,
The initial TXD dominant check prevents the bus being driven to a permanent dominant
state (blocking all network communications) if pin TXDx is forced permanently LOW by a
hardware and/or software application failure. The input level on TXDx is checked after a
transition to Normal mode. If TXDx is LOW, the transmit path will remain disabled and will
only be enabled when TXDx goes HIGH.
Once the transmitter has been enabled, a TXD dominant time-out timer is started every
time pin TXDx goes LOW. If the LOW state on pin TXDx persists for longer than the
TXD dominant time-out time (tto(dom)TXD), the transmitter is disabled, releasing the bus
line to recessive state. The TXD dominant time-out timer is reset when pin TXDx goes
HIGH.
TJA1022
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 24 April 2013
9 of 26
TJA1022
NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to pin GND, unless
otherwise specified. Positive currents flow into the IC.
Symbol
VBAT
Parameter
Conditions
Min
0.3
0.3
0.3
0.3
42
Max
+42
+7
Unit
V
battery supply voltage
voltage on pin TXD
voltage on pin RXD
voltage on pin SLP_N
voltage on pin LIN
VTXD
pins TXD1 and TXD2
pins RXD1 and RXD2
pins SLP1_N and SLP2_N
V
VRXD
+7
V
VSLP_N
VLIN
+7
V
pins LIN1 and LIN2; with respect to
GND and VBAT
+42
V
V(LIN1-LIN2)
voltage difference between pin
LIN1 and pin LIN2 (absolute
value)
-
42
V
VESD
electrostatic discharge voltage
according to IEC 61000-4-2
human body model
[1]
[2]
[2]
on pins LIN1, LIN2 and VBAT
on pins LIN1, LIN2 and VBAT
8
8
2
+8
+8
+2
kV
kV
kV
on pins TXD1, TXD2, RXD1, RXD2,
SLP1_N and SLP2_N
charge device model
machine model
all pins
all pins
750
200
40
+750
+200
+150
+150
V
[3]
[4]
V
Tvj
virtual junction temperature
storage temperature
C
C
Tstg
55
[1] Equivalent to discharging a 150 pF capacitor through a 330 resistor.
[2] Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor.
[3] Equivalent to discharging a 200 pF capacitor through a 10 resistor and a 0.75 H coil.
[4] Junction temperature in accordance with IEC 60747-1. An alternative definition is: Tj = Tamb + P Rth(j-a), where Rth(j-a) is a fixed value.
The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).
9. Thermal characteristics
Table 6.
Thermal characteristics
According to IEC 60747-1.
Symbol
Parameter
Conditions
Typ
145
50
Unit
K/W
K/W
Rth(j-a)
thermal resistance from junction to ambient
SO14 package; in free air
HVSON14 package; in free air
TJA1022
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 24 April 2013
10 of 26
TJA1022
NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
10. Static characteristics
Table 7.
BAT = 5 V to 18 V; Tvj = 40 C to +150 C; RL(LIN-VBAT) = 500 ; all voltages are referenced to pin GND; positive currents
flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1]
Static characteristics
V
Symbol
Supply
VBAT
Parameter
Conditions
Min
Typ
Max
Unit
battery supply voltage
battery supply current
5
-
18
10
V
IBAT
Sleep mode (both channels);
bus recessive (both channels);
2.5
7
A
VLINx = VBAT; VSLPx_N = 0 V
Sleep mode (both channels);
bus dominant (both channels);
VLINx = 0 V; VSLPx_N = 0 V;
300
800
3200
A
VBAT = 12 V
Standby mode (both channels);
bus recessive (both channels);
2.5
7
10
A
A
V
LINx = VBAT; VSLPx_N = 0 V
Standby mode (both channels);
bus dominant (both channels);
200
600
2000
VLINx = 0 V; VSLPx_N = 0 V;
VBAT = 12 V
Normal mode (both channels);
bus recessive (both channels);
300
1
1600
4
3200
10
A
V
TXDx = 5 V; VLINx = VBAT
;
VSLPx_N = 5 V
Normal mode (both channels);
bus dominant (both channels);
mA
VTXDx = 0 V; VSLPx_N = 5 V;
VBAT = 12 V
Undervoltage reset
Vth(POR)L
LOW-level power-on reset power-on reset
threshold voltage
1.6
3.1
3.4
0.3
4.4
4.7
0.3
3.9
4.3
1
V
V
V
V
V
V
Vth(POR)H
Vhys(POR)
Vth(VBATL)L
Vth(VBATL)H
Vhys(VBATL)
HIGH-level power-on reset
threshold voltage
2.3
[2]
power-on reset hysteresis
voltage
0.05
3.9
LOW-level VBAT LOW
threshold voltage
4.7
4.9
0.6
HIGH-level VBAT LOW
threshold voltage
4.2
[2]
VBAT LOW hysteresis
voltage
0.15
Pins TXDx and SLPx_N
VIH
VIL
HIGH-level input voltage
2
-
7
V
LOW-level input voltage
hysteresis voltage
0.3
50
-
+0.8
400
325
650
V
[2]
Vhys
Rpd
200
125
250
mV
k
k
pull-down resistance
on TXDx
50
on SLPx_N
100
TJA1022
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 24 April 2013
11 of 26
TJA1022
NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
Table 7.
Static characteristics …continued
VBAT = 5 V to 18 V; Tvj = 40 C to +150 C; RL(LIN-VBAT) = 500 ; all voltages are referenced to pin GND; positive currents
flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IIL
LOW-level input current
VTXDx = 0 V or VSLPx_N = 0 V
5
-
+5
A
Pin RXDx (open-drain)
IOL LOW-level output current VRXDx = 0.4 V
ILH
2
-
-
-
mA
[2]
HIGH-level leakage
current
5
+5
A
Pin LINx
IBUS_LIM
current limitation for driver VBAT = 18 V; VLINx = 18 V;
dominant state VTXDx = 0 V
40
-
-
100
-
mA
[2]
[2]
IBUS_PAS_dom receiver dominant input BAT = 12 V; VLINx = 0 V;
V
600
A
leakage current including VTXDx = 5 V
pull-up resistor
IBUS_PAS_rec
receiver recessive input
leakage current
VBAT = 5 V; VLINx = 18 V;
VTXDx = 5 V
-
0
1
A
[2]
[2]
IBUS_NO_GND loss-of-ground bus current VBAT = 18 V; VLINx = 0 V
IBUS_NO_BAT loss-of-battery bus current VBAT = 0 V; VLINx = 18 V
750
-
-
-
-
+10
A
A
V
-
1
VBUSdom
VBUSrec
receiver dominant state
receiver recessive state
receiver center voltage
-
0.4VBAT
-
0.6VBAT
V
VBUS_CNT
VBUS_CNT
=
0.475VBAT 0.5VBAT
0.525VBAT
V
(VBUSdom + VBUSrec) / 2
VHYS
receiver hysteresis voltage VHYS = VBUSrec VBUSdom
-
-
-
0.175VBAT
1.0
V
V
[2]
[2]
[2]
VSerDiode
voltage drop at the serial
diode
in pull-up path with Rslave
ISerDiode = 0.9 mA
;
0.4
VO(dom)
dominant output voltage
Normal mode; VTXDx = 0 V;
VBAT = 7.0 V
-
-
-
-
1.4
2.0
V
V
Normal mode; VTXDx = 0 V;
VBAT = 18 V
Rslave
CLIN
slave resistance
20
-
30
-
60
20
k
[2]
[2]
capacitance on pin LIN
pins LIN1 and LIN2; with
respect to GND
pF
Thermal shutdown
Tj(sd) shutdown junction
temperature
150
-
200
C
[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2] Not tested in production; guaranteed by design.
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Dual LIN 2.2A/SAE J2602 transceiver
11. Dynamic characteristics
Table 8.
BAT = 5 V to 18 V; Tvj = 40 C to +150 C; RL(LIN-VBAT) = 500 ; all voltages are referenced to pin GND; positive currents
flow into the IC; typical values are given at VBAT = 12 V, unless otherwise specified.[1]
Dynamic characteristics
V
Symbol
Duty cycles
1
Parameter
Conditions
Min
Typ
Max Unit
[2][4][5]
[2][4][5]
[3][4][5]
[3][4][5]
[2][4][5]
[2][4][5]
[3][4][5]
[3][4][5]
duty cycle 1
Vth(rec)(max) = 0.744 VBAT
Vth(dom)(max) = 0.581 VBAT
;
0.396 -
0.396 -
-
;
t
bit = 50 s; VBAT = 7 V to 18 V
Vth(rec)(max) = 0.768 VBAT
Vth(dom)(max) = 0.6 VBAT
bit = 50 s; VBAT = 5 V to 7 V
;
-
;
t
2
3
4
duty cycle 2
duty cycle 3
duty cycle 4
V
V
th(rec)(min) = 0.422 VBAT
th(dom)(min) = 0.284 VBAT
;
-
-
-
-
0.581
0.581
-
;
tbit = 50 s; VBAT = 7.6 V to 18 V
th(rec)(min) = 0.405 VBAT
Vth(dom)(min) = 0.271 VBAT
tbit = 50 s; VBAT = 5.6 V to 7.6 V
Vth(rec)(max) = 0.778 VBAT
Vth(dom)(max) = 0.616 VBAT
tbit = 96 s; VBAT = 7 V to 18 V
th(rec)(max) = 0.805 VBAT
Vth(dom)(max) = 0.637 VBAT
tbit = 96 s; VBAT = 5 V to 7 V
th(rec)(min) = 0.389 VBAT
Vth(dom)(min) = 0.251 VBAT
tbit = 96 s; VBAT = 7.6 V to 18 V
th(rec)(min) = 0.372 VBAT
V
;
;
;
0.417 -
0.417 -
;
V
;
-
;
V
;
-
-
-
-
0.590
0.590
;
V
Vth(dom)(min) = 0.238 VBAT
tbit = 96 s; VBAT = 5.6 V to 7.6 V
Timing characteristics
[5]
[5]
trx_pd
receiver propagation
delay
rising and falling;
CRXDx = 20 pF; RRXDx = 2.4 k
-
-
6
s
s
s
s
trx_sym
receiver propagation
delay symmetry
CRXDx = 20 pF; RRXDx = 2.4 k;
rising edge with respect to falling edge
2
30
2
-
+2
150
10
twake(dom)LIN
tgotonorm
LIN dominant wake-up
time
Sleep mode
80
6
go to normal time
time period for mode change from
Sleep or Standby mode to Normal
mode
tinit(norm)
tgotosleep
tto(dom)TXD
normal mode
initialization time
7
2
6
-
20
10
50
s
s
ms
go to sleep time
time period for mode change from
Normal to Sleep mode
6
TXD dominant time-out timer started at falling edge on TXDx
time
12
[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage ranges.
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Product data sheet
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NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
tbusrecmin
-------------------------------
[2] 1 3 =
[3] 2 4 =
. Variable tbus(rec)(min) is illustrated in the LIN timing diagram in Figure 5.
2 tbit
tbusrecmax
-------------------------------
2 tbit
. Variable tbus(rec)(max) is illustrated in the LIN timing diagram in Figure 5.
[4] Bus load conditions: CBUS = 1 nF and RBUS = 1 k; CBUS = 6.8 nF and RBUS = 660 ; CBUS = 10 nF and RBUS = 500 .
[5] See timing diagram in Figure 5.
t
bit
t
bit
V
TXDx
t
t
t
bus(rec)(min)
bus(dom)(max)
V
V
V
V
th(rec)(max)
th(dom)(max)
th(rec)(min)
th(dom)(min)
thresholds of
receiving node 1
LINx BUS
signal
t
bus(dom)(min)
bus(rec)(max)
V
BAT
thresholds of
receiving node 2
t
t
t
rx_pdf
rx_pdr
rx_pdf
V
V
RXDx
receiving
node 1
t
t
t
rx_pdf
rx_pdf
rx_pdr
RXDx
receiving
node 2
015aaa296
Fig 5. Timing diagram of LIN transceiver duty cycle
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Product data sheet
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NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
12. Application information
12.1 Application diagram
V
ECU
LIN BUS
LINE 1
LIN BUS
LINE 2
BATTERY
+3 V/
+5 V
only for
master node
V
BAT
1 kΩ
1 kΩ
RXD1
TXD1
V
10
DD
RX0
TX0
RX1
TX1
Px.x
Px.y
1
3
4
7
2
5
RXD2
LIN1
13
MICRO-
CONTROLLER
TJA1022
(1)
(1)
TXD2
SLP1_N
SLP2_N
LIN2
9
GND
8
015aaa291
(1) Master: C = 1 nF; slave: C = 220 pF
Fig 6. Application diagram
12.2 ESD robustness according to LIN EMC test specification
ESD robustness (IEC 61000-4-2) has been tested by an external test house according to
the LIN EMC test specification (part of Conformance Test Specification Package for
LIN 2.1, October 10th, 2008). The test report is available on request.
Table 9.
Pin
ESD robustness (IEC 61000-4-2) according to LIN EMC test specification
Test configuration
Value
12
Unit
kV
LIN
no capacitor connected to LIN pin
220 pF capacitor connected to LIN pin
100 nF capacitor connected to VBAT pin
12
kV
VBAT
> 14
kV
12.3 Hardware requirements for LIN interfaces in automotive applications
The TJA1022 satisfies the "Hardware Requirements for LIN, CAN and FlexRay Interfaces
in Automotive Applications", Version 1.2, March 2011.
TJA1022
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Product data sheet
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NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
13. Test information
13.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive applications.
TJA1022
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Product data sheet
Rev. 2 — 24 April 2013
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NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
14. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
v
c
y
H
M
A
E
Z
8
14
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
7
e
detail X
w
M
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.75
1.27
0.05
1.05
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.024
0.028
0.012
inches
0.041
0.01 0.004
0.069
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT108-1
076E06
MS-012
Fig 7. Package outline SOT108-1 (SO14)
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NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
HVSON14: plastic, thermal enhanced very thin small outline package; no leads;
14 terminals; body 3 x 4.5 x 0.85 mm
SOT1086-2
X
D
B
A
E
A
A
1
c
terminal 1
index area
detail X
e
1
terminal 1
index area
C
v
C
C
A
B
e
b
y
1
y
w
C
1
7
L
k
E
h
14
8
D
h
0
2.5
5 mm
w
scale
Dimensions
Unit
A
A
b
c
D
D
h
E
E
e
e
1
k
L
v
y
y
1
1
h
max 1.00 0.05 0.35
mm nom 0.85 0.03 0.32 0.2 4.5 4.20 3.0 1.60 0.65 3.9 0.30 0.40 0.1 0.05 0.05 0.1
min 0.80 0.00 0.29 4.4 4.15 2.9 1.55 0.25 0.35
4.6 4.25 3.1 1.65
0.35 0.45
sot1086-2
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
JEITA
- - -
10-07-14
10-07-15
SOT1086-2
MO-229
Fig 8. Package outline SOT1086-2 (HVSON14)
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Product data sheet
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18 of 26
TJA1022
NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
15. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
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Product data sheet
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19 of 26
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NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 9) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 10 and 11
Table 10. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
235
350
220
< 2.5
2.5
220
220
Table 11. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 9.
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Product data sheet
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NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 9. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Soldering of HVSON packages
Section 16 contains a brief introduction to the techniques most commonly used to solder
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON
leadless package ICs can be found in the following application notes:
• AN10365 “Surface mount reflow soldering description”
• AN10366 “HVQFN application information”
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Product data sheet
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NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
18. Mounting
The TJA1022 pin layout has been designed to be compatible with the TJA1020, TJA1021
and TJA1027. This makes it possible to design a board with a single socket that can
accommodate all four IC’s. The appropriate device would be inserted into the socket,
depending on the application, as illustrated in Figure 10.
1
2
3
4
8
7
6
5
RXD
SLP_N
n.c.
n.c.
V
BAT
TJA1027
TJA1020
TJA1021
LIN
1
2
3
4
5
6
7
14
13
12
11
10
9
RXD1
SLP1_N
TXD1
n.c.
LIN1
n.c.
n.c.
TXD
GND
RXD2
TJA1022
1
2
3
4
8
7
6
5
RXD
NSLP
INH
BAT
LIN
SLP2_N
n.c.
V
BAT
NWAKE
TXD
LIN2
GND
GND
8
TXD2
1
2
3
4
8
7
6
5
RXD
SLP_N
WAKE_N
TXD
INH
V
BAT
LIN
GND
015aaa308
Fig 10. The TJA1022 is pin compatible with the TJA1027, TJA1020 and TJA1021
TJA1022
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NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
19. Revision history
Table 12. Revision history
Document ID
TJA1022 v.2
Modifications:
Release date
20130424
Data sheet status
Change notice
Supersedes
Product data sheet
-
TJA1022 v.1
• text in Title, Section 1, Section 2.1, Section 7.1 revised to include LIN 2.2A compliance
• text in Section 1 (first paragraph) revised to be consistent with TJa1027/TJa1029
• Figure 2: revised/resized
• text in Section 7.1 revised to be consistent with TJA1029
• Section 13.1: text revised
TJA1022 v.1
20120330
Product data sheet
-
-
TJA1022
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NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use in automotive applications — This NXP
20.2 Definitions
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
TJA1022
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 24 April 2013
24 of 26
TJA1022
NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TJA1022
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 24 April 2013
25 of 26
TJA1022
NXP Semiconductors
Dual LIN 2.2A/SAE J2602 transceiver
22. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
18
19
Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history . . . . . . . . . . . . . . . . . . . . . . . 23
2
2.1
2.2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
20
Legal information . . . . . . . . . . . . . . . . . . . . . . 24
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 25
20.1
20.2
20.3
20.4
3
4
5
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
21
22
Contact information . . . . . . . . . . . . . . . . . . . . 25
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
7.1
7.2
Functional description . . . . . . . . . . . . . . . . . . . 5
LIN 2.x/SAE J2602 compliant. . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Transceiver wake-up . . . . . . . . . . . . . . . . . . . . 8
Remote wake-up via the LIN bus . . . . . . . . . . . 8
Wake-up via SLPx_N . . . . . . . . . . . . . . . . . . . . 8
Operation during automotive cranking pulses . 8
Operation when supply voltage is outside
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.3.1
7.3.2
7.4
7.5
specified operating range . . . . . . . . . . . . . . . . . 8
Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 9
7.6
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal characteristics . . . . . . . . . . . . . . . . . 10
Static characteristics. . . . . . . . . . . . . . . . . . . . 11
Dynamic characteristics . . . . . . . . . . . . . . . . . 13
9
10
11
12
12.1
12.2
Application information. . . . . . . . . . . . . . . . . . 15
Application diagram . . . . . . . . . . . . . . . . . . . . 15
ESD robustness according to LIN EMC
test specification. . . . . . . . . . . . . . . . . . . . . . . 15
Hardware requirements for LIN interfaces
12.3
in automotive applications . . . . . . . . . . . . . . . 15
13
13.1
14
Test information. . . . . . . . . . . . . . . . . . . . . . . . 16
Quality information . . . . . . . . . . . . . . . . . . . . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
Handling information. . . . . . . . . . . . . . . . . . . . 19
15
16
Soldering of SMD packages . . . . . . . . . . . . . . 19
Introduction to soldering . . . . . . . . . . . . . . . . . 19
Wave and reflow soldering . . . . . . . . . . . . . . . 19
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 19
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 20
16.1
16.2
16.3
16.4
17
Soldering of HVSON packages. . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 April 2013
Document identifier: TJA1022
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