TJA1027TK/20/1J [NXP]

TJA1027 - LIN 2.2A/SAE J2602 transceiver SON 8-Pin;
TJA1027TK/20/1J
型号: TJA1027TK/20/1J
厂家: NXP    NXP
描述:

TJA1027 - LIN 2.2A/SAE J2602 transceiver SON 8-Pin

电信 光电二极管 电信集成电路
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TJA1027  
LIN 2.2A/SAE J2602 transceiver  
Rev. 2 — 24 April 2013  
Product data sheet  
1. General description  
The TJA1027 is the interface between the Local Interconnect Network (LIN) master/slave  
protocol controller and the physical bus in a LIN network. It is primarily intended for  
in-vehicle sub-networks using baud rates up to 20 kBd and is compliant with LIN 2.0,  
LIN 2.1, LIN 2.2, LIN 2.2A and SAE J2602. The TJA1027 is pin-compatible with the  
TJA1020 and the TJA1021.  
The transmit data stream generated by the protocol controller is converted by the  
TJA1027 into an optimized bus signal shaped to minimize ElectroMagnetic Emissions  
(EME). The LIN bus output pin is pulled HIGH via an internal termination resistor. For a  
master application, an external resistor in series with a diode should be connected  
between pin VBAT and pin LIN. The receiver detects a receive data stream on the LIN bus  
input pin and transfers it via pin RXD to the microcontroller.  
Power consumption is very low in Sleep mode. However, the TJA1027 can still be woken  
up via pins LIN and SLP_N.  
2. Features and benefits  
2.1 General  
Compliant with LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and SAE J2602  
Baud rate up to 20 kBd  
Very low ElectroMagnetic Emissions (EME)  
Very low current consumption in Sleep mode with remote LIN wake-up  
Input levels compatible with 3.3 V and 5 V devices  
Integrated termination resistor for LIN slave applications  
Passive behavior in unpowered state  
Operational during cranking pulse: full operation from 5 V upwards  
Undervoltage detection  
K-line compatible  
Available in SO8 and HVSON8 packages  
Leadless HVSON8 package (3.0 mm 3.0 mm) with improved Automated Optical  
Inspection (AOI) capability  
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)  
compliant)  
Pin-compatible subset of the TJA1020 and TJA1021  
 
 
 
TJA1027  
NXP Semiconductors  
LIN 2.2A/SAE J2602 transceiver  
2.2 Protection  
Very high ElectoMagnetic Immunity (EMI)  
Very high ESD robustness: 8 kV according to IEC 61000-4-2 for pins LIN and VBAT  
Bus terminal and battery pin protected against transients in the automotive  
environment (ISO 7637)  
Bus terminal short-circuit proof to battery and ground  
Thermally protected  
Initial transmit data (TXD) dominant check  
3. Quick reference data  
Table 1.  
Symbol Parameter  
VBAT battery supply voltage  
Quick reference data  
Conditions  
Min  
0.3  
5
Typ  
Max  
+42  
18  
Unit  
V
limiting values  
-
operating range  
-
V
IBAT  
battery supply current  
Sleep mode; VLIN = VBAT; VSLP_N = 0 V  
2.5  
7
10  
A  
A  
A  
Standby mode; VLIN = VBAT; VSLP_N = 0 V 2.5  
7
10  
Normal mode; VLIN = VBAT; VSLP_N = 5 V; 200  
VTXD = 5 V  
800  
1600  
VLIN  
voltage on pin LIN  
limiting value; with respect to GND and  
VBAT  
42  
-
+42  
V
VESD  
Tvj  
electrostatic discharge voltage on pin LIN; according to IEC 61000-4-2  
virtual junction temperature  
8  
-
-
+8  
kV  
40  
+150  
C  
4. Ordering information  
Table 2.  
Ordering information  
Type number  
Package  
Name  
Description  
plastic small outline package; 8 leads; body width 3.9 mm  
Version  
TJA1027T/20  
SO8  
SOT96-1  
TJA1027TK/20  
HVSON8  
plastic thermal enhanced very thin small outline package; no leads;  
SOT782-1  
8 terminals; body 3 3 0.85 mm  
TJA1027  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 24 April 2013  
2 of 24  
 
 
 
TJA1027  
NXP Semiconductors  
LIN 2.2A/SAE J2602 transceiver  
5. Block diagram  
TJA1027  
POWER-ON RESET &  
7
6
V
BAT  
UNDERVOLTAGE DETECTION  
1
2
4
RXD  
BUS  
TIMER  
LIN  
SLP_N  
TXD  
CONTROL  
5
GND  
TEMPERATURE  
PROTECTION  
015aaa212  
Fig 1. Block diagram  
TJA1027  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 24 April 2013  
3 of 24  
 
TJA1027  
NXP Semiconductors  
LIN 2.2A/SAE J2602 transceiver  
6. Pinning information  
6.1 Pinning  
terminal 1  
index area  
TJA1027T  
TJA1027TK  
1
2
3
4
8
7
6
5
RXD  
SLP_N  
n.c.  
n.c.  
n.c.  
V
RXD  
SLP_N  
n.c.  
1
2
3
4
8
7
6
5
BAT  
V
BAT  
LIN  
LIN  
TXD  
GND  
TXD  
GND  
015aaa214  
Transparent top view  
015aaa213  
a. TJA1027T/20: SO8 package  
b. TJA1027TK/20: HVSON8 package  
Fig 2. Pin configuration diagrams  
6.2 Pin description  
Table 3.  
Pin description  
Symbol  
Pin  
Description  
RXD  
1
receive data output (open-drain); active LOW after a wake-up  
event  
SLP_N  
n.c.  
2
sleep control input (active LOW); resets wake-up request on RXD  
3
not connected  
transmit data input  
ground  
TXD  
GND  
LIN  
4
5[1]  
6
LIN bus line input/output  
battery supply  
not connected  
VBAT  
n.c.  
7
8
[1] For enhanced thermal and electrical performance, the exposed center pad of the HVSON8 package should  
be soldered to board ground (and not to any other voltage level).  
TJA1027  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 24 April 2013  
4 of 24  
 
 
 
 
 
 
TJA1027  
NXP Semiconductors  
LIN 2.2A/SAE J2602 transceiver  
7. Functional description  
The TJA1027 is the interface between the LIN master/slave protocol controller and the  
physical bus in a LIN network. According to the Open System Interconnect (OSI) model,  
this is the LIN physical layer.  
The LIN transceiver is optimized for, but not limited to, automotive applications with  
excellent ElectroMagnetic Compatibility (EMC) performance.  
7.1 LIN 2.x/SAE J2602 compliant  
The TJA1027 is fully LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and SAE J2602 compliant. The  
LIN physical layer is independent of higher OSI model layers (e.g. the LIN protocol).  
Consequently, nodes containing a LIN 2.2A-compliant physical layer can be combined,  
without restriction, with LIN physical layer nodes that comply with earlier revisions  
(LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3, LIN 2.0, LIN 2.1 and LIN 2.2).  
7.2 Operating modes  
The TJA1027 supports modes for normal operation (Normal mode) and very-low-power  
operation (Sleep mode). An intermediate wake-up mode between Sleep and Normal  
modes is also supported (Standby mode). The state diagram is shown in Figure 3.  
TJA1027  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 24 April 2013  
5 of 24  
 
 
 
TJA1027  
NXP Semiconductors  
LIN 2.2A/SAE J2602 transceiver  
falling V  
< V  
th(POR)L  
BAT  
Reset  
RXD: floating  
Transmitter: off  
Normal  
RXD: data output  
(1)  
Transmitter: on  
rising V  
> V  
t
> t  
BAT  
th(POR)H  
(SLP_N = 1) gotonorm  
t
> t  
gotonorm  
(SLP_N = 1)  
t
> t  
gotosleep  
(SLP_N = 0)  
Sleep  
Standby  
RXD: low  
Transmitter: off  
RXD: floating  
Transmitter: off  
t
> t  
wake(dom)LIN  
(LIN = 0→1; after LIN = 0)  
015aaa215  
(1) A positive edge on SLP_N triggers a transition to Normal mode; the transmitter is enabled once  
TXD goes HIGH; in the event of thermal shut down, the transmitter is disabled.  
Fig 3. State diagram  
Table 4.  
Mode  
Operating modes  
SLP_N  
RXD  
Transmitter  
Description  
Reset  
x
floating  
off  
all inputs ignored; all outputs  
drivers off  
Sleep[1]  
Standby[2]  
Normal  
0
0
1
floating  
LOW[3]  
off  
off  
no wake-up request detected  
wake-up request detected  
HIGH: recessive state Normal mode[4] bus signal shaping enabled  
LOW: dominant state  
[1] The TJA1027 enters Sleep mode after a power-on reset (e.g. after switching on VBAT).  
[2] The TJA1027 will switch automatically to Standby mode if a LIN wake-up event occurs during Sleep mode.  
[3] The wake-up interrupt (on pin RXD) is released after a positive edge on pin SLP_N.  
[4] A positive edge on SLP_N will trigger a transition to Normal mode The transmitter will be off if TXD is LOW  
and will be enabled as soon as TXD goes HIGH.  
TJA1027  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 24 April 2013  
6 of 24  
 
 
 
 
TJA1027  
NXP Semiconductors  
LIN 2.2A/SAE J2602 transceiver  
7.2.1 Reset mode  
When the TJA1027 is in Reset mode, it ignores all input signals and all output drivers are  
off. The TJA1027 switches to Reset mode when the voltage on VBAT drops below the  
LOW-level power-on reset threshold, Vth(POR)L. When the voltage on VBAT rises above the  
HIGH-level power-on reset threshold, Vth(POR)H, the TJA1027 switches to Sleep mode.  
7.2.2 Sleep mode  
The TJA1027 consumes significantly less power in Sleep mode than in any other mode.  
Even though current consumption is extremely low in Sleep mode, the TJA1027 can still  
be woken up remotely via pin LIN or activated directly via pin SLP_N. Filters on the  
receiver input (LIN) and on pin SLP_N prevent unwanted wake-up events occurring due to  
automotive transients or radio frequency interference. All wake-up events must be  
maintained for a specific period of time (twake(dom)LIN or tgotonorm).  
Sleep mode is initiated by a falling edge on pin SLP_N in Normal mode. The LIN transmit  
path is immediately disabled when pin SLP_N goes LOW. In order to ensure the TJA1027  
switches successfully to Sleep mode, the sleep command (pin SLP_N = LOW) must be  
maintained for at least tgotosleep  
.
Sleep mode activation is independent of the levels on pins LIN or TXD. So the lowest  
possible power consumption can be guaranteed, even when there is a continuous  
dominant level on pins LIN and TXD.  
7.2.3 Standby mode  
Standby mode is activated automatically when a local or remote wake-up event occurs  
while the TJA1027 is in Sleep mode. In Standby mode, pin RXD is held LOW to provide  
an interrupt flag for the microcontroller.  
7.2.4 Normal mode  
In Normal mode, the TJA1027 can transmit and receive data via the LIN bus.  
The receiver detects the data stream on the LIN bus input pin and transfers it via pin RXD  
to the microcontroller (see Figure 6): HIGH for a recessive level and LOW for a dominant  
level on the bus. The receiver has a supply-voltage related threshold with hysteresis and  
an integrated filter to suppress bus line noise.  
The transmit data stream from the protocol controller is detected on pin TXD and is  
converted by the transmitter into an optimized bus signal shaped to minimize EME. The  
LIN bus output pin is pulled HIGH via an internal slave termination resistor. For a master  
application, an external resistor in series with a diode should be connected between pin  
VBAT and pin LIN (see Figure 6).  
If pin SLP_N is pulled HIGH while the TJA1027 is in Sleep or Standby mode, the LIN  
transceiver switches to Normal mode after tgotonorm  
.
TJA1027  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 24 April 2013  
7 of 24  
 
 
 
 
TJA1027  
NXP Semiconductors  
LIN 2.2A/SAE J2602 transceiver  
7.3 Transceiver wake-up  
7.3.1 Remote wake-up via the LIN bus  
A falling edge on pin LIN followed by a LOW level maintained for twake(dom)LIN followed by  
a rising edge on pin LIN triggers a remote wake-up (see Figure 4). It should be noted that  
the time period twake(dom)LIN is measured either in Normal mode while TXD is HIGH, or in  
Sleep mode irrespective of the status of pin TXD.  
LIN recessive  
V
BUSrec  
V
V
t
wake(dom)LIN  
BUSdom  
LIN  
LIN dominant  
sleep mode  
ground  
standby mode  
015aaa241  
Fig 4. Remote wake-up behavior  
7.3.2 Wake-up via pin SLP_N  
If SLP_N is held HIGH for tgotonorm, the TJA1027 will switch from Sleep mode to Normal  
mode.  
7.4 Operation during automotive cranking pulses  
TJA1027 remains fully operational during automotive cranking pulses because the LIN  
transceiver is fully specified down to VBAT = 5 V.  
7.5 Operation when supply voltage is outside specified operating range  
If VBAT > 18 V or VBAT < 5 V, the TJA1027 may remain operational, but parameter values  
cannot be guaranteed to remain within the operation ranges specified in Table 7 and  
Table 8.  
In Normal mode:  
If the input level on pin TXD is HIGH, the LIN transmitter output on pin LIN will be  
recessive.  
If the input level on pin LIN is recessive, the receiver output on pin RXD will be HIGH.  
If the voltage on pin VBAT rises to 27 V (e.g. during an automotive jump start), the total  
LIN network pull-up resistance should be greater than 680 and the total LIN network  
capacitance should be less than 6.8 nF to ensure reliable LIN data transfer.  
If the voltage on pin VBAT drops below the LOW-level VBAT LOW threshold, Vth(VBATL)L  
,
the LIN transmit path is interrupted and the LIN output remains recessive. The LIN  
transmit path is switched on again when VBAT rises above Vth(VBATL)H and the input to  
pin TXD is recessive.  
TJA1027  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 24 April 2013  
8 of 24  
 
 
 
 
 
 
TJA1027  
NXP Semiconductors  
LIN 2.2A/SAE J2602 transceiver  
If the voltage on pin VBAT drops below the LOW-level power-on reset threshold, Vth(POR)L  
,
the TJA1027 switches to Reset mode (i.e. all output drivers are disabled and all inputs are  
ignored). The TJA1027 switches to Sleep mode if VBAT > Vth(POR)H  
.
7.6 Fail-safe features  
Pin TXD provides a pull-down to GND in order to force a predefined level on the transmit  
data input if the pin is disconnected.  
Pin SLP_N provides a pull-down to GND in order to force the transceiver into Sleep mode  
if pin SLP_N is disconnected.  
Pin RXD is set floating if VBAT is disconnected.  
The current in the transmitter output stage is limited in order to protect the transmitter  
against short circuits to pins VBAT or GND.  
A loss of power (pins VBAT and GND) has no impact on the bus line or on the  
microcontroller. No reverse currents flow from the bus into pin LIN. The current path from  
V
BAT to LIN via the integrated LIN slave termination resistor remains. The LIN transceiver  
can be disconnected from the power supply without influencing the LIN bus.  
The output driver on pin LIN is protected against overtemperature conditions. If the  
junction temperature exceeds the shutdown junction temperature, Tj(sd), the thermal  
protection circuit disables the output driver. The driver is enabled again when the junction  
temperature falls below Tj(sd) and pin TXD is recessive.  
The initial TXD dominant check prevents the bus line from being driven to a permanent  
dominant state (blocking all network communications) if pin TXD is forced permanently  
LOW by a hardware and/or software application failure. The TXD input level is checked  
after a transition to Normal mode. If TXD is LOW, the transmit path will remain disabled  
and will only be enabled when TXD goes HIGH.  
TJA1027  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 24 April 2013  
9 of 24  
 
TJA1027  
NXP Semiconductors  
LIN 2.2A/SAE J2602 transceiver  
8. Limiting values  
Table 5.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to pin GND, unless  
otherwise specified. Positive currents flow into the IC.  
Symbol  
VBAT  
Parameter  
Conditions  
Min  
0.3  
0.3  
0.3  
0.3  
42  
Max  
+42  
+7  
Unit  
V
battery supply voltage  
voltage on pin TXD  
voltage on pin RXD  
voltage on pin SLP_N  
voltage on pin LIN  
VTXD  
V
VRXD  
VSLP_N  
VLIN  
+7  
V
+7  
V
with respect to GND and VBAT  
+42  
V
VESD  
electrostatic discharge voltage  
[1]  
[2]  
[2]  
according to IEC 61000-4-2 on pins LIN and VBAT  
8  
+8  
kV  
kV  
kV  
V
human body model  
on pins LIN and VBAT  
on pins TXD, RXD and SLP_N  
all pins  
8  
+8  
2  
+2  
charge device model  
machine model  
750  
200  
40  
55  
+750  
+200  
+150  
+150  
[3]  
[4]  
all pins  
V
Tvj  
virtual junction temperature  
storage temperature  
C  
C  
Tstg  
[1] Equivalent to discharging a 150 pF capacitor through a 330 resistor.  
[2] Equivalent to discharging a 100 pF capacitor through a 1.5 kresistor.  
[3] Equivalent to discharging a 200 pF capacitor through a 10 resistor and a 0.75 H coil.  
[4] Junction temperature in accordance with IEC 60747-1. An alternative definition is: Tj = Tamb + P Rth(j-a), where Rth(j-a) is a fixed value.  
The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).  
9. Thermal characteristics  
Table 6.  
Thermal characteristics  
According to IEC 60747-1.  
Symbol  
Parameter  
Conditions  
Typ  
145  
50  
Unit  
K/W  
K/W  
Rth(j-a)  
thermal resistance from junction to ambient  
SO8 package; in free air  
HVSON8 package; in free air  
TJA1027  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 24 April 2013  
10 of 24  
 
 
 
 
 
 
TJA1027  
NXP Semiconductors  
LIN 2.2A/SAE J2602 transceiver  
10. Static characteristics  
Table 7.  
BAT = 5 V to 18 V; Tvj = 40 C to +150 C; RL(LIN-VBAT) = 500 ; all voltages are referenced to pin GND; positive currents  
flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1]  
Static characteristics  
V
Symbol  
Supply  
VBAT  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
battery supply voltage  
battery supply current  
5
-
18  
10  
V
IBAT  
Sleep mode; bus recessive;  
VLIN = VBAT; VSLP_N = 0 V  
2.5  
7
A  
Sleep mode; bus dominant;  
VLIN = 0 V; VBAT = 12 V;  
VSLP_N = 0 V  
150  
400  
1200  
A  
Standby mode; bus recessive;  
2.5  
7
10  
A  
A  
VLIN = VBAT; VSLP_N = 0 V  
[2]  
Standby mode; bus dominant;  
VLIN = 0 V; VBAT = 12 V;  
VSLP_N = 0 V  
100  
300  
1000  
Normal mode; bus recessive;  
200  
1
800  
2
1600  
4
A  
VLIN = VBAT; VSLP_N = 5 V;  
VTXD = 5 V  
Normal mode; bus dominant;  
VTXD = 0 V; VSLP_N = 5 V;  
VBAT = 12 V  
mA  
Undervoltage reset  
Vth(POR)L  
LOW-level power-on reset power-on reset  
threshold voltage  
1.6  
3.1  
3.4  
0.3  
4.4  
4.7  
0.3  
3.9  
4.3  
1
V
V
V
V
V
V
Vth(POR)H  
Vhys(POR)  
Vth(VBATL)L  
Vth(VBATL)H  
Vhys(VBATL)  
HIGH-level power-on reset  
threshold voltage  
2.3  
[2]  
power-on reset hysteresis  
voltage  
0.05  
3.9  
LOW-level VBAT LOW  
threshold voltage  
4.7  
4.9  
0.6  
HIGH-level VBAT LOW  
threshold voltage  
4.2  
[2]  
VBAT LOW hysteresis  
voltage  
0.15  
Pins TXD and SLP_N  
VIH  
VIL  
HIGH-level input voltage  
2
-
7
V
LOW-level input voltage  
hysteresis voltage  
0.3  
50  
-
+0.8  
400  
325  
650  
V
[2]  
Vhys  
Rpd  
200  
125  
250  
mV  
k  
k  
pull-down resistance  
on TXD  
50  
on SLP_N  
100  
Pin RXD (open-drain)  
IOL LOW-level output current VRXD = 0.4 V  
ILH  
2
-
-
-
mA  
[2]  
HIGH-level leakage  
current  
5  
+5  
A  
TJA1027  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 24 April 2013  
11 of 24  
 
 
TJA1027  
NXP Semiconductors  
LIN 2.2A/SAE J2602 transceiver  
Table 7.  
Static characteristics …continued  
VBAT = 5 V to 18 V; Tvj = 40 C to +150 C; RL(LIN-VBAT) = 500 ; all voltages are referenced to pin GND; positive currents  
flow into the IC; typical values are given at VBAT = 12 V; unless otherwise specified.[1]  
Symbol  
Pin LIN  
IBUS_LIM  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
current limitation for driver VBAT = 18 V; VLIN = 18 V;  
dominant state TXD = 0 V  
40  
-
-
100  
-
mA  
V
[2]  
[2]  
IBUS_PAS_dom receiver dominant input  
VBAT = 12 V; VLIN = 0 V;  
600  
A  
leakage current including VTXD = 5 V  
pull-up resistor  
IBUS_PAS_rec  
receiver recessive input  
leakage current  
VBAT = 5 V; VLIN = 18 V;  
-
0
1
A  
VTXD = 5 V  
[2]  
[2]  
[2]  
[2]  
IBUS_NO_GND loss-of-ground bus current VBAT = 18 V; VLIN = 0 V  
IBUS_NO_BAT loss-of-battery bus current VBAT = 0 V; VLIN = 18 V  
750  
-
-
-
-
+10  
A  
A  
V
-
1
VBUSdom  
VBUSrec  
receiver dominant state  
receiver recessive state  
receiver center voltage  
-
0.4VBAT  
-
0.6VBAT  
V
VBUS_CNT  
VBUS_CNT  
=
0.475VBAT 0.5VBAT  
0.525VBAT  
V
(VBUSdom + VBUSrec) / 2  
[2]  
[2]  
VHYS  
receiver hysteresis voltage VHYS = VBUSrec VBUSdom  
-
-
-
0.175VBAT  
1.0  
V
V
VSerDiode  
voltage drop at the serial  
diode  
in pull-up path with Rslave  
ISerDiode = 0.9 mA  
;
0.4  
[2]  
[2]  
VO(dom)  
dominant output voltage  
Normal mode; VTXD = 0 V;  
VBAT = 7.0 V  
-
-
-
-
1.4  
2.0  
V
V
Normal mode; VTXD = 0 V;  
VBAT = 18 V  
Rslave  
CLIN  
slave resistance  
20  
-
30  
-
60  
20  
k  
[2]  
[2]  
capacitance on pin LIN  
with respect to GND  
pF  
Thermal shutdown  
Tj(sd) shutdown junction  
temperature  
150  
-
200  
C  
[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to  
cover the specified temperature and power supply voltage range.  
[2] Not tested in production; guaranteed by design.  
TJA1027  
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Product data sheet  
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LIN 2.2A/SAE J2602 transceiver  
11. Dynamic characteristics  
Table 8.  
BAT = 5 V to 18 V; Tvj = 40 C to +150 C; RL(LIN-VBAT) = 500 ; all voltages are referenced to pin GND; positive currents  
flow into the IC; typical values are given at VBAT = 12 V, unless otherwise specified.[1]  
Dynamic characteristics  
V
Symbol  
Duty cycles  
1  
Parameter  
Conditions  
Min  
Typ  
Max Unit  
[2][4][5]  
[2][4][5]  
[3][4][5]  
[3][4][5]  
[2][4][5]  
[2][4][5]  
[3][4][5]  
[3][4][5]  
duty cycle 1  
Vth(rec)(max) = 0.744 VBAT  
Vth(dom)(max) = 0.581 VBAT  
;
0.396 -  
0.396 -  
-
;
t
bit = 50 s; VBAT = 7 V to 18 V  
Vth(rec)(max) = 0.768 VBAT  
Vth(dom)(max) = 0.6 VBAT  
bit = 50 s; VBAT = 5 V to 7 V  
;
-
;
t
2  
3  
4  
duty cycle 2  
duty cycle 3  
duty cycle 4  
V
V
th(rec)(min) = 0.422 VBAT  
th(dom)(min) = 0.284 VBAT  
;
-
-
-
-
0.581  
0.581  
-
;
tbit = 50 s; VBAT = 7.6 V to 18 V  
th(rec)(min) = 0.405 VBAT  
Vth(dom)(min) = 0.271 VBAT  
tbit = 50 s; VBAT = 5.6 V to 7.6 V  
Vth(rec)(max) = 0.778 VBAT  
Vth(dom)(max) = 0.616 VBAT  
tbit = 96 s; VBAT = 7 V to 18 V  
th(rec)(max) = 0.805 VBAT  
Vth(dom)(max) = 0.637 VBAT  
tbit = 96 s; VBAT = 5 V to 7 V  
th(rec)(min) = 0.389 VBAT  
Vth(dom)(min) = 0.251 VBAT  
tbit = 96 s; VBAT = 7.6 V to 18 V  
th(rec)(min) = 0.372 VBAT  
V
;
;
;
0.417 -  
0.417 -  
;
V
;
-
;
V
;
-
-
-
-
0.590  
0.590  
;
V
Vth(dom)(min) = 0.238 VBAT  
tbit = 96 s; VBAT = 5.6 V to 7.6 V  
Timing characteristics  
[5]  
[5]  
trx_pd  
receiver propagation  
delay  
rising and falling;  
CRXD = 20 pF; RRXD = 2.4 k  
-
-
6
s  
s  
s  
s  
trx_sym  
receiver propagation  
delay symmetry  
CRXD = 20 pF; RRXD = 2.4 k;  
rising edge with respect to falling edge  
2  
30  
2
-
+2  
150  
10  
twake(dom)LIN  
tgotonorm  
LIN dominant wake-up  
time  
Sleep mode  
80  
6
go to normal time  
time period for mode change from  
Sleep or Standby mode to Normal  
mode  
tinit(norm)  
tgotosleep  
normal mode  
initialization time  
7
2
-
20  
10  
s  
s  
go to sleep time  
time period for mode change from  
Normal to Sleep mode  
6
[1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to  
cover the specified temperature and power supply voltage ranges.  
tbusrecmin  
-------------------------------  
[2] 1 3 =  
. Variable tbus(rec)(min) is illustrated in the LIN timing diagram in Figure 5.  
2 tbit  
TJA1027  
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Product data sheet  
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LIN 2.2A/SAE J2602 transceiver  
tbusrecmax  
-------------------------------  
[3] 2 4 =  
. Variable tbus(rec)(max) is illustrated in the LIN timing diagram in Figure 5.  
2 tbit  
[4] Bus load conditions: CBUS = 1 nF and RBUS = 1 k; CBUS = 6.8 nF and RBUS = 660 ; CBUS = 10 nF and RBUS = 500 .  
[5] See timing diagram in Figure 5.  
t
bit  
t
bit  
V
TXD  
t
t
t
bus(rec)(min)  
bus(dom)(max)  
V
V
V
V
th(rec)(max)  
th(dom)(max)  
th(rec)(min)  
th(dom)(min)  
thresholds of  
receiving node 1  
LIN BUS  
signal  
t
bus(dom)(min)  
bus(rec)(max)  
V
BAT  
thresholds of  
receiving node 2  
t
t
t
rx_pdf  
rx_pdr  
rx_pdf  
V
V
RXD  
receiving  
node 1  
t
t
t
rx_pdf  
rx_pdf  
rx_pdr  
RXD  
receiving  
node 2  
015aaa237  
Fig 5. Timing diagram of LIN transceiver duty cycle  
TJA1027  
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Product data sheet  
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NXP Semiconductors  
LIN 2.2A/SAE J2602 transceiver  
12. Application information  
12.1 Application diagram  
V
ECU  
LIN BUS  
LINE  
BATTERY  
+3 V/  
+5 V  
only for  
master node  
V
7
BAT  
1 kΩ  
RXD  
V
DD  
RX0  
TX0  
Px.x  
1
4
2
TXD  
MICRO-  
CONTROLLER  
TJA1027  
SLP_N  
LIN  
6
GND  
5
(1)  
015aaa238  
(1) Master: C = 1 nF; slave: C = 220 pF  
Fig 6. Application diagram  
12.2 ESD robustness according to LIN EMC test specification  
ESD robustness (IEC 61000-4-2) has been tested by an external test house according to  
the LIN EMC test specification (part of Conformance Test Specification Package for  
LIN 2.1, October 10th, 2008). The test report is available on request.  
Table 9.  
Pin  
ESD robustness (IEC 61000-4-2) according to LIN EMC test specification  
Test configuration  
Value  
13  
Unit  
kV  
LIN  
no capacitor connected to LIN pin  
220 pF capacitor connected to LIN pin  
100 nF capacitor connected to VBAT pin  
12  
kV  
VBAT  
> 15  
kV  
12.3 Hardware requirements for LIN interfaces in automotive applications  
The TJA1027 satisfies the "Hardware Requirements for LIN, CAN and FlexRay Interfaces  
in Automotive Applications", Version 1.1, December 2009.  
13. Test information  
13.1 Quality information  
This product has been qualified in accordance with the Automotive Electronics Council  
(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for  
integrated circuits, and is suitable for use in automotive applications.  
TJA1027  
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14. Package outline  
SO8: plastic small outline package; 8 leads; body width 3.9 mm  
SOT96-1  
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
Q
A
2
A
(A )  
3
A
1
pin 1 index  
θ
L
p
L
1
4
e
w
M
detail X  
b
p
0
2.5  
5 mm  
scale  
DIMENSIONS (inch dimensions are derived from the original mm dimensions)  
A
(1)  
(1)  
(2)  
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.  
0.25  
0.10  
1.45  
1.25  
0.49  
0.36  
0.25  
0.19  
5.0  
4.8  
4.0  
3.8  
6.2  
5.8  
1.0  
0.4  
0.7  
0.6  
0.7  
0.3  
mm  
1.27  
0.05  
1.05  
0.041  
1.75  
0.25  
0.01  
0.25  
0.01  
0.25  
0.1  
8o  
0o  
0.010 0.057  
0.004 0.049  
0.019 0.0100 0.20  
0.014 0.0075 0.19  
0.16  
0.15  
0.244  
0.228  
0.039 0.028  
0.016 0.024  
0.028  
0.012  
inches 0.069  
0.01 0.004  
Notes  
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.  
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-18  
SOT96-1  
076E03  
MS-012  
Fig 7. Package outline SOT96-1 (SO8)  
TJA1027  
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Product data sheet  
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NXP Semiconductors  
LIN 2.2A/SAE J2602 transceiver  
HVSON8: plastic thermal enhanced very thin small outline package; no leads;  
8 terminals; body 3 x 3 x 0.85 mm  
SOT782-1  
X
D
B
A
E
A
A
1
c
detail X  
terminal 1  
index area  
e
1
C
terminal 1  
index area  
v
C
C
A
B
e
b
y
1
y
w
C
1
4
L
K
E
h
8
5
D
h
0
1
2 mm  
L
scale  
Dimensions  
(1)  
Unit  
A
A
b
c
D
D
h
E
E
e
e
1
K
v
w
y
y
1
1
h
max 1.00 0.05 0.35  
mm nom 0.85 0.03 0.30 0.2 3.00 2.40 3.00 1.60 0.65 1.95 0.30 0.40 0.1 0.05 0.05 0.1  
min 0.80 0.00 0.25 2.90 2.35 2.90 1.55 0.25 0.35  
3.10 2.45 3.10 1.65  
0.35 0.45  
Note  
1. Plastic or metal protrusions of 0.075 maximum per side are not included.  
sot782-1_po  
References  
Outline  
version  
European  
projection  
Issue date  
IEC  
- - -  
JEDEC  
JEITA  
- - -  
09-08-25  
09-08-28  
SOT782-1  
MO-229  
Fig 8. Package outline SOT782-1 (HVSON8)  
TJA1027  
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Product data sheet  
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LIN 2.2A/SAE J2602 transceiver  
15. Handling information  
All input and output pins are protected against ElectroStatic Discharge (ESD) under  
normal handling. When handling ensure that the appropriate precautions are taken as  
described in JESD625-A or equivalent standards.  
16. Soldering of SMD packages  
This text provides a very brief insight into a complex technology. A more in-depth account  
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow  
soldering description”.  
16.1 Introduction to soldering  
Soldering is one of the most common methods through which packages are attached to  
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both  
the mechanical and the electrical connection. There is no single soldering method that is  
ideal for all IC packages. Wave soldering is often preferred when through-hole and  
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not  
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high  
densities that come with increased miniaturization.  
16.2 Wave and reflow soldering  
Wave soldering is a joining technology in which the joints are made by solder coming from  
a standing wave of liquid solder. The wave soldering process is suitable for the following:  
Through-hole components  
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board  
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless  
packages which have solder lands underneath the body, cannot be wave soldered. Also,  
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,  
due to an increased probability of bridging.  
The reflow soldering process involves applying solder paste to a board, followed by  
component placement and exposure to a temperature profile. Leaded packages,  
packages with solder balls, and leadless packages are all reflow solderable.  
Key characteristics in both wave and reflow soldering are:  
Board specifications, including the board finish, solder masks and vias  
Package footprints, including solder thieves and orientation  
The moisture sensitivity level of the packages  
Package placement  
Inspection and repair  
Lead-free soldering versus SnPb soldering  
16.3 Wave soldering  
Key characteristics in wave soldering are:  
TJA1027  
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Process issues, such as application of adhesive and flux, clinching of leads, board  
transport, the solder wave parameters, and the time during which components are  
exposed to the wave  
Solder bath specifications, including temperature and impurities  
16.4 Reflow soldering  
Key characteristics in reflow soldering are:  
Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to  
higher minimum peak temperatures (see Figure 9) than a SnPb process, thus  
reducing the process window  
Solder paste printing issues including smearing, release, and adjusting the process  
window for a mix of large and small components on one board  
Reflow temperature profile; this profile includes preheat, reflow (in which the board is  
heated to the peak temperature) and cooling down. It is imperative that the peak  
temperature is high enough for the solder to make reliable solder joints (a solder paste  
characteristic). In addition, the peak temperature must be low enough that the  
packages and/or boards are not damaged. The peak temperature of the package  
depends on package thickness and volume and is classified in accordance with  
Table 10 and 11  
Table 10. SnPb eutectic process (from J-STD-020D)  
Package thickness (mm) Package reflow temperature (C)  
Volume (mm3)  
< 350  
235  
350  
220  
< 2.5  
2.5  
220  
220  
Table 11. Lead-free process (from J-STD-020D)  
Package thickness (mm) Package reflow temperature (C)  
Volume (mm3)  
< 350  
260  
350 to 2000  
> 2000  
260  
< 1.6  
260  
250  
245  
1.6 to 2.5  
> 2.5  
260  
245  
250  
245  
Moisture sensitivity precautions, as indicated on the packing, must be respected at all  
times.  
Studies have shown that small packages reach higher temperatures during reflow  
soldering, see Figure 9.  
TJA1027  
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LIN 2.2A/SAE J2602 transceiver  
maximum peak temperature  
= MSL limit, damage level  
temperature  
minimum peak temperature  
= minimum soldering temperature  
peak  
temperature  
time  
001aac844  
MSL: Moisture Sensitivity Level  
Fig 9. Temperature profiles for large and small components  
For further information on temperature profiles, refer to Application Note AN10365  
“Surface mount reflow soldering description”.  
17. Soldering of HVSON packages  
Section 16 contains a brief introduction to the techniques most commonly used to solder  
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON  
leadless package ICs can found in the following application notes:  
AN10365 ‘Surface mount reflow soldering description”  
AN10366 “HVQFN application information”  
TJA1027  
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LIN 2.2A/SAE J2602 transceiver  
18. Revision history  
Table 12. Revision history  
Document ID  
TJA1027 v.2  
Modifications:  
Release date  
20130424  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
TJA1027 v.1  
text in Title, Section 1, Section 2.1, Section 7.1 revised to include LIN 2.2A compliance  
text in Section 7.1 revised to be consistent with TJA1029  
Figure 2: revised/resized  
Table 3, Table note 1: revised  
Figure 4: revised  
Table 7: revised measurement conditions for parameter IBUS_NO_BAT  
Section 13.1: text revised  
TJA1027 v.1  
20111020  
Product data sheet  
-
-
TJA1027  
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19. Legal information  
19.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
Suitability for use in automotive applications — This NXP  
19.2 Definitions  
Semiconductors product has been qualified for use in automotive  
applications. Unless otherwise agreed in writing, the product is not designed,  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors and its suppliers accept no liability for  
inclusion and/or use of NXP Semiconductors products in such equipment or  
applications and therefore such inclusion and/or use is at the customer's own  
risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
19.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information. NXP Semiconductors takes no  
responsibility for the content in this document if provided by an information  
source outside of NXP Semiconductors.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
TJA1027  
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LIN 2.2A/SAE J2602 transceiver  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
19.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
20. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
TJA1027  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 2 — 24 April 2013  
23 of 24  
 
 
TJA1027  
NXP Semiconductors  
LIN 2.2A/SAE J2602 transceiver  
21. Contents  
1
General description. . . . . . . . . . . . . . . . . . . . . . 1  
18  
Revision history . . . . . . . . . . . . . . . . . . . . . . . 21  
2
2.1  
2.2  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
19  
Legal information . . . . . . . . . . . . . . . . . . . . . . 22  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22  
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
19.1  
19.2  
19.3  
19.4  
3
4
5
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
20  
21  
Contact information . . . . . . . . . . . . . . . . . . . . 23  
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4  
7
7.1  
7.2  
Functional description . . . . . . . . . . . . . . . . . . . 5  
LIN 2.x/SAE J2602 compliant. . . . . . . . . . . . . . 5  
Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5  
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Transceiver wake-up . . . . . . . . . . . . . . . . . . . . 8  
Remote wake-up via the LIN bus . . . . . . . . . . . 8  
Wake-up via pin SLP_N . . . . . . . . . . . . . . . . . . 8  
Operation during automotive cranking pulses . 8  
Operation when supply voltage is outside  
7.2.1  
7.2.2  
7.2.3  
7.2.4  
7.3  
7.3.1  
7.3.2  
7.4  
7.5  
specified operating range . . . . . . . . . . . . . . . . . 8  
Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 9  
7.6  
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10  
Thermal characteristics . . . . . . . . . . . . . . . . . 10  
Static characteristics. . . . . . . . . . . . . . . . . . . . 11  
Dynamic characteristics . . . . . . . . . . . . . . . . . 13  
9
10  
11  
12  
12.1  
12.2  
Application information. . . . . . . . . . . . . . . . . . 15  
Application diagram . . . . . . . . . . . . . . . . . . . . 15  
ESD robustness according to LIN EMC test  
specification . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Hardware requirements for LIN interfaces in  
automotive applications . . . . . . . . . . . . . . . . . 15  
12.3  
13  
13.1  
14  
Test information. . . . . . . . . . . . . . . . . . . . . . . . 15  
Quality information . . . . . . . . . . . . . . . . . . . . . 15  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16  
Handling information. . . . . . . . . . . . . . . . . . . . 18  
15  
16  
Soldering of SMD packages . . . . . . . . . . . . . . 18  
Introduction to soldering . . . . . . . . . . . . . . . . . 18  
Wave and reflow soldering . . . . . . . . . . . . . . . 18  
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 18  
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 19  
16.1  
16.2  
16.3  
16.4  
17  
Soldering of HVSON packages. . . . . . . . . . . . 20  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2013.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 24 April 2013  
Document identifier: TJA1027  
 

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