TEA1202TS/N2,118 [NXP]
IC 5 A BATTERY CHARGE CONTROLLER, 720 kHz SWITCHING FREQ-MAX, PDSO20, 4.40 MM, PLASTIC, MO-152, SOT-266-1, SSOP-20, Switching Regulator or Controller;
| 型号： | TEA1202TS/N2,118 |
| 厂家： | 
NXP |
| 描述： | IC 5 A BATTERY CHARGE CONTROLLER, 720 kHz SWITCHING FREQ-MAX, PDSO20, 4.40 MM, PLASTIC, MO-152, SOT-266-1, SSOP-20, Switching Regulator or Controller 信息通信管理 开关 光电二极管 |
| 文件： | 总28页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TEA1202TS
0.95 V starting power unit
Preliminary specification
2002 Mar 14
Supersedes data of 2000 Jun 08
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
CONTENTS
14
PACKAGE OUTLINE
15
SOLDERING
1
2
3
4
5
6
7
8
FEATURES
15.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
APPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION
QUICK REFERENCE DATA
BLOCK DIAGRAM
15.2
15.3
15.4
15.5
Suitability of surface mount IC packages for
wave and reflow soldering methods
PINNING
16
17
18
DATA SHEET STATUS
DEFINITIONS
FUNCTIONAL DESCRIPTION
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
Control mechanism
Synchronous rectification
Start-up
Undervoltage lockout
Shut-down
Power switches
Temperature protection
Current limiters
External synchronization and PWM-only mode
Behaviour at input voltage exceeding the
specified range
DISCLAIMERS
8.11
8.12
Low drop-out voltage regulators
Low battery detector
9
LIMITING VALUES
10
11
12
13
THERMAL CHARACTERISTICS
QUALITY SPECIFICATION
CHARACTERISTICS
APPLICATION INFORMATION
13.1
External component selection
Inductor L1
DC-to-DC input capacitor C1
DC-to-DC output capacitor C2
Diode D1
Feedback resistors R1 and R2
Current limiting resistor R10
Reference voltage decoupling capacitor C5
LDO output capacitors C3 and C4
LDO feedback resistors R3, R4, R5 and R6
Low battery detector components R7, R8, R9
and C6
13.1.1
13.1.2
13.1.3
13.1.4
13.1.5
13.1.6
13.1.7
13.1.8
13.1.9
13.1.10
13.2
13.3
Application recommendations
Typical performance characteristics
2002 Mar 14
2
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
1
FEATURES
3
GENERAL DESCRIPTION
• Fully integrated battery power unit, including complete
DC-to-DC converter circuit, two Low Drop-Out voltage
regulators (LDOs) and a battery low detector
The TEA1202TS is a fully integrated battery power unit
including a high efficiency DC-to-DC converter which runs
from a single-cell NiCd or NiMH battery, two low drop-out
voltage regulators and a low battery detector. The circuit
can be arranged in many ways to optimize the application
circuit of a power supply system. Therefore, most inputs
and outputs are separated, the DC-to-DC converter can be
arranged for upconversion or downconversion and the
regulators can also be used as power switches. One
regulator can be used completely independent of the rest
of the system, and the low battery detector can be
configured for several types of batteries. Accurate low
battery detection is possible while all other blocks are
switched off.
• Configurable for 1, 2 or 3-cell Nickel-Cadmium (NiCd)
or Nickel Metal Hybrid (NiMH) batteries and 1 Lithium
Ion (Li-Ion) battery
• Guaranteed DC-to-DC converter start-up from 1-cell
NiCd or NiMH battery, even with a load current
• Upconversion or downconversion
• Internal power MOSFETs featuring a low RDSon of
approximately 0.1 Ω
• Synchronous rectification for high efficiency
• Soft start
The DC-to-DC converter features efficient, compact and
dynamic power conversion using a digital control concept
comparable with Pulse Width Modulation (PWM) and
Pulse Frequency Modulation (PFM), integrated CMOS
power switches with a very low RDSon and fully
synchronous rectification.
• PWM-only operating option
• LDO drop-out voltage of 30 mV at 50 mA
• Both LDOs can also be used as low-ohmic power
switches
• Stable LDO performance with ceramic capacitors
• At start-up, LDO1 can be loaded
The device operates at a switching frequency of 600 kHz
which enables the use of external components with
minimum size. The switching frequency can be
synchronized to an external high frequency clock signal.
Optionally, the device can be kept in PWM control mode
only. Deadlock is prevented by an on-chip undervoltage
lockout circuit.
• Stand-alone low battery detector requires no additional
supply voltage
• Low battery detection level at 0.90 V, externally
adjustable to a higher level
• Adjustable output voltages
• Shut-down function
Active current limiting enables efficient conversion in
pulsed-load systems such as Global System for Mobile
communication (GSM) and Digital Enhanced Cordless
Telecommunications (DECT).
• Small outline package
• Advanced 0.6 µm BICMOS process.
Both LDOs show a low drop-out voltage and are inherently
stable, even when ceramic capacitors with a low ESR
value are applied at the outputs. Usage of the LDOs as
low-ohmic switches is also possible.
2
APPLICATIONS
• Cellular phones
• Cordless phones
LDO1 can be loaded at start-up.
• Personal Digital Assistants (PDAs)
• Portable audio players
• Pagers
The low battery detector has a built-in detection level
which is optimum for a single-cell NiCd or NiMH battery.
Higher battery voltages can be translated to this single-cell
level by an additional built-in LDO circuit.
• Mobile equipment.
4
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TEA1202TS
SSOP20
plastic shrink small outline package; 20 leads; body width 4.4 mm
SOT266-1
2002 Mar 14
3
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
5
QUICK REFERENCE DATA
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
DC-to-DC converter
UPCONVERSION
VI(up)
input voltage
VI(start)
VO(uvlo)
0.93
−
5.50
5.50
1.00
2.4
V
V
V
V
VO(up)
VI(start)
VO(uvlo)
output voltage
−
start-up input voltage
undervoltage lockout voltage
IL < 10 mA
0.96
2.2
note 1
2.0
DOWNCONVERSION
VI(dwn)
input voltage
output voltage
VO(uvlo)
1.30
−
−
5.50
5.50
V
V
VO(dwn)
CURRENT LEVELS
Iq(DCDC)
Ishdwn
quiescent current at pin UPOUT/DNIN
−
−
−
110
65
−
−
µA
µA
A
current in shut-down mode
VLBI1 = VI(up) = 1.2 V
−
ILX(max)
maximum continuous current at
pins LX1 and LX2
Tamb = 80 °C
1.0
∆Ilim
current limit deviation
Ilim set to 1.0 A
upconversion
−12
−12
−
−
+12
+12
%
%
downconversion
POWER MOSFETS
RDSon(N) drain-to-source on-state resistance
NFET; IDS = 100 mA;
Tj = 27 °C
−
−
110
125
200
250
mΩ
mΩ
RDSon(P)
drain-to-source on-state resistance
PFET; IDS = −100 mA;
Tj = 27 °C
EFFICIENCY
η
efficiency upconversion
see Fig.10; VO up to 3.3 V
VI = 1.2 V; IL = 100 mA
VI = 2.4 V; IL = 200 mA
−
−
84
92
−
−
%
%
TIMING
fsw
switching frequency
PWM mode
480
6
600
13
720
20
−
kHz
MHz
ms
fi(sync)
tstart
synchronization clock input frequency
start-up time
−
10
2002 Mar 14
4
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Low drop-out voltage regulators
VLDO
Vdropout
ILDO
output voltage range
drop-out voltage
output current
VLDO < V4 + 0.3 V
1.30
−
5.50
45
V
ILDO = 50 mA
in regulation
−
−
−
30
−
mV
mA
mΩ
250
750
RDSon(LDO1) LDO1 drain-to-source on-state
resistance
VI(LDO1) = 5 V; VFB1 < 0.4 V;
ILDO1 = 50 mA
500
General characteristics
Vref
reference voltage
1.165 1.190 1.215
V
Note
1. The undervoltage lockout level shows wide specification limits since it decreases at increasing temperature. When
the temperature increases, the minimum supply voltage of the digital control part of the IC decreases and therefore
the correct operation of this function is guaranteed over the whole temperature range. The undervoltage lockout level
is measured at pin UPOUT/DNIN.
2002 Mar 14
5
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
6
BLOCK DIAGRAM
3
SHDWN2
11
IN2
12
V
LBI2
ref
10
OUT2
LDO2
13
9
LBI1
FB2
TEA1202TS
SHDWN0
LOW BATTERY
DETECTOR
V
ref
6
7
OUT1
FB1
LDO1
14
LBO
P-type POWER FET
1
4
LX1
UPOUT/DNIN
20
LX2
INTERNAL
SUPPLY
sense FET
8
5
GND
ILIM
START-UP
CIRCUIT
16
V
ref
CONTROL LOGIC
AND
MODE GEARBOX
FB0
CURRENT LIMIT
COMPARATOR
V
ref
N-type
POWER
FET
TEMPERATURE
PROTECTION
15
REFERENCE
VOLTAGE
V
TIME
ref
sense
FET
COUNTER
DIGITAL CONTROLLER
19
13 MHz
OSCILLATOR
SYNC
GATE
17
18
2
MGU062
GND0
SYNC/PWM SHDWN0 U/D
Fig.1 Block diagram.
2002 Mar 14
6
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
7
PINNING
SYMBOL
PIN
DESCRIPTION
LX1
1
2
3
4
inductor connection 1
DC-to-DC shut-down input
LDO2 shut-down input
SHDWN0
SHDWN2
UPOUT/DNIN
up mode DC-to-DC output;
down mode DC-to-DC input
handbook, halfpage
LX1
1
2
3
4
5
6
7
8
9
20 LX2
ILIM
5
current limiting resistor
connection
SHDWN0
SHDWN2
UPOUT/DNIN
ILIM
19 U/D
18 SYNC/PWM
17 GND0
16 FB0
OUT1
FB1
6
7
8
9
LDO1 output
LDO1 feedback input
internal supply ground
LDO2 feedback input
GND
FB2
TEA1202TS
OUT1
15 V
ref
OUT2
IN2
10 LDO2 output
FB1
14 LBO
13 LBI1
12 LBI2
11 IN2
11 LDO2 input
GND
LBI2
12 low battery detector input 2
13 low battery detector input 1
14 low battery detector output
15 reference voltage
FB2
LBI1
OUT2 10
LBO
Vref
MGU060
FB0
16 DC-to-DC feedback input
17 DC-to-DC converter ground
GND0
SYNC/PWM
18 synchronization clock input or
PWM-only selection input
U/D
LX2
19 conversion mode selection input
20 inductor connection 2
Fig.2 Pin configuration.
8
FUNCTIONAL DESCRIPTION
Control mechanism
When the output voltage reaches one of the window
borders, the digital controller immediately reacts by
adjusting the pulse width and inserting a current step in
such a way that the output voltage stays within the window
with higher or lower current capability. This approach
enables very fast reaction to load variations. Figure 3
shows the response of the converter to a sudden load
increase. The upper trace shows the output voltage.
8.1
The DC-to-DC converter of the TEA1202TS is able to
operate in PFM (discontinuous conduction) or PWM
(continuous conduction) operating mode. All switching
actions are completely determined by a digital control
circuit which uses the output voltage level as its control
input. This novel digital approach enables the use of a new
pulse width and frequency modulation scheme, which
ensures optimum power efficiency over the complete
range of operation of the converter.
The ripple on top of the DC level is a result of the current
in the output capacitor, which changes in sign twice per
cycle, times the internal Equivalent Series Resistance
(ESR) of the capacitor. After each ramp-down of the
inductor current, i.e. when the ESR effect increases the
output voltage, the converter determines what to do in the
next cycle. As soon as more load current is taken from the
output the output voltage starts to decay.
When high output power is requested, the device will
operate in PWM (continuous conduction) operating mode.
This results in minimum AC currents in the circuit
components and hence optimum efficiency, minimum
costs and low EMC. In this operating mode, the output
voltage is allowed to vary between two predefined voltage
levels. As long as the output voltage stays within this
so-called window, switching continues in a fixed pattern.
2002 Mar 14
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Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
load increase
start corrective action
V
o
high window limit
low window limit
time
I
L
MGK925
time
Fig.3 Response to load increase.
maximum positive spread of V
O
V
wdw(high)
upper specification limit
2%
V
wdw(low)
+2%
V
wdw(high)
V
2%
V
O (typ)
wdw(low)
−2%
V
wdw(high)
2%
lower specification limit
V
typical situation
wdw(low)
maximum negative spread of V
MGU576
O
Fig.4 Output voltage window spread.
8
2002 Mar 14
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
When the output voltage becomes lower than the low limit
of the window, a corrective action is taken by a ramp-up of
the inductor current during a much longer time. As a result,
the DC current level is increased and normal PWM control
can continue. The output voltage (including ESR effect) is
again within the predefined window.
8.4
Undervoltage lockout
As a result of too high a load or disconnection of the input
power source, the output voltage can drop so low that
normal regulation cannot be guaranteed. In this event, the
device switches back to start-up mode. If the output
voltage drops even further, switching is stopped
completely.
Figure 4 shows the spread of the output voltage window.
The absolute value is mostly dependent on spread, while
the actual window size [Vwdw(high) − Vwdw(low)] is not
affected. For one specific device, the output voltage will
not vary more than 2% (typical value).
8.5
Shut-down
When the shut-down input is set HIGH, the DC-to-DC
converter disables both switches and power consumption
is reduced to a few microamperes.
In low output power situations, the TEA1202TS will switch
over to PFM (discontinuous conduction) operating mode.
In this mode, regulation information from an earlier PWM
operating mode is used. This results in optimum inductor
peak current levels in the PFM mode, which are slightly
larger than the inductor ripple current in the PWM mode.
As a result, the transition between PFM and PWM mode is
optimum under all circumstances. In the PFM mode the
TEA1202TS regulates the output voltage to the high
window limit as shown in Fig.3.
8.6
Power switches
The power switches in the IC are one N-type and one
P-type power MOSFET, both having a typical
drain-to-source resistance of 100 mΩ. The maximum
continuous current in the power switches is 1.0 A at
Tamb = 80 °C.
8.7 Temperature protection
8.2
Synchronous rectification
When the DC-to-DC converter operates in the PWM
mode, and the die temperature gets too high (typical value
is 160 °C), the converter and both LDOs stop operating.
They resume operation when the die temperature falls
below 90 °C again. As a result, low frequency cycling
between the on and off state will occur. It should be noted
that in the event of device temperatures at the cut-off limit,
the application differs strongly from maximum
specifications.
For optimum efficiency over the whole load range,
synchronous rectifiers inside the TEA1202TS ensure that
during the whole second switching phase, all inductor
current will flow through the low-ohmic power MOSFETs.
Special circuitry is included which detects when the
inductor current reaches zero. Following this detection, the
digital controller switches off the power MOSFET and
proceeds with regulation.
8.8
Current limiters
8.3
Start-up
If the current in one of the power switches exceeds the
programmed limit in the PWM mode, the current ramp is
stopped immediately and the next switching phase is
entered. Current limiting is required to keep power
conversion efficient during temporary high loads.
Furthermore, current limiting protects the IC against
overload conditions, inductor saturation, etc.
Start-up from low input voltage in the boost mode is
realized by an independent start-up oscillator, which starts
switching the N-type power MOSFET as soon as the
low-battery detector detects a sufficiently high voltage.
The inductor current is limited internally to ensure
soft-starting. The switch actions of the start-up oscillator
will increase the output voltage. As soon as the output
voltage is high enough for normal regulation, the digital
control system takes control over the power MOSFETs.
The current limiting level is set by an external resistor
which must be connected between pin ILIM and ground for
downconversion, or between pins ILIM and UPOUT/DNIN
for upconversion.
2002 Mar 14
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Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
8.9
External synchronization and PWM-only mode
Both LDOs are protected from high temperature
(see Section 8.7).
If an external high-frequency clock or a HIGH level is
applied to pin SYNC/PWM, the TEA1202TS will use PWM
regulation independent of the load applied.
Next to normal LDO functions, both regulators can be
switched off or can be used as switches. Each regulator
will act as a low-ohmic switch in the on-state when its
feedback input is connected to ground. When the
feedback input is higher than 2 V, the regulator will make
its power FET high-ohmic. So the feedback inputs of the
regulators can be used as digital inputs which make the
LDOs behave as switches.
In the event a high-frequency clock is applied, the
switching frequency in the PWM mode will be exactly that
frequency divided by 22. In the PWM mode the quiescent
current of the device increases.
In the event that no external synchronization or PWM
mode selection is necessary, pin SYNC/PWM must be
connected to ground.
8.12 Low battery detector
The low battery detector is an autonomous circuit which
can work at an input voltage down to 0.90 V. It is always
on, even when all other blocks are in the shut-down mode.
8.10 Behaviour at input voltage exceeding the
specified range
In general, an input voltage exceeding the specified range
is not recommended since instability may occur. There are
two exceptions:
The detector has two inputs: the input on pin LBI1 is tuned
to accept a single-cell NiCd or NiMH battery voltage
directly, while the input on pin LBI2 can detect a two-cell
NiCd or NiMH battery voltage or higher voltage. The
detection level of the input on pin LBI2 can be set by using
a voltage divider between the battery voltage, pin LBI2 and
ground. Hysteresis is included for proper operating.
Furthermore, a capacitor of 10 nF (typical value) must be
connected between pin LBI1 and ground when the input
on pin LBI2 is used.
• Upconversion: at an input voltage higher than the target
output voltage, but up to 5.5 V, the converter will stop
switching and the external Schottky diode will take over.
The output voltage will equal the input voltage minus the
diode voltage drop. Since all current flows through the
external diode in this situation, the current limiting
function is not active.
In the PWM mode, the P-type power MOSFET is always
on when the input voltage exceeds the target output
voltage. The internal synchronous rectifier ensures that
the inductor current does not fall below zero. As a result,
the achieved efficiency is higher in this situation than
standard PWM-controlled converters achieve.
The output of the low battery detector on pin LBO is an
open-collector output. The output is high (i.e. no current is
sunk by the collector) when the input voltage of the
detector is below the lower detection level.
• Downconversion: when the input voltage is lower than
the target output voltage, but higher than 2.2 V, the
P-type power MOSFET will stay conducting resulting in
an output voltage being equal to the input voltage minus
some resistive voltage drop. The current limiting
function remains active.
8.11 Low drop-out voltage regulators
The low drop-out voltage regulators are functionally equal
apart from the shut-down mechanism: LDO2 can be
controlled separately by pin SHDWN2, while LDO1 is
controlled by pin SHDWN0 like the DC-to-DC converter.
The input voltage of each LDO must be 250 mV (at
ILDO = 50 mA) higher than its output voltage to achieve full
specification on e.g. ripple rejection. However, the parts
will function like an LDO down to a margin of 45 mV (at
ILDO = 50 mA) between input and output: the so-called
drop-out voltage. At a lower margin between input and
output, the LDOs will behave like a resistor.
2002 Mar 14
10
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
9
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER CONDITIONS
Vn voltage on any pin shut-down mode
MIN.
−0.2
MAX.
+6.5
UNIT
V
V
operating mode
−0.2
−40
−20
−40
+5.5
+150
+80
Tj
junction temperature
°C
°C
°C
V
Tamb
Tstg
Ves
ambient temperature
storage temperature
+125
electrostatic handling voltage
notes 1 and 2
Class II
Notes
1. ESD specification is in accordance with the JEDEC standard:
a) Human Body Model (HBM) tests are carried out by discharging a 100 pF capacitor through a 1.5 kΩ series
resistor.
b) Machine Model (MM) tests are carried out by discharging a 200 pF capacitor via a 0.75 µH series inductor.
2. Exception is pin ILIM: 1000 V HBM.
10 THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient in free air
140
K/W
11 QUALITY SPECIFICATION
In accordance with “SNW-FQ-611D”.
12 CHARACTERISTICS
Tamb = −20 to +80 °C; all voltages are measured with respect to ground; positive currents flow into the IC; unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DC-to-DC converter
UPCONVERSION; pin U/D = LOW
VI(up)
input voltage
VI(start)
VO(uvlo)
0.93
−
−
5.50
V
V
V
V
VO(up)
VI(start)
VO(uvlo)
output voltage
5.50
1.00
2.4
start-up input voltage
undervoltage lockout voltage
IL < 10 mA
0.96
2.2
note 1
2.0
DOWNCONVERSION; pin U/D = HIGH
VI(dwn)
input voltage
note 2
VO(uvlo)
1.30
−
−
5.50
5.50
V
V
VO(dwn)
output voltage
REGULATION
∆VO(wdw)
output voltage window size as a PWM mode
function of output voltage
1.5
2.0
2.5
%
2002 Mar 14
11
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CURRENT LEVELS
Iq(DCDC)
quiescent current at
pin UPOUT/DNIN
note 3
−
110
−
µA
Ishdwn
Ilim(max)
∆Ilim
current in shut-down mode
maximum current limit
current limit deviation
VLBI1 = VI(up) = 1.2 V
−
−
65
5
−
−
µA
A
Ilim set to 1.0 A; note 4
upconversion
−12
−12
−
−
−
−
+12
+12
1.0
%
%
A
downconversion
ILX(max)
maximum continuous current at Tamb = 80 °C
pins LX1 and LX2
POWER MOSFETS
RDS(on)(N) drain-to-source on-state
NFET; IDS = 100 mA;
Tj = 27 °C
−
−
110
125
200
250
mΩ
mΩ
resistance
RDS(on)(P)
drain-to-source on-state
resistance
PFET; IDS = −100 mA;
Tj = 27 °C
EFFICIENCY
η
efficiency upconversion
see Fig.10; VO up to 3.3 V
VI = 1.2 V; IL = 100 mA
VI = 2.4 V; IL = 200 mA
−
−
84
92
−
−
%
%
TIMING
fsw
switching frequency
PWM mode
note 6
480
6
600
13
720
20
kHz
fi(sync)
synchronization clock input
frequency
MHz
tstart
start-up time
−
10
−
ms
V
DIGITAL INPUT LEVELS
VlL(n)
LOW-level input voltage on all
0
−
0.4
digital pins
VIH(n)
HIGH-level input voltage
pin SYNC/PWM
note 7
0.55V4
0.9
−
−
−
V4 + 0.3 V
V4 + 0.3 V
V4 + 0.3 V
pins SHDWN0 and SHDWN2
all other digital input pins
V4 − 0.4
Low drop-out voltage regulators; note 8
VI(LDO1)
VI(LDO2)
VLDO
output voltage range pin LDO1
output voltage range pin LDO2
output voltage range
VO(uvlo)
1.8
−
−
−
5.50
V
V4 + 0.3 V
VLDO < V4 + 0.3 V
note 9
1.30
5.50
V
Vdropout
drop-out voltage
I
LDO = 50 mA
LDO = 150 mA
−
30
90
−
45
135
−
mV
mV
mV
mV
I
−
Vdrop
minimum drop voltage for
ILDO = 50 mA
ILDO = 150 mA
250
500
functionality within specification
−
−
2002 Mar 14
12
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
SYMBOL
ILDO
PARAMETER
output current
CONDITIONS
in regulation
MIN.
TYP.
MAX.
250
UNIT
mA
−
−
−
∆VLDO
output voltage accuracy
VI − VLDO = 1 V;
−3.5
+3.5
%
ILDO = 1 mA; note 10
∆Vline
line voltage regulation
1 mA < ILDO < 150 mA;
note 11
(VI − VLDO) > Vdrop < 4.5 V
−
−
−
−
0.1
%/V
4.5 V < (VI − VLDO) < 5.5 V −
0.2
%/V
∆Vload
load voltage regulation with
changing load current
10 mA < ILDO < 150 mA;
note 12
−
−0.02
%/mA
PSRR
tres(up)
power supply ripple rejection
note 13
−
−
40
−
dB
response time after a positive
load step
IO = 0.5 mA to 50 mA;
CL = 2.2 µF;
−
20
µs
VO(error) < ±0.1% of end
value
tres(down)
response time after a negative IO = 50 mA to 0.5 mA;
−
−
100
µs
load step
CL = 2.2 µF;
VO(error) < ±0.1% of end
value
Iq(LDO)
quiescent current
shut-down current
−
−
50
−
µA
µA
Ishdwn(LDO)
−
1
SWITCH CIRCUIT
RDS(on)(LD01) LD01 drain-to-source
resistance
LD01 in switched-on state;
Vl(LDO1) = 5 V; VFB1 < 0.4 V
−
−
−
−
500
300
−
750
450
0.40
0.40
mΩ
mΩ
A
RDS(on)(LD02) LD02 drain-to-source
resistance
LD02 in switched-on state;
Vl(LDO2) = 5 V; VFB2 < 0.4 V
IO(max)(LDO1) LDO1 maximum output current LDO1 in switched-on state;
VFB1 > 0.4 V
IO(max)(LDO2) LDO2 maximum output current LDO2 in switched-on state;
VFB2 > 0.4 V
−
A
Low battery detector
tt(HL)
transition time
falling Vbat
falling Vbat
−
2
−
µs
DETECTION INPUT PIN LBI1
Vdet
low battery detection level
0.87
−
0.90
20
0
0.93
−
V
Vhys
low battery detection hysteresis
mV
mV/K
TCVdet
temperature coefficient of
detection level
−
−
TCVhys
temperature coefficient of
detection hysteresis
−
0.175
−
−
mV/K
DETECTION OUTPUT PIN LB0
IO(sink)
output sink current
15
−
µA
2002 Mar 14
13
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
General characteristics
Vref
Iq
reference voltage
1.165
1.190
270
1.215
V
quiescent current at
pin UPOUT/DNIN
all blocks operating
−
−
µA
Tamb
Tmax
ambient temperature
−20
+25
160
+80
170
°C
°C
internal temperature for cut-off
150
Notes
1. The undervoltage lockout level shows wide specification limits since it decreases at increasing temperature. When
the temperature increases, the minimum supply voltage of the digital control part of the IC decreases and therefore
the correct operation of this function is guaranteed over the whole temperature range. The undervoltage lockout level
is measured at pin UPOUT/DNIN.
2. When VI(dwn) is lower than the target output voltage but higher than 2.2 V, the P-type power MOSFET will remain
conducting (duty factor is 100%), resulting in VO(dwn) following VI(dwn)
.
3. The quiescent current is specified as the current in to pin UPOUT/DNIN (pin 4) in the upconversion configuration at
VI = 1.20 V and VO = 3.30 V, using L1 = 6.8 µH, R1 = 150 kΩ and R2 = 91 kΩ.
4. The current limit is defined by resistor R10. This resistor must have 1% accuracy.
5. The specified efficiency is valid when using an output capacitor having an ESR of 0.1 Ω and an inductor of 6.8 µH
with an ESR of 0.05 Ω and a sufficient saturation current level.
6. The specified start-up time is the time between the connection of a 1.20 V input voltage source and the moment the
output reaches 3.30 V. The output capacitance equals 100 µF, the inductance equals 6.8 µH and no load is present.
7. V4 is the voltage at pin UPOUT/DNIN. If the applied HIGH-level voltage is less than V4 − 1 V, the quiescent current
of the device will increase.
8. Take care regarding total dissipation if output current ILDO > 50 mA and drop voltage Vdrop > 2 V.
9. The drop-out voltage is defined as the voltage between the input and the output of the LDO when the output voltage
has dropped 100 mV below its nominal value. The drop-out voltage is measured while the LDO input voltage is
decreasing.
10. The output voltage of each LDO is defined by external feedback resistors. These resistors must have 1% accuracy.
∆VLDO
11. ∆Vline
12. ∆Vload
=
× 100 %/V.
----------------------------
V
LDO × ∆VI
∆VLDO
=
× 100 %/mA.
----------------------------------
V
LDO × ∆ILDO
13. Measured with a sine wave at fi = 100 Hz to 1 MHz, Vi = 100 mV (RMS), CL = 2.2 µF and ILDO = 10 mA.
2002 Mar 14
14
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
13 APPLICATION INFORMATION
DC/DC
output
DC/DC
UPCONVERTER
regulator 1
output
LDO1
LDO2
TEA1202TS
regulator 2
output
LOW BATTERY
DETECTOR
low battery
detection
equivalent block diagram
D1
L1
R10
ILIM
LX1
1
5
4
UPOUT/DNIN
DC/DC
output
LX2
IN2
20
11
C1
R1
FB0
C2
C3
C4
16
R2
LBI1
LBI2
LBO
U/D
13
R7
OUT1
regulator 1
output
12
14
19
6
7
low battery
detection
R3
FB1
TEA1202TS
R4
external
clock
SYNC/PWM
SHDWN0
18
DC/DC
shut-down
OUT2
regulator 2
output
2
10
SHDWN2
Vref
regulator 2
shut-down
R5
3
FB2
15
9
8
17
GND0
C5
R6
GND
MGU063
Fig.5 Application in single-cell NiCd or NiMH battery powered equipment.
15
2002 Mar 14
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
DC/DC
output
DC/DC
UPCONVERTER
regulator 1
output
LDO1
LDO2
TEA1202TS
regulator 2
output
low battery
detection
LOW BATTERY
DETECTOR
equivalent block diagram
D1
L1
R10
ILIM
LX1
LX2
1
5
4
UPOUT/DNIN
DC/DC
output
20
11
13
IN2
C1
R1
LBI1
FB0
C2
C3
C4
16
C6
R8
R2
LBI2
U/D
12
19
R7
R9
OUT1
regulator 1
output
6
R3
TEA1202TS
LBO
low battery
detection
FB1
14
7
R4
external
clock
SYNC/PWM
SHDWN0
18
2
DC/DC
shut-down
OUT2
regulator 2
output
10
9
SHDWN2
Vref
regulator 2
shut-down
R5
3
FB2
15
8
17
GND0
C5
R6
GND
MGU064
Fig.6 Application in two-cell NiCd or NiMH battery powered equipment.
16
2002 Mar 14
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
control
regulator 1 switch
DC/DC
output
DC/DC
UPCONVERTER
output
regulator 1
switch
SWITCH
LDO1
TEA1202TS
regulator 2
output
LDO2
LOW BATTERY
DETECTOR
low battery
detection
equivalent block diagram
D1
L1
R10
ILIM
LX1
LX2
1
5
4
UPOUT/DNIN
DC/DC
output
20
11
13
IN2
C1
R1
LBI1
FB0
C2
16
C6
R8
R9
R2
LBI2
U/D
12
R7
TEA1202TS
19
output
OUT1
FB1
regulator 1
switch
6
7
LBO
low battery
detection
14
control
regulator 1
switch
external
clock
SYNC/PWM
SHDWN0
18
2
OUT2
regulator 2
output
10
9
SHDWN2
Vref
R5
3
FB2
15
C4
8
17
GND0
C5
R6
GND
MGU065
Fig.7 Application in two-cell NiCd or NiMH battery powered equipment with autonomous shut-down at low
battery voltage and using LDO1 as a switch.
2002 Mar 14
17
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
DC/DC
output
DC/DC
DOWNCONVERTER
regulator 1
output
LDO1
LDO2
TEA1202TS
regulator 2
output
LOW BATTERY
DETECTOR
low battery
detection
equivalent block diagram
R10
ILIM
LX2
LX1
5
UPOUT/DNIN
4
20
1
L1
D1
DC/DC
output
IN2
11
13
C1
LBI1
R1
R2
C6
FB0
C2
C3
C4
16
R8
LBI2
U/D
12
19
R7
R9
OUT1
FB1
regulator 1
output
6
TEA1202TS
R3
R4
LBO
low battery
detection
7
14
SYNC/PWM
SHDWN0
external
clock
18
2
DC/DC
shut-down
OUT2
FB2
regulator 2
output
10
9
SHDWN2
Vref
regulator 2
shut-down
R5
R6
3
15
8
17
GND0
C5
GND
MGU066
Fig.8 Application in three-cell NiCd or NiMH and single-cell Li-Ion battery powered equipment.
18
2002 Mar 14
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
USB supply
5 V
BAW62
0.95 to 1.5 V
DC/DC CONVERTER
1
4
20
130
kΩ
120
µF
16
120
µF
V
bat
68
kΩ
LDO1
6
7
3.3 V
load
120
kΩ
2.2
TEA1202TS
µF
68
kΩ
MGU589
Fig.9 Application with USB and single-cell NiCd or NiMH battery supply.
13.1 External component selection
13.1.4 DIODE D1
Component references apply to the circuits shown in
Figs 5 to 8.
The Schottky diode is only used for a short time during
takeover from N-type power MOSFET and P-type power
MOSFET and vice versa. Therefore, a medium-power
diode is sufficient in most applications, for example
Philips PRLL5819.
13.1.1 INDUCTOR L1
The performance of the TEA1202TS is not very sensitive
to inductance value. The best efficiency performance over
a wide load current range is achieved by using an
inductance of 6.8 µH, for example TDK SLF7032 or
Coilcraft DO1608 range.
13.1.5 FEEDBACK RESISTORS R1 AND R2
The output voltage of the DC-to-DC converter is
determined by the resistors R1 and R2. The following
conditions apply:
13.1.2 DC-TO-DC INPUT CAPACITOR C1
• Only use 1% tolerance SMD-type resistors. If larger
body-size resistors are used, the capacitance on
pin FB0 will be too large and could cause inaccurate
operation
The value of C1 depends strongly on the type of input
source. In general, a 100 µF tantalum capacitor is
sufficient.
• Resistors R1 and R2 should have a maximum value of
50 kΩ when connected in parallel. A higher value will
result in inaccurate operation.
13.1.3 DC-TO-DC OUTPUT CAPACITOR C2
The value and type of C2 depends on the maximum output
current and the ripple voltage which is allowed in the
application. Low-ESR tantalum capacitors show good
results. The most important specification of C2 is its ESR,
which mainly determines output voltage ripple.
Under these conditions the output voltage can be
calculated by the formula:
R1
R2
VO = Vref × 1 +
-------
2002 Mar 14
19
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
13.1.6 CURRENT LIMITING RESISTOR R10
13.1.10 LOW BATTERY DETECTOR
COMPONENTS R7, R8, R9 AND C6
The maximum instantaneous current is set by the external
resistor R10. The preferred type is SMD, 1% accuracy.
Resistor R7 is connected between pin LBO and the input
or output pin and must be 330 kΩ or higher.
The connection of resistor R10 differs for each mode:
A single-cell NiCd or NiMH battery can be connected
directly to pin LBI1.
• At upconversion: resistor R10 must be connected
between pins ILIM and UPOUT/DNIN; the current
320
R10
A higher battery voltage must be applied to pin LBI2 using
a divider circuit with resistor R8 and R9. In that situation,
capacitor C6 (10 nF) must be connected between pin LBI1
and ground. The low-battery detection level for a higher
battery voltage can be set by the resistors at pin LBI2
using the formula:
limiting level is defined by: IIim
=
----------
• At downconversion: resistor R10 must be connected
between pins ILIM and GND0; the current limiting level
300
is defined by: I Iim
=
----------
R10
R8
R9
The average inductor current during limited current
operation also depends on the inductance value, input
voltage, output voltage and resistive losses in all
components in the power path. Ensure that
V LBI2 = 0.90 × 1 +
-------
13.2 Application recommendations
I
lim < Isat (saturation current) of the inductor.
1. Connect loads above approximately 30 mA via LDO1
to avoid start-up problems.
13.1.7 REFERENCE VOLTAGE DECOUPLING CAPACITOR C5
2. Apply minimum input voltage to minimize the power
dissipation of the LDOs.
Optionally, a decoupling capacitor can be connected
between pin Vref and ground in order to achieve a lower
noise level of the output voltages of the LDO. The best
choice for C5 is a ceramic multilayer capacitor of
approximately 10 nF.
3. For optimum LDO performance, the required drop
voltage is 250 mV at ILDO = 50 mA and 500 mV at
ILDO = 150 mA; the minimum required voltage drop is
calculated by Iload × 900 mΩ.
4. Minimum LDO input capacitance is 2.2 µF.
13.1.8 LDO OUTPUT CAPACITORS C3 AND C4
5. Minimum LDO output capacitance is 2.2 µF for load
currents between 0 and 150 mA and 4.7 µF for load
currents between 0 and 250 mA.
A typical LDO output capacitor is a ceramic multilayer
capacitor of 2.2 µF, for example GRM40X5R225K6.3 from
Murata. The ESR of the output capacitor must be at least
10 mΩ to achieve stability and the specified transient
response.
6. X7R or X5R-type ceramic capacitors with a minimum
ESR of 10 mΩ must be used on the LDO outputs.
7. With the USB and battery powered concept shown in
Fig.9, LDO1 is used as a regulator and not as a switch.
For a good load regulation, the DC-to-DC converter is
set at 3.5 V and the LDO at 3.3 V. This reduces the
efficiency by approximately 5%. However, the
efficiency can be improved by lowering the voltage
drop, but this will reduce the output voltage
performance.
13.1.9 LDO FEEDBACK RESISTORS R3, R4, R5 AND R6
The output voltage of each LDO can be set by the external
feedback resistors. Their values can be derived from the
formulae:
R3
V O = V ref × 1 +
V O = V ref × 1 +
-------
R4
8. In two or more cell applications, pin LBI1 is not used
and should be decoupled with a 10 nF capacitor.
R5
-------
R6
9. In a single-cell application pin LBI2 is not used and
should be connected to ground.
The maximum value for each of the LDO feedback
10. The maximum continuous current at pins LX1 and LX2
is 1 A. During experiments, especially at low input
voltages, the current can rise excessively. Avoid this
situation by using a power supply with a 1 A current
limit.
resistors is 500 kΩ.
2002 Mar 14
20
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
13.3 Typical performance characteristics
MGU577
100
η
(%)
(1)
(2)
80
60
40
2
3
1
10
10
10
I
(mA)
L
(1) VI = 2.4 V.
(2) VI = 1.2 V.
VO = 3.5 V
Fig.10 Efficiency as a function of load current.
2002 Mar 14
21
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
MGU579
2.50
V
I(start)
(V)
2.00
(1)
1.50
(2)
1.00
(3)
0.50
0.00
0
50
100
150
200
I
(mA)
L
(1) Two-cell start-up.
(2) Single-cell start-up.
VI = 2.4 V; VO = 3.5 V.
(3) Minimum supply voltage after start-up.
Fig.11 Start-up voltage and minimum supply voltage as a function of load current.
MGU578
600
R
DS(on)
mΩ
500
LDO1
LDO2
400
300
200
100
0
0.00
1.00
2.00
3.00
4.00
5.00
6.00
V (V)
I
Fig.12 LDO1 and LDO2 drain-to-source on-state resistance as a function of input voltage.
22
2002 Mar 14
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
14 PACKAGE OUTLINE
SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm
SOT266-1
D
E
A
X
c
y
H
v
M
A
E
Z
11
20
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
10o
0o
0.15
0
1.4
1.2
0.32
0.20
0.20
0.13
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.45
0.65
0.45
0.48
0.18
mm
1.5
0.65
1.0
0.2
0.25
0.13
0.1
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-22
99-12-27
SOT266-1
MO-152
2002 Mar 14
23
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
15 SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
15.1 Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
15.2 Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
15.4 Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
15.3 Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2002 Mar 14
24
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
15.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
not suitable
REFLOW(1)
BGA, HBGA, LFBGA, SQFP, TFBGA
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS
PLCC(3), SO, SOJ
suitable
suitable
suitable
not suitable(2)
suitable
LQFP, QFP, TQFP
not recommended(3)(4) suitable
not recommended(5)
suitable
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Mar 14
25
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
16 DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS(1)
STATUS(2)
DEFINITIONS
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
17 DEFINITIONS
18 DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2002 Mar 14
26
Philips Semiconductors
Preliminary specification
0.95 V starting power unit
TEA1202TS
NOTES
2002 Mar 14
27
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403502/02/pp28
Date of release: 2002 Mar 14
Document order number: 9397 750 09361
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