SC16C751B_技术文档

SC16C751B

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

Rev. 02 — 10 October 2008

Product data sheet

1. General description

The SC16C751B is a Universal Asynchronous Receiver and Transmitter (UART) used for

serial data communications. Its principal function is to convert parallel data into serial

data, and vice versa. The UART can handle serial data rates up to 5 Mbit/s.

The SC16C751B is functionally equivalent to the SC16C750B, and requires a special

software initialization sequence to conﬁgure the device to operate (see Section 6.6).

Programming of control registers enables the added features of the SC16C751B. Some of

these added features are the 64-byte receive and transmit FIFOs, automatic hardware

ﬂow control. The selectable auto-ﬂow control feature signiﬁcantly reduces software

overload and increases system efﬁciency while in FIFO mode by automatically controlling

serial data ﬂow using RTS output and CTS input signals. On-board status registers

provide the user with error indications, operational status, and modem interface control.

System interrupts may be tailored to meet user requirements. An internal loopback

capability allows on-board diagnostics.

The SC16C751B operates at 5 V, 3.3 V and 2.5 V, the industrial temperature range and is

available in the plastic HVQFN24 package.

2. Features

I Single channel

I 5 V, 3.3 V and 2.5 V operation

I 5 V tolerant on input only pins¹

I Industrial temperature range (−40 °C to +85 °C)

I After reset, all registers are identical to the typical 16C450 register set

I Capable of running with all existing generic 16C450 software

I Up to 5 Mbit/s transmit/receive operation at 5 V, 3.3 V; 3 Mbit/s at 2.5 V

I 64-byte transmit FIFO

I 64-byte receive FIFO with error ﬂags

I Programmable auto-RTS and auto-CTS

N In auto-CTS mode, CTS controls transmitter

N In auto-RTS mode, receive FIFO contents and threshold control RTS

I Automatic hardware ﬂow control

I Software selectable baud rate generator

I Four selectable receive interrupt trigger levels

I Standard modem interface

I Sleep mode

1. For data bus pins D7 to D0, see Table 22 “Limiting values”.

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

I Standard asynchronous error and framing bits (start, stop, and parity overrun break)

I Independent receiver clock input

I Transmit, receive, line status, and data set interrupts independently controlled

I Fully programmable character formatting:

N 5-bit, 6-bit, 7-bit, or 8-bit characters

N Even, odd, or no-parity formats

N 1, 1¹⁄₂, or 2-stop bit

N Baud generation (DC to 5 Mbit/s)

I False start-bit detection

I Complete status reporting capabilities

I 3-state output TTL drive capabilities for bidirectional data bus and control bus

I Line break generation and detection

I Internal diagnostic capabilities:

N Loopback controls for communications link fault isolation

I Prioritized interrupt system controls

I Modem control functions (CTS, RTS)

3. Ordering information

Table 1.

Ordering information

Industrial: V_DD= 2.5 V, 3.3 V or 5 V ± 10 %; T_amb= −40 °C to +85 °C.

Type number

Package

Name

Description

Version

SC16C751BIBS

HVQFN24 plastic thermal enhanced very thin quad ﬂat package; no leads;

SOT616-3

24 terminals; body 4 × 4 × 0.85 mm

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

2 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

4. Block diagram

SC16C751B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TX

REGISTERS

REGISTER

DATA BUS

D0 to D7

IOR, IOW

RESET

AND

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

RECEIVE

FIFO

RECEIVE

SHIFT

RX

REGISTERS

REGISTER

FLOW

CONTROL

LOGIC

REGISTER

SELECT

LOGIC

A0 to A2

CS

RTS

CTS

MODEM

CONTROL

LOGIC

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

INT

002aad010

XTAL1

XTAL2

Fig 1. Block diagram of SC16C751B

5. Pinning information

5.1 Pinning

terminal 1

index area

1

2

3

4

5

6

18

17

16

15

14

13

D5

CTS

RESET

RTS

INT

D6

D7

RX

TX

CS

SC16C751BIBS

A0

A1

002aad011

Transparent top view

Fig 2. Pin conﬁguration for HVQFN24

Rev. 02 — 10 October 2008

SC16C751B_2

Product data sheet

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SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

5.2 Pin description

Table 2.

Symbol

A0

Pin description

14

13

12

6

Type

Description

I

Register select. A0 to A2 are used during read and write

operations to select the UART register to read from or write to.

Refer to Table 3 for register addresses.

A1

A2

CS

Chip select. When CS is LOW, the UART is selected.

CTS

18

Clear to send. CTS is a modem status signal. Its condition can be

checked by reading bit 4 (CTS) of the Modem Status Register

(MSR). MSR[3] (∆CTS) indicates that CTS has changed states

since the last read from the MSR. If the modem status interrupt is

enabled when CTS changes levels and the auto-CTS mode is not

enabled, an interrupt is generated. CTS is also used in the

auto-CTS mode to control the transmitter.

D0

D1

D2

D3

D4

D5

D6

D7

INT

20

21

22

23

24

1

I/O

O

Data bus. Eight data lines with 3-state outputs provide a

bidirectional path for data, control and status information between

the UART and the CPU.

2

3

15

Interrupt. When active (HIGH), INT informs the CPU that the UART

has an interrupt to be serviced. Four conditions that cause an

interrupt to be issued are: a receiver error, received data that is

available or timed out (FIFO mode only), an empty transmitter

holding register or an enabled modem status interrupt. INT is reset

(deactivated) either when the interrupt is serviced or as a result of a

Master Reset.

RESET

IOR

17

11

I

Master Reset. When active (HIGH), RESET clears most UART

registers and sets the levels of various output signals.

Read input. When IOR is active (LOW) while the UART is selected,

the CPU is allowed to read status information or data from a

selected UART register.

RTS

16

O

Request to send. When active, RTS informs the modem or data

set that the UART is ready to receive data. RTS is set to the active

level by setting the RTS Modem Control Register bit and is set to

the inactive (HIGH) level either as a result of a Master Reset or

during Loopback mode operations or by clearing bit 1 (RTS) of the

MCR. In the auto-RTS mode, RTS is set to the inactive level by the

receiver threshold control logic.

RX

TX

4

5

I

Serial data input. RX is serial data input from a connected

communications device.

O

Serial data output. TX is composite serial data output to a

connected communication device. TX is set to the marking (HIGH)

level as a result of Master Reset.

V_DD

19

10

power 2.5 V, 3 V or 5 V supply voltage.

power Ground voltage.

[1]

V_SS

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

4 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

Table 2.

Pin description …continued

Symbol

Type

Description

IOW

9

I

Write input. When IOW is active (LOW) and while the UART is

selected, the CPU is allowed to write control words or data into a

selected UART register.

XTAL1

XTAL2^[2]

7

8

I

Crystal connection or External clock input.

O

Crystal connection or the inversion of XTAL1 if XTAL1 is

driven.

[1] HVQFN24 package die supply ground is connected to both V_SSpin and exposed center pad. V_SSpin must

be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board

level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad

on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the

PCB in the thermal pad region.

[2] In Sleep mode, XTAL2 is left ﬂoating.

6. Functional description

The SC16C751B provides serial asynchronous receive data synchronization,

parallel-to-serial and serial-to-parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for converting the serial data stream into

parallel data that is required with digital data systems. Synchronization for the serial data

stream is accomplished by adding start and stop bits to the transmit data to form a data

character (character orientated protocol). Data integrity is insured by attaching a parity bit

to the data character. The parity bit is checked by the receiver for any transmission bit

errors. The SC16C751B is fabricated with an advanced CMOS process to achieve low

drain power and high speed requirements.

The SC16C751B is an upward solution that provides 64 bytes of transmit and receive

FIFO memory, instead of none in the 16C450, or 16 bytes in the 16C550. The

SC16C751B is designed to work with high speed modems and shared network

environments that require fast data processing time. Increased performance is realized in

the SC16C751B by the larger transmit and receive FIFOs. This allows the external

processor to handle more networking tasks within a given time. In addition, the four

selectable levels of FIFO trigger interrupt and automatic hardware ﬂow control is uniquely

provided for maximum data throughput performance, especially when operating in a

multi-channel environment. The combination of the above greatly reduces the bandwidth

requirement of the external controlling CPU, increases performance, and reduces power

consumption.

The SC16C751B is capable of operation up to 5 Mbit/s with an 80 MHz external clock

input (at 5 V).

The rich feature set of the SC16C751B is available through internal registers. Automatic

hardware ﬂow control, selectable transmit and receive FIFO trigger level, selectable TX

and RX baud rates, modem interface controls, and a Sleep mode are some of these

features.

6.1 Internal registers

The SC16C751B provides 12 internal registers for monitoring and control. These registers

are shown in Table 3. These twelve registers are similar to those already available in the

standard 16C550. These registers function as data holding registers (THR/RHR), interrupt

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

5 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

status and control registers (IER/ISR), a FIFO Control Register (FCR), line status and

control registers (LCR/LSR), modem status and control registers (MCR/MSR),

programmable data rate (clock) control registers (DLL/DLM), and a user accessible

Scratchpad Register (SPR). Register functions are more fully described in the following

paragraphs.

Table 3.

A2

Internal registers decoding

A0 READ mode

A1

WRITE mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR/LSR, SPR)^[1]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive Holding Register

Interrupt Enable Register

Interrupt Status Register

Line Control Register

Modem Control Register

Line Status Register

Transmit Holding Register

Interrupt Enable Register

FIFO Control Register

Line Control Register

Modem Control Register

n/a

Modem Status Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM)^[2]

0

1

LSB of Divisor Latch

MSB of Divisor Latch

LSB of Divisor Latch

MSB of Divisor Latch

[1] These registers are accessible only when LCR[7] is a logic 0.

[2] These registers are accessible only when LCR[7] is a logic 1.

6.2 FIFO operation

The 64-byte transmit and receive data FIFOs are enabled by the FIFO Control Register

bit 0 (FCR[0]). The receiver FIFO section includes a time-out function to ensure data is

delivered to the external CPU. An interrupt is generated whenever the Receive Holding

Register (RHR) has not been read following the loading of a character or the receive

trigger level has not been reached.

Table 4.

Flow control mechanism

Selected trigger level

(characters)

INT pin activation

Negate RTS

Assert RTS

16-byte FIFO

1

0

4

8

14

64-byte FIFO

1

0

16

32

56

16

32

56

16

32

56

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

6 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

6.3 Hardware ﬂow control

When automatic hardware ﬂow control is enabled, the SC16C751B monitors the CTS pin

for a remote buffer overﬂow indication and controls the RTS pin for local buffer overﬂows.

Automatic hardware ﬂow control is selected by setting MCR[5] (RTS) and MCR[1] (CTS)

to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a ﬂow control request,

the SC16C751B will suspend TX transmissions as soon as the stop bit of the character in

process is shifted out. Transmission is resumed after the CTS input returns to a logic 0,

indicating more data may be sent.

With the auto-RTS function enabled, an interrupt is generated when the receive FIFO

reaches the programmed trigger level. The RTS pin will not be forced to a logic 1 (RTS

off), until the receive FIFO reaches the next trigger level. However, the RTS pin will return

to a logic 0 after the data buffer (FIFO) is emptied. However, under the above described

conditions, the SC16C751B will continue to accept data until the receive FIFO is full.

6.4 Time-out interrupts

When two interrupt conditions have the same priority, it is important to service these

interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt

priority (when enabled by IER[0]). The receiver issues an interrupt after the number of

characters have reached the programmed trigger level. In this case, the SC16C751B

FIFO may hold more characters than the programmed trigger level. Following the removal

of a data byte, the user should re-check LSR[0] for additional characters. A Receive Time

Out will not occur if the receive FIFO is empty. The time-out counter is reset at the center

of each stop bit received or each time the receive holding register (RHR) is read. The

actual time-out value is 4 character time.

6.5 Programmable baud rate generator

The SC16C751B supports high speed modem technologies that have increased input

data rates by employing data compression schemes. For example, a 33.6 kbit/s modem

that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s

ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.

A single baud rate generator is provided for the transmitter and receiver, allowing

independent TX/RX channel control. The programmable baud rate generator is capable of

accepting an input clock up to 80 MHz, as required for supporting a 5 Mbit/s data rate.

The SC16C751B can be conﬁgured for internal or external clock operation. For internal

clock oscillator operation, an industry standard microprocessor crystal (parallel resonant,

22 pF to 33 pF load) is connected externally between the XTAL1 and XTAL2 pins (see

Figure 3). Alternatively, an external clock can be connected to the XTAL1 pin to clock the

internal baud rate generator for standard or custom rates (see Table 5).

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

7 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

XTAL1

XTAL2

XTAL1

XTAL2

1.5 kΩ

X1

1.8432 MHz

C1

22 pF

C2

33 pF

C1

22 pF

C2

47 pF

002aaa870

Fig 3. Crystal oscillator connection

The generator divides the input 16× clock by any divisor from 1 to (2¹⁶− 1). Customized

baud rates can be achieved by selecting the proper divisor values for the MSB and LSB

sections of baud rate generator.

Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a

user capability for selecting the desired ﬁnal baud rate. The example in Table 5 shows

selectable baud rates when using a 1.8432 MHz crystal.

For custom baud rates, the divisor value can be calculated using Equation 1:

XTAL1 clock frequency

serial data rate × 16

divisor (in decimal) =

(1)

----------------------------------------------------------------

Table 5.

Baud rates using 1.8432 MHz or 3.072 MHz crystal

Using 3.072 MHz crystal

Using 1.8432 MHz crystal

Desired

baud rate

Divisor for

16× clock

Baud rate

error

Desired

baud rate

Divisor for

16× clock

Baud rate

error

50

2304

1536

1047

857

768

384

192

96

50

3840

2560

1745

1428

1280

640

320

160

107

96

75

110

0.026

0.058

110

0.026

0.034

134.5

150

134.5

150

300

600

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

56000

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

64

0.312

58

0.69

48

80

32

53

0.628

1.23

24

40

16

27

12

20

6

10

3

5

2

2.86

SC16C751B_2

Product data sheet

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SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

6.6 Special software initialization sequence

Upon reset, the SC16C751B will not be able to receive. A special software initialization

sequence must be sent to the device to enable its receiver clock.

The following software sequence can be added to the UART initialization routine, and this

must be done before other registers are initialized.

WRITE LCR 00

WRITE MSR AA

WRITE MSR 55

WRITE MSR CC

WRITE MSR 33

WRITE MSR A5

WRITE MSR C3

WRITE MSR 5C

WRITE MSR 3A

WRITE LSR 20

6.7 Sleep mode

The SC16C751B is designed to operate with low power consumption. A special Sleep

mode is included to further reduce power consumption (the internal oscillator driver is

disabled) when the chip is not being used. With IER[4] enabled (set to a logic 1), the

SC16C751B enters the Sleep mode, but resumes normal operation when a start bit is

detected, a change of state of RX, CTS, or a transmit data is provided by the user. If the

Sleep mode is enabled and the SC16C751B is awakened by one of the conditions

described above, it will return to the Sleep mode automatically after the last character is

transmitted or read by the user. In any case, the Sleep mode will not be entered while an

interrupt(s) is pending. The SC16C751B will stay in the Sleep mode of operation until it is

disabled by setting IER[4] to a logic 0.

6.8 Low power mode

In Low power mode the oscillator is still running and only the clock to the UART core is

cut off. This helps to reduce the operating current to about ¹⁄₃. The UART wakes up under

the same conditions as in Sleep mode.

6.9 Loopback mode

The internal loopback capability allows on-board diagnostics. In the Loopback mode, the

normal modem interface pins are disconnected and reconﬁgured for loopback internally.

MCR[3:0] register bits are used for controlling loopback diagnostic testing. The transmitter

output (TX) and the receiver input (RX) are disconnected from their associated interface

pins, and instead are connected together internally (see Figure 4). The CTS is

disconnected from its normal modem control input pins, and instead is connected

internally to RTS. Loopback test data is entered into the Transmit Holding Register via the

user data bus interface, D0 to D7. The transmit UART serializes the data and passes the

serial data to the receive UART via the internal loopback connection. The receive UART

converts the serial data back into parallel data that is then made available at the user data

interface D0 to D7. The user optionally compares the received data to the initial

transmitted data for verifying error-free operation of the UART TX/RX circuits.

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

9 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

SC16C751B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TX

REGISTERS

REGISTER

MCR[4] = 1

RECEIVE

DATA BUS

D0 to D7

IOR, IOW

RESET

AND

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

RECEIVE

FIFO

SHIFT

RX

REGISTERS

REGISTER

FLOW

CONTROL

LOGIC

REGISTER

SELECT

LOGIC

A0 to A2

CS

RTS

MODEM

CONTROL

LOGIC

CTS

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

INT

002aad012

XTAL1

XTAL2

Fig 4. Internal Loopback mode diagram

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

10 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7. Register descriptions

Table 6 details the assigned bit functions for the ﬁfteen SC16C751B internal registers. The

assigned bit functions are more fully deﬁned in Section 7.1 through Section 7.10.

Table 6.

SC16C751B internal registers

A2 A1 A0 Register Default^[1]Bit 7

General register set^[2]

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

RHR

THR

IER

XX

00

bit 7

0

bit 6

0

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Low

power

mode

Sleep

mode

modem receive

status line

interrupt status

interrupt

transmit receive

holding holding

register register

0

1

0

1

0

1

FCR

ISR

00

01

00

60

RCVR

trigger

(MSB)

RCVR

trigger

(LSB)

64-byte reserved reserved XMIT

RCVR

FIFO

reset

FIFO

enable

[3]

FIFO

enable

FIFO

reset

FIFOs

64-byte

0

INT

priority

bit 0

INT

status

enabled enabled FIFO

enable

priority

bit 2

priority

bit 1

LCR

MCR

LSR

divisor

latch

enable

set break set

parity

even

parity

enable

stop bits word

length

word

length

bit 0

bit 1

0

ﬂow

control

enable

loopback reserved reserved RTS

reserved

[3]

FIFO

data

error

trans.

empty

trans.

break

framing parity

overrun receive

error

holding interrupt error

empty

error

data

ready

1

0

1

MSR

SPR

X0

FF

reserved reserved reserved CTS

reserved reserved reserved ∆CTS

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Special register set^[4]

0

1

DLL

XX

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 9

bit 0

bit 8

DLM

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

[1] The value shown represents the register’s initialized hex value; X = n/a.

[2] These registers are accessible only when LCR[7] = 0.

[3] Do not write a logic 1 to the reserved bits. Read of the reserved bits reﬂect unknown values.

[4] The ‘Special register set’ is accessible only when LCR[7] is set to a logic 1.

SC16C751B_2

Product data sheet

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11 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.1 Transmit and Receive Holding Registers (THR and RHR)

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the

THR, providing that the THR or TSR is empty. The THR empty ﬂag in the LSR register will

be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.

Note that a write operation can be performed when the THR empty ﬂag is set

(logic 0 = FIFO full; logic 1 = at least one FIFO location available).

The serial receive section also contains an 8-bit Receive Holding Register (RHR).

Receive data is removed from the SC16C751B and receive FIFO by reading the RHR

register. The receive section provides a mechanism to prevent false starts. On the falling

edge of a start or false start bit, an internal receiver counter starts counting clocks at the

16× clock rate. After 7¹⁄₂clocks, the start bit time should be shifted to the center of the

start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.

Evaluating the start bit in this manner prevents the receiver from assembling a false

character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the INT output pin.

Table 7.

Interrupt Enable Register bits description

Bit Symbol Description

7:6 IER[7:6] Not used.

5

4

3

2

IER[5]

IER[4]

IER[3]

IER[2]

Low power mode.

logic 0 = disable Low power mode (normal default condition)

logic 1 = enable Low power mode

Sleep mode.

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode. See Section 6.7 “Sleep mode” for details.

Modem Status Interrupt.

logic 0 = disable the modem status register interrupt (normal default condition)

logic 1 = enable the modem status register interrupt

Receive Line Status interrupt. This interrupt will be issued whenever a fully

assembled receive character is transferred from RSR to the RHR/FIFO, i.e., data

ready, LSR[0].

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

1

IER[1]

Transmit Holding Register interrupt. This interrupt will be issued whenever the

THR is empty, and is associated with LSR[1].

logic 0 = disable the transmitter empty interrupt (normal default condition)

logic 1 = enable the transmitter empty interrupt

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

12 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

Table 7.

Bit Symbol Description

IER[0]

Interrupt Enable Register bits description …continued

0

Receive Holding Register interrupt. This interrupt will be issued when the FIFO

has reached the programmed trigger level, or is cleared when the FIFO drops

below the trigger level in the FIFO mode of operation.

logic 0 = disable the receiver ready interrupt (normal default condition)

logic 1 = enable the receiver ready interrupt

7.2.1 IER versus Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are

enabled, the receive interrupts and register status will reﬂect the following:

• The receive data available interrupts are issued to the external CPU when the FIFO

has reached the programmed trigger level. It will be cleared when the FIFO drops

below the programmed trigger level.

• FIFO status will also be reﬂected in the user accessible ISR register when the FIFO

trigger level is reached. Both the ISR register status bit and the interrupt will be

cleared when the FIFO drops below the trigger level.

• The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift

register to the receive FIFO. It is reset when the FIFO is empty.

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C751B in the FIFO polled

mode of operation. Since the receiver and transmitter have separate bits in the LSR,

either or both can be used in the polled mode by selecting respective transmit or receive

control bit(s).

• LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

• LSR[4:1] will provide the type of errors encountered, if any.

• LSR[5] will indicate when the transmit FIFO is empty.

• LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

• LSR[7] will indicate any FIFO data errors.

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

13 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs and set the receive FIFO trigger

levels.

7.3.1 FIFO mode

Table 8.

FIFO Control Register bits description

Bit Symbol

Description

7:6 FCR[7]

(MSB),

RCVR trigger. These bits are used to set the trigger level for the receive

FIFO interrupt.

FCR[6] (LSB)

An interrupt is generated when the number of characters in the FIFO equals

the programmed trigger level. However, the FIFO will continue to be loaded

until it is full. Refer to Table 9.

5

FCR[5]

64-byte FIFO enable.

logic 0 = 16-byte mode (normal default condition)

logic 1 = 64-byte mode

4:3 FCR[4:3]

reserved

2

1

0

FCR[2]

FCR[1]

FCR[0]

XMIT FIFO reset.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO

counter logic (the transmit shift register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

RCVR FIFO reset.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO

counter logic (the receive shift register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

FIFO enable.

logic 0 = disable the transmit and receive FIFO (normal default condition)

logic 1 = enable the transmit and receive FIFO

Table 9.

FCR[7]

RCVR trigger levels

FCR[6]

RX FIFO trigger level (bytes)

16-byte operation

64-byte operation

0

1

0

1

0

1

4

16

32

56

8

14

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

14 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.4 Interrupt Status Register (ISR)

The SC16C751B provides four levels of prioritized interrupts to minimize external software

interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status

bits. Performing a read cycle on the ISR will provide the user with the highest pending

interrupt level to be serviced. No other interrupts are acknowledged until the pending

interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is

cleared. However, it should be noted that only the current pending interrupt is cleared by

the read. A lower level interrupt may be seen after re-reading the interrupt status bits.

Table 10 “Interrupt source” shows the data values (bit 0 to bit 4) for the four prioritized

interrupt levels and the interrupt sources associated with each of these interrupt levels.

Table 10. Interrupt source

Priority

level

ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt

1

2

3

4

0

1

0

1

0

1

0

1

0

LSR (Receiver Line Status Register)

RXRDY (Received Data Ready)

RXRDY (Receive Data time-out)

TXRDY (Transmitter Holding Register Empty)

MSR (Modem Status Register)

Table 11. Interrupt Status Register bits description

Bit

Symbol

Description

7:6

ISR[7:6]

FIFOs enabled. These bits are set to a logic 0 when the FIFO is not

being used. They are set to a logic 1 when the FIFOs are enabled.

logic 0 or cleared = default condition

64-byte FIFO enable.

5

ISR[5]

logic 0 = 16-byte operation

logic 1 = 64-byte operation

not used

4

ISR[4]

3:1

ISR[3:1]

INT priority bit 2 to bit 0. These bits indicate the source for a pending

interrupt at interrupt priority levels 1, 2, and 3 (see Table 10).

logic 0 or cleared = default condition

INT status.

0

ISR[0]

logic 0 = an interrupt is pending and the ISR contents may be used

as a pointer to the appropriate interrupt service routine

logic 1 = no interrupt pending (normal default condition)

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

15 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits, and the parity are selected by writing the

appropriate bits in this register.

Table 12. Line Control Register bits description

Bit

Symbol

Description

7

LCR[7]

Divisor latch enable. The internal baud rate counter latch and Enhanced

Feature mode enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch and enhanced feature register enabled

6

5

LCR[6]

LCR[5]

Set break. When enabled, the Break control bit causes a break condition to

be transmitted (the TX output is forced to a logic 0 state). This condition exists

until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the

remote receiver to a line break condition

Set parity. If the parity bit is enabled, LCR[5] selects the forced parity format.

Programs the parity conditions (see Table 13).

logic 0 = parity is not forced (normal default condition)

LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logic 1 for the

transmit and receive data

LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logic 0 for the

transmit and receive data

4

LCR[4]

Even parity. If the parity bit is enabled with LCR[3] set to a logic 1, LCR[4]

selects the even or odd parity format.

logic 0 = odd parity is generated by forcing an odd number of logic 1s in the

transmitted data. The receiver must be programmed to check the same

format (normal default condition).

logic 1 = even parity is generated by forcing an even number of logic 1s in

the transmitted data. The receiver must be programmed to check the same

format.

3

LCR[3]

Parity enable. Parity or no parity can be selected via this bit.

logic 0 = no parity (normal default condition)

logic 1 = a parity bit is generated during the transmission, receiver checks

the data and parity for transmission errors

2

LCR[2]

Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with the

programmed word length (see Table 14).

logic 0 or cleared = default condition

1:0

LCR[1:0]

Word length bit 1, bit 0. These two bits specify the word length to be

transmitted or received (see Table 15).

logic 0 or cleared = default condition

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

16 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

Table 13. LCR[5] parity selection

LCR[5]

LCR[4]

LCR[3]

Parity selection

X

0

1

X

0

1

0

1

0

1

no parity

odd parity

even parity

force parity ‘1’

forced parity ‘0’

Table 14. LCR[2] stop bit length

LCR[2]

Word length (bits)

Stop bit length (bit times)

0

1

5, 6, 7, 8

5

1

1¹⁄₂

6, 7, 8

2

Table 15. LCR[1:0] word length

LCR[1]

LCR[0]

Word length (bits)

0

1

0

1

0

1

5

6

7

8

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

17 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 16. Modem Control Register bits description

Bit

7

Symbol

MCR[7]

MCR[6]

MCR[5]

Description

reserved; set to 0

6

5

AFE. This bit is the auto ﬂow control enable. When this bit is set, the auto

ﬂow control is enabled.

4

MCR[4]

Loopback. Enable the local Loopback mode (diagnostics). In this mode the

transmitter output (TX) and the receiver input (RX), CTS are disconnected

from the SC16C751B I/O pins. Internally the modem data and control pins

are connected into a loopback data conﬁguration (see Figure 4). In this

mode, the receiver and transmitter interrupts remain fully operational. The

Modem Control Interrupts are also operational, but the interrupts’ sources

are switched to the lower four bits of the Modem Control. Interrupts continue

to be controlled by the IER register.

logic 0 = disable Loopback mode (normal default condition)

logic 1 = enable local Loopback mode (diagnostics)

3:2

1

MCR[3:2]

MCR[1]

reserved

RTS

logic 0 = force RTS output to a logic 1 (normal default condition)

logic 1 = force RTS output to a logic 0

reserved

0

MCR[0]

The ﬂow control can be conﬁgured by programming MCR[1] and MCR[5] as shown in

Table 17.

Table 17. Flow control conﬁguration

MCR[5] (AFE)

MCR[1] (RTS)

Flow conﬁguration

1

0

1

0

X

auto RTS and CTS enabled

auto CTS only enabled

auto RTS and CTS disabled

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

18 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C751B and the CPU.

Table 18. Line Status Register bits description

Bit

Symbol Description

7

LSR[7]

FIFO data error.

logic 0 = no error (normal default condition)

logic 1 = at least one parity error, framing error or break indication is in the

current FIFO data. This bit is cleared when LSR register is read.

6

5

LSR[6]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a

logic 1 whenever the transmit holding register and the transmit shift register are

both empty. It is reset to logic 0 whenever either the THR or TSR contains a data

character. In the FIFO mode, this bit is set to logic 1 whenever the transmit FIFO

and transmit shift register are both empty.

LSR[5]

THR empty. This bit is the Transmit Holding Register Empty indicator. This bit

indicates that the UART is ready to accept a new character for transmission. In

addition, this bit causes the UART to issue an interrupt to CPU when the THR

interrupt enable is set. The THR bit is set to a logic 1 when a character is

transferred from the transmit holding register into the transmitter shift register.

The bit is reset to a logic 0 concurrently with the loading of the transmitter

holding register by the CPU. In the FIFO mode, this bit is set when the transmit

FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.

4

3

2

1

LSR[4]

LSR[3]

LSR[2]

LSR[1]

Break interrupt.

logic 0 = no break condition (normal default condition)

logic 1 = the receiver received a break signal (RX was a logic 0 for one

character frame time). In the FIFO mode, only one break character is loaded

into the FIFO.

Framing error.

logic 0 = no framing error (normal default condition)

logic 1 = framing error. The receive character did not have a valid stop bit(s). In

the FIFO mode, this error is associated with the character at the top of the

FIFO.

Parity error.

logic 0 = no parity error (normal default condition)

logic 1 = parity error. The receive character does not have correct parity

information and is suspect. In the FIFO mode, this error is associated with the

character at the top of the FIFO.

Overrun error.

logic 0 = no overrun error (normal default condition)

logic 1 = overrun error. A data overrun error occurred in the receive shift

register. This happens when additional data arrives while the FIFO is full. In

this case, the previous data in the shift register is overwritten. Note that under

this condition, the data byte in the receive shift register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the error.

0

LSR[0]

Receive data ready.

logic 0 = no data in receive holding register or FIFO (normal default condition)

logic 1 = data has been received and is saved in the receive holding register or

FIFO

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

19 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the modem, or

other peripheral device to which the SC16C751B is connected. Four bits of this register

are used to indicate the changed information. These bits are set to a logic 1 whenever a

control input from the modem changes state. These bits are set to a logic 0 whenever the

CPU reads this register.

Table 19. Modem Status Register bits description

Bit

7:5

4

Symbol

MSR[7:5] reserved

MSR[4] Clear To Send. CTS. CTS functions as hardware ﬂow control signal input if it

Description

is enabled via MCR[5]. Flow control (when enabled) allows starting and

stopping the transmissions based on the external modem CTS signal. A

logic 1 at the CTS pin will stop SC16C751B transmissions as soon as current

character has ﬁnished transmission. Normally MSR[4] is the complement of

the CTS input. However, in the Loopback mode, this bit is equivalent to the

RTS bit in the MCR register.

3:1

0

MSR[3:1] reserved

MSR[0]

∆CTS ^[1]

logic 0 = no CTS change (normal default condition)

logic 1 = the CTS input to the SC16C751B has changed state since the last

time it was read. A modem Status Interrupt will be generated.

[1] Whenever any MSR[0] is set to logic 1, a Modem Status Interrupt will be generated if modem status

interrupt is enabled.

7.9 Scratchpad Register (SPR)

The SC16C751B provides a temporary data register to store 8 bits of user information.

7.10 SC16C751B external reset conditions

Table 20. Reset state for registers

Register

IER

Reset state

IER[7:0] = 0

ISR

ISR[7:1] = 0; ISR[0] = 1

LCR[7:0] = 0

LCR

MCR

LSR

MCR[7:0] = 0

LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0

MSR[7:4] = input signals; MSR[3:0] = 0

FCR[7:0] = 0

MSR

FCR

Table 21. Reset state for outputs

Output

TX

Reset state

HIGH

RTS

INT

HIGH

LOW

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

20 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

8. Limiting values

Table 22. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

Parameter

Conditions

Min

Max

7

Unit

V

supply voltage

-

V_n

voltage on any other pin

at D7 to D0 pins

at any input only pin

operating

V

_SS− 0.3

V_DD+ 0.3

5.3

V

T_amb

ambient temperature

−40

−65

-

+85

°C

mW

T_stg

storage temperature

+150

500

P_tot/pack

total power dissipation per package

9. Static characteristics

Table 23. Static characteristics

T_amb= −40 °C to +85 °C; tolerance of V_DD= ± 10 %, unless otherwise speciﬁed.

Symbol Parameter

Conditions

V_DD= 2.5 V

V_DD= 3.3 V

V_DD= 5.0 V Unit

Min

−0.3

1.8

Max

0.45

V_DD

0.65

-

Min

−0.3

2.4

Max

0.6

V_DD

0.8

-

Min

−0.5

3.0

Max

0.6

V_IL(clk)

V_IH(clk)

V_IL

clock LOW-level input voltage

V

clock HIGH-level input voltage

LOW-level input voltage

HIGH-level input voltage

LOW-level output voltage

V_DD

0.8

−0.3

1.6

−0.3

2.0

−0.5

2.2

V_IH

V_DD

[1]

V_OL

on all outputs

I_OL= 5 mA

(data bus)

-

0.4

-

0.4

-

0.4

-

V

I_OL= 4 mA

(other outputs)

I_OL= 2 mA

(data bus)

-

I_OL= 1.6 mA

(other outputs)

-

V_OH

HIGH-level output voltage

I_OH= −5 mA

(data bus)

1.85

2.0

I_OH= −1 mA

(other outputs)

-

I_OH= −800 µA

(data bus)

-

I_OH= −400 µA

-

(other outputs)

I_LIL

LOW-level input leakage current

clock leakage current

-

±10

±30

3.5

50

1.0

5

-

±10

±30

4.5

50

1.5

5

-

±10 µA

±30 µA

4.5 mA

I_L(clk)

I_DD(AV)

-

average supply current

-

[2]

I_DD(sleep)sleep mode supply current

-

50

µA

I_DD(lp)

C_i

low-power mode supply current

input capacitance

-

1.5 mA

5

-

pF

R_pu(int)

SC16C751B_2

internal pull-up resistance

500

-

500

-

500

kΩ

Product data sheet

Rev. 02 — 10 October 2008

21 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

[1] Except for XTAL2, V_OL= 1 V typically.

[2] Sleep current might be higher if there is activity on the UART data bus during Sleep mode.

10. Dynamic characteristics

Table 24. Dynamic characteristics

T_amb= −40 °C to +85 °C; tolerance of V_DD= ± 10 %, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

V_DD= 2.5 V

V_DD= 3.3 V

V_DD= 5.0 V

Unit

Min

Max

Min

Max

Min

Max

t_w2

pulse width LOW

10

-

6

-

6

-

ns

t_w1

pulse width HIGH

ns

[1]

f_XTAL1

t_6s’

frequency on pin XTAL1

address set-up time

IOR delay from chip select

IOR strobe width

48

-

80

-

80

-

MHz

ns

10

77

0

10

26

0

5

t_7d

-

10

23

0

-

ns

t_7w

25 pF load

-

ns

t_7h

chip select hold time from

IOR

-

ns

t_7h’

address hold time

5

20

-

5

20

-

5

20

-

ns

t_9d

read cycle delay

25 pF load

t_12d

t_12h

t_13d

t_13w

t_13h

delay from IOR to data

data disable time

77

15

-

26

15

-

23

15

-

IOW delay from chip select

IOW strobe width

10

20

0

10

20

0

10

15

0

-

chip select hold time from

IOW

-

t_14d

t_15d

t_16s

t_16h

t_17d

t_18d

IOW delay from address

write cycle delay

10

25

20

15

-

10

25

20

5

-

10

20

15

5

-

ns

-

data set-up time

-

data hold time

-

delay from IOW to output

25 pF load

100

-

33

24

-

29

23

delay to set interrupt from 25 pF load

modem input

-

t_19d

t_20d

t_21d

t_22d

t_23d

t_24d

delay to reset interrupt from 25 pF load;

-

100

1T_RCLK

100

-

24

1T_RCLK

29

-

23

1T_RCLK

28

ns

s

IOR

Figure 7

[2]

delay from stop to set

interrupt

delay time IOR to reset

interrupt

25 pF load;

Figure 9

ns

s

delay from start to set

interrupt

100

45

40

[2]

[3]

delay time from IOW to

transmit start

8T_RCLK24T_RCLK8T_RCLK24T_RCLK8T_RCLK24T_RCLK

delay from IOW to reset

interrupt

-

100

-

45

-

40

ns

t_RESET

N

RESET pulse width

baud rate divisor

100

1

-

40

1

-

40

1

-

2¹⁶− 1

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

22 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

[1] Applies to external clock, crystal oscillator max 24 MHz.

[2] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.

[3] Reset pulse must happen when these signals are inactive: CS, IOR, IOW.

10.1 Timing diagrams

valid

address

valid

address

A0 to A2

t

7h'

t

6s'

7h'

7w

CS

active

t

9d

7d

7w

active

IOR

t

12h

12d

D0 to D7

data

002aad015

Fig 5. General read timing

valid

address

valid

address

A0 to A2

t

6s'

7h'

6s'

7h'

active

CS

t

13w

13d

13w

15d

active

IOW

t

16h

t

16h

16s

data

D0 to D7

002aad014

Fig 6. General write timing

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

23 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

active

IOW

t

17d

change of state

RTS

change of state

CTS

INT

t

18d

active

t

19d

active

IOR

002aad013

Fig 7. Modem input/output timing

t

w1

w2

EXTERNAL

CLOCK

002aaa112

t

w3

1

f _XTAL1

=

-------

t_w3

Fig 8. External clock timing

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

24 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

start

bit

parity stop start

bit

data bits (0 to 7)

D3 D4

RX

D0

D1

D2

D5

D6

D7

5 data bits

6 data bits

7 data bits

t

20d

active

INT

t

21d

active

IOR

16 baud rate clock

002aaa113

Fig 9. Receive timing

start

bit

parity stop start

bit bit

bit

data bits (0 to 7)

TX

D0

D1

D2

D3

D4

D5

D6

D7

5 data bits

6 data bits

7 data bits

active

INT

transmitter ready

t

22d

t

24d

t

23d

active

IOW

active

16 baud rate clock

002aaa116

Fig 10. Transmit timing

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

25 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

11. Package outline

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 4 x 4 x 0.85 mm

SOT616-3

B

A

D

terminal 1

index area

A

1

E

c

detail X

e

1

C

1/2 e

y

C

1

e

v

M

C

A

B

b

7

12

w

L

13

6

e

E

h

2

1/2 e

1

18

terminal 1

index area

24

19

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

mm

A

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

4.1

3.9

2.75

2.45

4.1

3.9

2.75

2.45

0.5

0.3

0.05

0.1

1

0.2

0.5

2.5

0.1 0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

04-11-19

05-03-10

SOT616-3

- - -

MO-220

- - -

Fig 11. Package outline SOT616-3 (HVQFN24)

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

26 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

12. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

12.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

12.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

12.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

27 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

12.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 12) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 25 and 26

Table 25. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 26. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 12.

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

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SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 12. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

13. Abbreviations

Table 27. Abbreviations

Acronym

BRG

Description

Baud Rate Generator

CMOS

CPU

Complementary Metal-Oxide Semiconductor

Central Processing Unit

Divisor Latch LSB

DLL

DLM

Divisor Latch MSB

FIFO

LSB

First In, First Out

Least Signiﬁcant Bit

MSB

Most Signiﬁcant Bit

TTL

Transistor-Transistor Logic

Universal Asynchronous Receiver and Transmitter

UART

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

29 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

14. Revision history

Table 28. Revision history

Document ID

SC16C751B_2

Modiﬁcations:

Release date

Data sheet status

Change notice

Supersedes

20081010

Product data sheet

-

SC16C751B_1

• Section 2 “Features”, 5^thbullet item re-written; added Footnote 1 on page 1

• Section 7.3 “FIFO Control Register (FCR)”, 1^stparagraph: removed phrase “and select the DMA

mode”

• Table 22 “Limiting values”:

–

symbol V_nsplit to show 2 separate conditions: “at D7 to D0 pins” and “at input only pins”

SC16C751B_1

20080424 Product data sheet

-

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

30 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

15.2 Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

16. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

SC16C751B_2

Product data sheet

Rev. 02 — 10 October 2008

31 of 32

SC16C751B

NXP Semiconductors

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

17. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

14

Revision history . . . . . . . . . . . . . . . . . . . . . . . 30

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

15

Legal information . . . . . . . . . . . . . . . . . . . . . . 31

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 31

15.1

15.2

15.3

15.4

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

16

17

Contact information . . . . . . . . . . . . . . . . . . . . 31

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6

Functional description . . . . . . . . . . . . . . . . . . . 5

Internal registers. . . . . . . . . . . . . . . . . . . . . . . . 5

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . 6

Hardware ﬂow control. . . . . . . . . . . . . . . . . . . . 7

Time-out interrupts . . . . . . . . . . . . . . . . . . . . . . 7

Programmable baud rate generator . . . . . . . . . 7

Special software initialization sequence . . . . . . 9

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Low power mode . . . . . . . . . . . . . . . . . . . . . . . 9

Loopback mode . . . . . . . . . . . . . . . . . . . . . . . . 9

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

7

7.1

Register descriptions . . . . . . . . . . . . . . . . . . . 11

Transmit and Receive Holding Registers

(THR and RHR) . . . . . . . . . . . . . . . . . . . . . . . 12

Interrupt Enable Register (IER) . . . . . . . . . . . 12

IER versus Receive FIFO interrupt mode

7.2

7.2.1

operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

IER versus Receive/Transmit FIFO

7.2.2

polled mode operation . . . . . . . . . . . . . . . . . . 13

FIFO Control Register (FCR) . . . . . . . . . . . . . 14

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Interrupt Status Register (ISR) . . . . . . . . . . . . 15

Line Control Register (LCR) . . . . . . . . . . . . . . 16

Modem Control Register (MCR) . . . . . . . . . . . 18

Line Status Register (LSR). . . . . . . . . . . . . . . 19

Modem Status Register (MSR). . . . . . . . . . . . 20

Scratchpad Register (SPR) . . . . . . . . . . . . . . 20

SC16C751B external reset conditions . . . . . . 20

7.3

7.3.1

7.4

7.5

7.6

7.7

7.8

7.9

7.10

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 21

Static characteristics. . . . . . . . . . . . . . . . . . . . 21

Dynamic characteristics . . . . . . . . . . . . . . . . . 22

Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 23

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26

9

10

10.1

11

12

Soldering of SMD packages . . . . . . . . . . . . . . 27

Introduction to soldering . . . . . . . . . . . . . . . . . 27

Wave and reﬂow soldering . . . . . . . . . . . . . . . 27

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 27

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 28

12.1

12.2

12.3

12.4

13

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 29

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 10 October 2008

Document identifier: SC16C751B_2


型号：	SC16C751B
厂家：	NXP
描述：	5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs 5 V ， 3.3 V和2.5 V UART，具有64字节FIFO 先进先出芯片
文件：	总32页 (文件大小：151K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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