SC16C752BIB48,128_技术文档

SC16C752B

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte

FIFOs

Rev. 6 — 30 November 2010

Product data sheet

1. General description

The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with

64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s

(3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission Control

Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during

hardware and software flow control. With the FIFO Rdy register, the software gets the

status of TXRDYn/RXRDYn for all four ports in one access. On-chip status registers

provide the user with error indications, operational status, and modem interface control.

System interrupts may be tailored to meet user requirements. An internal loopback

capability allows on-board diagnostics.

The UART transmits data, sent to it over the peripheral 8-bit bus, on the TXn signal and

receives characters on the RXn signal. Characters can be programmed to be 5 bits, 6 bits,

7 bits, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be

programmed to interrupt at different trigger levels. The UART generates its own desired

baud rate based upon a programmable divisor and its input clock. It can transmit even,

odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing

errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The

UART also contains a software interface for modem control operations, and has software

flow control and hardware flow control capabilities.

The SC16C752B is available in plastic LQFP48 and HVQFN32 packages.

2. Features and benefits

Pin compatible with SC16C2550 with additional enhancements

Up to 5 Mbit/s baud rate (at 3.3 V and 5 V; at 2.5 V maximum baud rate is 3 Mbit/s)

64-byte transmit FIFO

64-byte receive FIFO with error flags

Programmable and selectable transmit and receive FIFO trigger levels for DMA and

interrupt generation

Software/hardware flow control

Programmable Xon/Xoff characters

Programmable auto-RTS and auto-CTS

Optional data flow resume by Xon any character

DMA signalling capability for both received and transmitted data

Supports 5 V, 3.3 V and 2.5 V operation

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

5 V tolerant on input only pins¹

Software selectable baud rate generator

Prescaler provides additional divide-by-4 function

Industrial temperature range (−40 °C to +85 °C)

Pin and software compatible with SC16C752, TL16C752

Fast data bus access time

Programmable Sleep mode

Programmable serial interface characteristics

5-bit, 6-bit, 7-bit, or 8-bit characters

Even, odd, or no parity bit generation and detection

1, 1.5, or 2 stop bit generation

False start bit detection

Complete status reporting capabilities in both normal and Sleep mode

Line break generation and detection

Internal test and loopback capabilities

Fully prioritized interrupt system controls

Modem control functions (CTS, RTS, DSR, DTR, RI, and CD)

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

SC16C752BIB48

SC16C752BIBS

LQFP48

HVQFN32

plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm

SOT313-2

SOT617-1

plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 × 5 × 0.85 mm

1. For data bus, D7 to D0, see Table 24 “Limiting values”.

SC16C752B

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 30 November 2010

2 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

4. Block diagram

SC16C752B

TRANSMIT

FIFO

TRANSMIT

SHIFT

TXA, TXB

REGISTERS

REGISTER

D0 to D7

IOR

DATA BUS

AND

IOW

RESET

CONTROL

LOGIC

FLOW

CONTROL

LOGIC

RECEIVE

FIFO

RECEIVE

SHIFT

RXA, RXB

REGISTERS

REGISTER

FLOW

CONTROL

LOGIC

A0 to A2

CSA

REGISTER

SELECT

LOGIC

CSB

DTRA, DTRB

RTSA, RTSB

OPA, OPB

MODEM

CONTROL

LOGIC

CTSA, CTSB

RIA, RIB

CDA, CDB

DSRA, DSRB

INTA, INTB

TXRDYA, TXRDYB

RXRDYA, RXRDYB

CLOCK AND

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

002aaa600

XTAL1

XTAL2

Fig 1. Block diagram

SC16C752B

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Product data sheet

Rev. 6 — 30 November 2010

3 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

5. Pinning information

5.1 Pinning

1

2

36

35

34

33

32

31

30

29

28

27

26

25

D5

D6

RESET

DTRB

DTRA

RTSA

OPA

RXRDYA

INTA

INTB

A0

3

D7

4

RXB

RXA

TXRDYB

TXA

5

6

SC16C752BIB48

7

8

TXB

9

OPB

CSA

CSB

n.c.

10

11

12

A1

A2

n.c.

002aaa601

Fig 2. Pin configuration for LQFP48

terminal 1

index area

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

D6

D7

RESET

RTSA

OPA

INTA

INTB

A0

RXB

RXA

TXA

TXB

OPB

CSA

SC16C752BIBS

A1

A2

002aaa950

Transparent top view

Fig 3. Pin configuration for HVQFN32

SC16C752B

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Product data sheet

Rev. 6 — 30 November 2010

4 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

5.2 Pin description

Table 2.

Symbol

Pin description

Type Description

LQFP48 HVQFN32

A0

28

27

26

40

16

19

18

17

-

I

i

Address 0 select bit. Internal registers address selection.

Address 1 select bit. Internal registers address selection.

Address 2 select bit. Internal registers address selection.

A1

A2

CDA

CDB

Carrier Detect (active LOW). These inputs are associated with individual

UART channels A and B. A logic LOW on these pins indicates that a carrier has

been detected by the modem for that channel. The state of these inputs is

reflected in the Modem Status Register (MSR).

-

CSA

CSB

10

11

8

9

I

Chip Select (active LOW). These pins enable data transfers between the user

CPU and the SC16C752B for the channel(s) addressed. Individual UART

sections (A, B) are addressed by providing a logic LOW on the respective CSA

and CSB pins.

CTSA

CTSB

38

23

25

16

I

Clear to Send (active LOW). These inputs are associated with individual UART

channels A and B. A logic 0 (LOW) on the CTSn pins indicates the modem or

data set is ready to accept transmit data from the SC16C752B. Status can be

tested by reading MSR[4]. These pins only affect the transmit and receive

operations when auto-CTS function is enabled via the Enhanced Feature

Register EFR[7] for hardware flow control operation.

D0

44

45

46

47

48

1

27

28

29

30

31

32

1

I/O

I

Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for

transferring information to or from the controlling CPU. D0 is the least significant

bit and the first data bit in a transmit or receive serial data stream.

D1

D2

D3

D4

D5

D6

2

D7

3

2

DSRA

DSRB

39

20

-

Data Set Ready (active LOW). These inputs are associated with individual

UART channels A and B. A logic 0 (LOW) on these pins indicates the modem or

data set is powered-on and is ready for data exchange with the UART. The state

of these inputs is reflected in the Modem Status Register (MSR).

-

I

DTRA

DTRB

34

35

-

O

Data Terminal Ready (active LOW). These outputs are associated with

individual UART channels A and B. A logic 0 (LOW) on these pins indicates that

the SC16C752B is powered-on and ready. These pins can be controlled via the

modem control register. Writing a logic 1 to MCR[0] will set the DTRn output to

logic 0 (LOW), enabling the modem. The output of these pins will be a logic 1

after writing a logic 0 to MCR[0], or after a reset.

GND

INTA

INTB

17

30

29

13

21

20

I

Signal and power ground

O

Interrupt A and B (active HIGH). These pins provide individual channel

interrupts INTA and INTB. INTA and INTB are enabled when MCR[3] is set to a

logic 1, interrupt sources are enabled in the Interrupt Enable Register (IER).

Interrupt conditions include: receiver errors, available receiver buffer data,

available transmit buffer space, or when a modem status flag is detected. INTA,

INTB are in the high-impedance state after reset.

IOR

19

14

I

Input/Output Read strobe (active LOW). A HIGH-to-LOW transition on IOR

will load the contents of an internal register defined by address bits A0 to A2

onto the SC16C752B data bus (D0 to D7) for access by external CPU.

SC16C752B

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 30 November 2010

5 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Table 2.

Symbol

Pin description …continued

Type Description

LQFP48 HVQFN32

IOW

n.c.

15

12

I

Input/Output Write strobe (active LOW). A LOW-to-HIGH transition on IOW

will transfer the contents of the data bus (D0 to D7) from the external CPU to an

internal register that is defined by address bits A0 to A2 and CSA and CSB.

12, 24,

25, 37

-

not connected

OPA

OPB

32

9

22

7

O

User defined outputs. This function is associated with individual channels A

and B. The state of these pins is defined by the user through the software

settings of MCR[3]. INTA-INTB are set to active mode and OPA-OPB to a logic 0

when MCR[3] is set to a logic 1. INTA-INTB are set to the 3-state mode and

OPA-OPB to a logic 1 when MCR[3] is set to a logic 0. The output of these two

pins is HIGH after reset.

RESET

36

24

I

Reset. This pin will reset the internal registers and all the outputs. The UART

transmitter output and the receiver input will be disabled during reset time.

RESET is an active HIGH input.

RIA

RIB

41

21

-

I

Ring Indicator (active LOW). These inputs are associated with individual

UART channels, A and B. A logic 0 on these pins indicates the modem has

received a ringing signal from the telephone line. A LOW-to-HIGH transition on

these input pins generates a modem status interrupt, if enabled. The state of

these inputs is reflected in the Modem Status Register (MSR).

RTSA

RTSB

33

22

23

15

O

Request to Send (active LOW). These outputs are associated with individual

UART channels, A and B. A logic 0 on the RTSn pin indicates the transmitter

has data ready and waiting to send. Writing a logic 1 in the modem control

register MCR[1] will set this pin to a logic 0, indicating data is available. After a

reset these pins are set to a logic 1. These pins only affect the transmit and

receive operations when auto-RTS function is enabled via the Enhanced

Feature Register (EFR[6]) for hardware flow control operation.

RXA

RXB

5

4

3

I

Receive data input. These inputs are associated with individual serial channel

data to the SC16C752B. During the local Loopback mode, these RXn input pins

are disabled and transmit data is connected to the UART receive input internally.

RXRDYA 31

RXRDYB 18

-

O

Receive Ready (active LOW). RXRDYA or RXRDYB goes LOW when the

trigger level has been reached or the FIFO has at least one character. It goes

HIGH when the receive FIFO is empty.

TXA

TXB

7

8

5

6

O

Transmit data A, B. These outputs are associated with individual serial transmit

channel data from the SC16C752B. During the local Loopback mode, the TXn

output pin is disabled and transmit data is internally connected to the UART

receive input.

TXRDYA

TXRDYB

43

6

-

O

Transmit Ready (active LOW). TXRDYA or TXRDYB go LOW when there are

at least a trigger level number of spaces available or when the FIFO is empty. It

goes HIGH when the FIFO is full or not empty.

V_CC

42

13

26

10

I

Power supply input

XTAL1

Crystal or external clock input. Functions as a crystal input or as an external

clock input. A crystal can be connected between XTAL1 and XTAL2 to form an

internal oscillator circuit (see Figure 13). Alternatively, an external clock can be

connected to this pin to provide custom data rates.

XTAL2

14

11

O

Output of the crystal oscillator or buffered clock. (See also XTAL1.) XTAL2

is used as a crystal oscillator output or a buffered clock output.

SC16C752B

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Product data sheet

Rev. 6 — 30 November 2010

6 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6. Functional description

The SC16C752B UART is pin-compatible with the SC16C2550 UART. It provides more

enhanced features. All additional features are provided through a special Enhanced

Feature Register (EFR).

The UART will perform serial-to-parallel conversion on data characters received from

peripheral devices or modems, and parallel-to-parallel conversion on data characters

transmitted by the processor. The complete status of each channel of the SC16C752B

UART can be read at any time during functional operation by the processor.

The SC16C752B can be placed in an alternate mode (FIFO mode) relieving the processor

of excessive software overhead by buffering received/transmitted characters. Both the

receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of

error status per byte for the receiver FIFO) and have selectable or programmable trigger

levels. Primary outputs RXRDYn and TXRDYn allow signalling of DMA transfers.

The SC16C752B has selectable hardware flow control and software flow control.

Hardware flow control significantly reduces software overhead and increases system

efficiency by automatically controlling serial data flow using the RTSn output and CTSn

input signals. Software flow control automatically controls data flow by using

programmable Xon/Xoff characters.

The UART includes a programmable baud rate generator that can divide the timing

reference clock input by a divisor between 1 and (2¹⁶− 1).

6.1 Trigger levels

The SC16C752B provides independent selectable and programmable trigger levels for

both receiver and transmitter DMA and interrupt generation. After reset, both transmitter

and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of

one byte. The selectable trigger levels are available via the FIFO Control Register (FCR).

The programmable trigger levels are available via the Trigger Level Register (TLR).

6.2 Hardware flow control

Hardware flow control is comprised of auto-CTS and auto-RTS. Auto-CTS and auto-RTS

can be enabled/disabled independently by programming EFR[7:6].

With auto-CTS, CTSn must be active before the UART can transmit data.

Auto-RTS only activates the RTSn output when there is enough room in the FIFO to

receive data and de-activates the RTSn output when the receive FIFO is sufficiently full.

The halt and resume trigger levels in the TCR determine the levels at which RTSn is

activated/deactivated.

If both auto-CTS and auto-RTS are enabled, when RTSn is connected to CTSn, data

transmission does not occur unless the receiver FIFO has empty space. Thus, overrun

errors are eliminated during hardware flow control. If not enabled, overrun errors occur if

the transmit data rate exceeds the receive FIFO servicing latency.

SC16C752B

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 30 November 2010

7 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

UART 1

UART 2

SERIAL TO

PARALLEL

TO SERIAL

RXn

TXn

RX

TX

FIFO

RTSn

CTSn

FLOW

CONTROL

D7 to D0

PARALLEL

TO SERIAL

SERIAL TO

PARALLEL

TXn

RXn

TX

RX

FIFO

CTSn

RTSn

FLOW

CONTROL

002aaf905

Fig 4. Auto flow control (auto-RTS and auto-CTS) example

6.2.1 Auto-RTS

Auto-RTS data flow control originates in the receiver block (see Figure 1 “Block diagram”

on page 3). Figure 5 shows RTSn functional timing. The receiver FIFO trigger levels used

in auto-RTS are stored in the TCR. RTSn is active if the RX FIFO level is below the halt

trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTSn is

de-asserted. The sending device (e.g., another UART) may send an additional byte after

the trigger level is reached (assuming the sending UART has another byte to send)

because it may not recognize the de-assertion of RTSn until it has begun sending the

additional byte. RTSn is automatically reasserted once the receiver FIFO reaches the

resume trigger level programmed via TCR[7:4]. This re-assertion allows the sending

device to resume transmission.

RXn

Start

byte N

Stop

Start

byte N + 1

Stop

Start

RTSn

1

2

N

N+1

IOR

002aaf906

N = receiver FIFO trigger level.

The two blocks in dashed lines cover the case where an additional byte is sent, as described in Section 6.2.1.

Fig 5. RTS functional timing

SC16C752B

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Product data sheet

Rev. 6 — 30 November 2010

8 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.2.2 Auto-CTS

The transmitter circuitry checks CTSn before sending the next data byte. When CTSn is

active, the transmitter sends the next byte. To stop the transmitter from sending the

following byte, CTSn must be de-asserted before the middle of the last stop bit that is

currently being sent. The auto-CTS function reduces interrupts to the host system. When

flow control is enabled, CTSn level changes do not trigger host interrupts because the

device automatically controls its own transmitter. Without auto-CTS, the transmitter sends

any data present in the transmit FIFO and a receiver overrun error may result.

Start

byte 0 to 7

Stop

TXn

Start

byte 0 to 7

Stop

CTSn

002aaa227

When CTSn is LOW, the transmitter keeps sending serial data out.

When CTSn goes HIGH before the middle of the last stop bit of the current byte, the transmitter finishes sending the current

byte, but is does not send the next byte.

When CTSn goes from HIGH to LOW, the transmitter begins sending data again.

Fig 6. CTS functional timing

6.3 Software flow control

Software flow control is enabled through the enhanced feature register and the modem

control register. Different combinations of software flow control can be enabled by setting

different combinations of EFR[3:0]. Table 3 shows software flow control options.

Table 3.

Software flow control options (EFR[0:3])

EFR[3]

EFR[2]

EFR[1]

EFR[0]

TX, RX software flow controls

no transmit flow control

0

1

0

1

X

1

0

1

X

0

X

0

1

0

1

X

0

1

transmit Xon1, Xoff1

transmit Xon2, Xoff2

transmit Xon1, Xon2, Xoff1, Xoff2

no receive flow control

receiver compared Xon1, Xoff1

receiver compares Xon2, Xoff2

transmit Xon1, Xoff1

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

transmit Xon2, Xoff2

0

1

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

transmit Xon1, Xon2, Xoff1, Xoff2

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

SC16C752B

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 30 November 2010

9 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

There are two other enhanced features relating to software flow control:

• Xon Any function (MCR[5]): Operation will resume after receiving any character

after recognizing the Xoff character. It is possible that an Xon1 character is

recognized as an Xon Any character, which could cause an Xon2 character to be

written to the receive FIFO.

• Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the

special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The

Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the

receive FIFO.

6.3.1 Receive flow control

When software flow control operation is enabled, the SC16C752B will compare incoming

data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be

received sequentially). When the correct Xoff character are received, transmission is

halted after completing transmission of the current character. Xoff detection also sets

IIR[4] (if enabled via IER[5]) and causes INTA/INTB to go HIGH.

To resume transmission, an Xon1/Xon2 character must be received (in certain cases

Xon1 and Xon2 must be received sequentially). When the correct Xon characters are

received, IIR[4] is cleared, and the Xoff interrupt disappears.

6.3.2 Transmit flow control

Xoff1/Xoff2 character is transmitted when the receive FIFO has passed the halt trigger

level programmed in TCR[3:0].

Xon1/Xon2 character is transmitted when the receive FIFO reaches the resume trigger

level programmed in TCR[7:4].

The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an

ordinary byte from the FIFO. This means that even if the word length is set to be 5, 6, or 7

characters, then the 5, 6, or 7 least significant bits of Xoff1/Xoff2, Xon1/Xoff2 will be

transmitted. (Note that the transmission of 5 bits, 6 bits, or 7 bits of a character is seldom

done, but this functionality is included to maintain compatibility with earlier designs.)

It is assumed that software flow control and hardware flow control will never be enabled

simultaneously. Figure 7 shows an example of software flow control.

SC16C752B

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Product data sheet

Rev. 6 — 30 November 2010

10 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.3.3 Software flow control example

UART1

UART2

TRANSMIT FIFO

RECEIVE FIFO

data

PARALLEL-TO-SERIAL

SERIAL-TO-PARALLEL

Xon1 WORD

SERIAL-TO-PARALLEL

PARALLEL-TO-SERIAL

Xon1 WORD

Xoff–Xon–Xoff

Xon2 WORD

Xoff1 WORD

compare

programmed

Xon-Xoff

Xoff2 WORD

characters

002aaa229

Fig 7. Software flow control example

6.3.3.1 Assumptions

UART1 is transmitting a large text file to UART2. Both UARTs are using software flow

control with single character Xoff (0Fh) and Xon (0Dh) tokens. Both have Xoff threshold

(TCR[3:0] = Fh) set to 60, and Xon threshold (TCR[7:4] = 8h) set to 32. Both have the

interrupt receive threshold (TLR[7:4] = Dh) set to 52.

UART 1 begins transmission and sends 52 characters, at which point UART2 will

generate an interrupt to its processor to service the receive FIFO, but assume the

interrupt latency is fairly long. UART1 will continue sending characters until a total of 60

characters have been sent. At this time, UART2 will transmit a 0Fh to UART1, informing

UART1 to halt transmission. UART1 will likely send the 61^stcharacter while UART2 is

sending the Xoff character. Now UART2 is serviced and the processor reads enough data

out of the receive FIFO that the level drops to 32. UART2 will now send a 0Dh to UART1,

informing UART1 to resume transmission.

SC16C752B

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 30 November 2010

11 of 47

SC16C752B

NXP Semiconductors

6.4 Reset

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Table 4 summarizes the state of register after reset.

Table 4.

Register

Register reset functions^[1]

Reset control

RESET

Reset state

Interrupt Enable Register

Interrupt Identification Register

FIFO Control Register

all bits cleared

bit 0 is set; all other bits cleared

all bits cleared

Line Control Register

reset to 0001 1101 (1Dh)

all bits cleared

Modem Control Register

Line Status Register

bit 5 and bit 6 set; all other bits cleared

bits [3:0] cleared; bits [7:4] input signals

all bits cleared

Modem Status Register

Enhanced Feature Register

Receiver Holding Register

Transmitter Holding Register

Transmission Control Register

Trigger Level Register

pointer logic cleared

all bits cleared

[1] Registers DLL, DLM, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the top-level reset signal

RESET, i.e., they hold their initialization values during reset.

Table 5 summarizes the state of registers after reset.

Table 5.

Signal

TXn

Signal RESET functions

Reset control

Reset state

HIGH

RESET

RTSn

HIGH

DTRn

HIGH

RXRDYn

TXRDYn

HIGH

LOW

SC16C752B

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Product data sheet

Rev. 6 — 30 November 2010

12 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

6.5 Interrupts

The SC16C752B has interrupt generation and prioritization (six prioritized levels of

interrupts) capability. The Interrupt Enable Register (IER) enables each of the six types of

interrupts and the INTA/INTB signal in response to an interrupt generation. The IER can

also disable the interrupt system by clearing bit 0 to bit 3 and bit 5 to bit 7. When an

interrupt is generated, the IIR indicates that an interrupt is pending and provides the type

of interrupt through IIR[5:0]. Table 6 summarizes the interrupt control functions.

Table 6.

IIR[5:0]

Interrupt control functions

Priority

level

Interrupt type

Interrupt source

Interrupt reset method

00 0001

00 0110

None

1

none

receiver line status

OE, FE, PE, or BI errors occur in

characters in the RX FIFO

FE, PE, BI: all erroneous

characters are read from the

RX FIFO.

OE: read LSR

read RHR

00 1100

00 0100

2

RX time-out

stale data in RX FIFO

DRDY (data ready)

(FIFO disable)

RHR interrupt

read RHR

RX FIFO above trigger level

(FIFO enable)

00 0010

3

THR interrupt

TFE (THR empty)

read IIR or a write to the THR

(FIFO disable)

TX FIFO passes above trigger level

(FIFO enable)

00 0000

01 0000

4

5

modem status

Xoff interrupt

MSR[3:0] = logic 0

read MSR

receive Xoff character(s)/special

character

receive Xon character(s)/Read of

IIR

10 0000

6

CTS, RTS

RTSn pin or CTSn pin change state

from active (LOW) to inactive (HIGH)

read IIR

It is important to note that for the framing error, parity error, and break conditions, LSR[7]

generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO,

and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always

represent the error status for the received character at the top of the RX FIFO. Reading

the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of

the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.

For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt

is cleared by an Xon flow character detection. If a special character detection caused the

interrupt, the interrupt is cleared by a read of the LSR.

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6.5.1 Interrupt mode operation

In interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of the

receiver and transmitter by an interrupt signal, INTA/INTB. Therefore, it is not necessary

to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be

serviced. Figure 8 shows interrupt mode operation.

IIR

IOW / IOR

INTn

PROCESSOR

IER

1

THR

RHR

002aaf908

Fig 8. Interrupt mode operation

6.5.2 Polled mode operation

In polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be

checked by polling the Line Status Register (LSR). This mode is an alternative to the FIFO

interrupt mode of operation where the status of the receiver and transmitter is

automatically known by means of interrupts sent to the CPU. Figure 9 shows FIFO polled

mode operation.

LSR

IOW / IOR

PROCESSOR

IER

0

THR

RHR

002aaa231

Fig 9. FIFO polled mode operation

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6.6 DMA operation

There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by

FCR[3].

In DMA mode 0 or FIFO disable (FCR[0] = 0) DMA occurs in single character transfers. In

DMA mode 1, multi-character (or block) DMA transfers are managed to relieve the

processor for longer periods of time.

6.6.1 Single DMA transfers (DMA mode 0/FIFO disable)

Figure 10 shows TXRDYn and RXRDYn in DMA mode 0/FIFO disable.

transmit

receive

TXRDYn

RXRDYn

at least one

wrptr

rdptr

location filled

TXRDYn

RXRDYn

FIFO EMPTY

wrptr

rdptr

002aaa232

Fig 10. TXRDYn and RXRDYn in DMA mode 0/FIFO disable

6.6.1.1 Transmitter

When empty, the TXRDYn signal becomes active. TXRDYn will go inactive after one

character has been loaded into it.

6.6.1.2 Receiver

RXRDYn is active when there is at least one character in the FIFO. It becomes inactive

when the receiver is empty.

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6.6.2 Block DMA transfers (DMA mode 1)

Figure 11 shows TXRDYn and RXRDYn in DMA mode 1.

transmit

receive

wrptr

trigger

level

TXRDYn

rdptr

RXRDYn

at least one

FIFO full

location filled

trigger

level

TXRDYn

wrptr

RXRDYn

FIFO EMPTY

rdptr

002aaa234

Fig 11. TXRDYn and RXRDYn in DMA mode 1

6.6.2.1 Transmitter

TXRDYn is active when there is a trigger level number of spaces available. It becomes

inactive when the FIFO is full.

6.6.2.2 Receiver

RXRDYn becomes active when the trigger level has been reached, or when a time-out

interrupt occurs. It will go inactive when the FIFO is empty or an error in the receive FIFO

is flagged by LSR[7].

6.7 Sleep mode

Sleep mode is an enhanced feature of the SC16C752B UART. It is enabled when EFR[4],

the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when:

• The serial data input line, RXn, is idle (see Section 6.8 “Break and time-out

conditions”).

• The transmit FIFO and transmit shift register are empty.

• There are no interrupts pending except THR and time-out interrupts.

Remark: Sleep mode will not be entered if there is data in the receive FIFO.

In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are

clocked using these clocks, the power consumption is greatly reduced. The UART will

wake up when any change is detected on the RXn line, when there is any change in the

state of the modem input pins, or if data is written to the transmit FIFO.

Remark: Writing to the divisor latches DLL and DLM to set the baud clock must not be

done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]

before writing to DLL or DLM.

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6.8 Break and time-out conditions

An RX idle condition is detected when the receiver line, RXn, has been HIGH for

4 character time. The receiver line is sampled midway through each bit.

When a break condition occurs, the TXn line is pulled LOW. A break condition is activated

by setting LCR[6].

6.9 Programmable baud rate generator

The SC16C752B UART contains a programmable baud generator that takes any clock

input and divides it by a divisor in the range between 1 and (2¹⁶− 1). An additional

divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in

Figure 12. The output frequency of the baud rate generator is 16 × the baud rate. The

formula for the divisor is given in Equation 1:

XTAL1 crystal input frequency

⎛

⎝

⎞

⎠

-----------------------------------------------------------------------------------

prescaler

divisor =

(1)

----------------------------------------------------------------------------------------

(desired baud rate × 16)

Where:

prescaler = 1, when MCR[7] is set to logic 0 after reset (divide-by-1 clock selected);

prescaler = 4, when MCR[7] is set to logic 1 after reset (divide-by-4 clock selected).

Remark: The default value of prescaler after reset is divide-by-1.

Figure 12 shows the internal prescaler and baud rate generator circuitry.

PRESCALER

MCR[7] = 0

LOGIC

(DIVIDE-BY-1)

internal

XTAL1

INTERNAL

OSCILLATOR

LOGIC

BAUD RATE

GENERATOR

LOGIC

baud rate

clock for

transmitter

and receiver

input clock

XTAL2

reference

clock

PRESCALER

LOGIC

(DIVIDE-BY-4)

MCR[7] = 1

002aaa233

Fig 12. Prescaler and baud rate generator block diagram

DLL and DLM must be written to in order to program the baud rate. DLL and DLM are the

least significant and most significant byte of the baud rate divisor. If DLL and DLM are

both zero, the UART is effectively disabled, as no baud clock will be generated.

Remark: The programmable baud rate generator is provided to select both the transmit

and receive clock rates.

Table 7 and Table 8 show the baud rate and divisor correlation for crystal with frequency

1.8432 MHz and 3.072 MHz, respectively.

Figure 13 shows the crystal clock circuit reference.

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Table 7.

Baud rates using a 1.8432 MHz crystal

Desired baud rate

Divisor used to generate

Percent error difference

16× clock

between desired and actual

50

2304

1536

1047

857

768

384

192

96

75

110

0.026

0.058

134.5

150

300

600

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

56000

64

58

0.69

48

32

24

16

12

6

3

2

2.86

Table 8.

Baud rates using a 3.072 MHz crystal

Desired baud rate

Divisor used to generate

Percent error difference

16× clock

between desired and actual

50

2304

2560

1745

1428

1280

640

320

160

107

96

75

110

0.026

0.034

134.5

150

300

600

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

0.312

80

53

0.628

1.23

40

27

20

10

5

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XTAL1

XTAL2

XTAL1

XTAL2

1.5 kΩ

X1

1.8432 MHz

C1

22 pF

C2

33 pF

C1

22 pF

C2

47 pF

002aaa870

Fig 13. Crystal oscillator connections

7. Register descriptions

Each register is selected using address lines A0, A1, A2, and in some cases, bits from

other registers. The programming combinations for register selection are shown in

Table 9.

A1

Register map - read/write properties

A2

0

1

0

1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Read mode

Write mode

0

1

0

1

0

1

0

1

Receive Holding Register (RHR)

Interrupt Enable Register (IER)

Interrupt Identification Register (IIR)

Line Control Register (LCR)

Modem Control Register (MCR)^[1]

Line Status Register (LSR)

Modem Status Register (MSR)

Scratchpad Register (SPR)

Divisor Latch LSB (DLL)^[2][3]

Divisor Latch MSB (DLM)^[2][3]

Enhanced Feature Register (EFR)^[2][4]

Xon1 word^[2][4]

Transmit Holding Register (THR)

Interrupt Enable Register

FIFO Control Register (FCR)

Line Control Register

Modem Control Register^[1]

Scratchpad Register

Divisor Latch LSB^[2][3]

Divisor Latch MSB^[2][3]

Enhanced Feature Register^[2][4]

Xon1 word^[2][4]

Xon2 word^[2][4]

Xoff1 word^[2][4]

Xoff2 word^[2][4]

Xon2 word^[2][4]

Xoff1 word^[2][4]

Xoff2 word^[2][4]

Transmission Control Register (TCR)^[2][5]Transmission Control Register^[2][5]

Trigger Level Register (TLR)^[2][5]

FIFO ready register^[2][6]

Trigger Level Register^[2][5]

[1] MCR[7] can only be modified when EFR[4] is set.

[2] Accessed by a combination of address pins and register bits.

[3] Accessible only when LCR[7] is logic 1.

[4] Accessible only when LCR is set to 1011 1111 (BFh).

[5] Accessible only when EFR[4] = logic 1 and MCR[6] = logic 1, i.e., EFR[4] and MCR[6] are read/write

enables.

[6] Accessible only when CSA or CSB = logic 0, MCR[2] = logic 1, and loopback is disabled

(MCR[4] = logic 0).

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Table 10 lists and describes the SC16C752B internal registers.

Table 10. SC16C752B internal registers

Read/

Write

A2 A1 A0 Register Bit 7

General register set^[1]

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0

1

RHR

THR

IER

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

THR

bit 0

R

bit 7

bit 6

bit 5

0/Xoff^[2]

W

0/CTS

interrupt interrupt

enable^[2]enable^[2]

0/RTS

0/X sleep modem receive

mode^[2]

Rx data R/W

available

status

interrupt interrupt

line status empty

interrupt interrupt

TX FIFO RX FIFO FIFO

reset reset enable

0

1

0

FCR

RXtrigger RX trigger 0/TX

level

(MSB)

0/TX

DMA

mode

select

W

level (LSB) trigger

level

trigger

level

(LSB)^[2]

(MSB)^[2]

0

1

0

1

0

1

IIR

FCR[0]

DLAB

FCR[0]

0/CTS,

RTS

0/Xoff

interrupt interrupt

priority priority

interrupt interrupt

R

priority

bit 0

status

bit 2

bit 1

LCR

MCR

LSR

break

control bit

set parity parity type parity

number of word

enable stop bits length

word

length

bit 0

R/W

R

select

bit 1

1× or

TCR and

TLR

enable^[2]

0/Xon

Any^[2]

0/enable

loopback enable ready

OP enable

IRQ

FIFO

RTS

DTR

1× / 4

clock^[2]

0/error in THR and

RX FIFO TSR empty empty

THR

break

interrupt

framing parity

overrun

error

data in

receiver

error

ΔCD

bit 3

0

error

ΔRI

bit 2

0

1

0

1

0

1

MSR

SPR

TCR

TLR

CD

bit 7

0

RI

DSR

bit 5

CTS

bit 4

ΔDSR

bit 1

ΔCTS

bit 0

R

bit 6

0

R/W

bit 1

FIFO

Rdy

RX FIFO RX FIFO

B status

TX FIFO TX FIFO R

B status A status

A status

Special register set^[3]

0

DLL

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 9

bit 0

bit 8

R/W

0

1

DLM

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

Enhanced register set^[4]

0

1

0

EFR

auto CTS auto RTS

Special

Enable

software software software software R/W

character IER[7:4],

flow

detect

FCR[5:4], control control

control

bit 1

control

bit 0

MCR[7:5] bit 3

bit 2

1

0

1

0

1

0

1

Xon1

Xon2

Xoff1

Xoff2

bit 7

bit 6

bit 5

bit 4

bit 3

bit 1

bit 0

R/W

[1] These registers are accessible only when LCR[7] = logic 0.

[2] These bits can only be modified if register bit EFR[4] is enabled, i.e., if enhanced functions are enabled.

[3] The Special register set is accessible only when LCR[7] is set to a logic 1.

[4] Enhanced Feature Register; Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to BFh.

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5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Remark: Refer to the notes under Table 9 for more register access information.

7.1 Receiver Holding Register (RHR)

The receiver section consists of the Receiver Holding Register (RHR) and the Receiver

Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data

from the RX terminal. The data is converted to parallel data and moved to the RHR. The

receiver section is controlled by the Line Control Register. If the FIFO is disabled, location

zero of the FIFO is used to store the characters.

Remark: In this case, characters are overwritten if overflow occurs.

If overflow occurs, characters are lost. The RHR also stores the error status bits

associated with each character.

7.2 Transmit Holding Register (THR)

The transmitter section consists of the Transmit Holding Register (THR) and the Transmit

Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and

shifts it into the TSR, where it is converted to serial data and moved out on the TXn

terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are

lost if overflow occurs.

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7.3 FIFO Control Register (FCR)

This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting

transmitter and receiver trigger levels, and selecting the type of DMA signalling. Table 11

shows FIFO control register bit settings.

Table 11. FIFO Control Register bits description

Bit

Symbol

Description

7:6

FCR[7](MSB), RX trigger. Sets the trigger level for the receive FIFO.

FCR[6] (LSB)

00 - 8 characters

01 - 16 characters

10 - 56 characters

11 - 60 characters

5:4

FCR[5](MSB), TX trigger. Sets the trigger level for the transmit FIFO.

FCR[4] (LSB)

00 - 8 spaces

01 - 16 spaces

10 - 32 spaces

11 - 56 spaces

FCR[5:4] can only be modified and enabled when EFR[4] is set. This is

because the transmit trigger level is regarded as an enhanced function.

3

2

FCR[3]

FCR[2]

DMA mode select.

logic 0 = set DMA mode ‘0’

logic 1 = set DMA mode ‘1’

Reset transmit FIFO.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = Clears the contents of the transmit FIFO and resets the FIFO

counter logic (the transmit shift register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

1

0

FCR[1]

FCR[0]

Reset receive FIFO.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = Clears the contents of the receive FIFO and resets the FIFO

counter logic (the receive shift register is not cleared or altered). This bit

will return to a logic 0 after clearing the FIFO.

FIFO enable.

logic 0 = disable the transmit and receive FIFO (normal default

condition)

logic 1 = enable the transmit and receive FIFO.

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7.4 Line Control Register (LCR)

This register controls the data communication format. The word length, number of stop

bits, and parity type are selected by writing the appropriate bits to the LCR. Table 12

shows the Line Control Register bit settings.

Table 12. Line Control Register bits description

Bit

Symbol

Description

7

LCR[7]

Divisor latch enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch enabled

6

5

LCR[6]

LCR[5]

Break control bit. When enabled, the Break control bit causes a break

condition to be transmitted (the TXn output is forced to a logic 0 state). This

condition exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no break condition (normal default condition)

logic 1 = forces the transmitter output (TXn) to a logic 0 to alert the

communication terminal to a line break condition

Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1).

logic 0 = parity is not forced (normal default condition)

LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logic 1 for the

transmit and receive data.

LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logic 0 for the

transmit and receive data.

4

3

LCR[4]

LCR[3]

Parity type select.

logic 0 = odd parity is generated (if LCR[3] = 1)

logic 1 = even parity is generated (if LCR[3] = 1)

Parity enable.

logic 0 = no parity (normal default condition)

logic 1 = a parity bit is generated during transmission and the receiver

checks for received parity

2

LCR[2]

Number of Stop bits. Specifies the number of stop bits.

0 - 1 stop bit (word length = 5, 6, 7, 8)

1 - 1.5 stop bits (word length = 5)

1 - 2 stop bits (word length = 6, 7, 8)

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to be

transmitted or received.

00 - 5 bits

01 - 6 bits

10 - 7 bits

11 - 8 bits

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7.5 Line Status Register (LSR)

Table 13 shows the Line Status Register bit settings.

Table 13. Line Status Register bits description

Bit

Symbol

Description

7

LSR[7]

FIFO data error.

logic 0 = no error (normal default condition)

logic 1 = At least one parity error, framing error, or break indication is in the

receiver FIFO. This bit is cleared when no more errors are present in the

FIFO.

6

5

LSR[6]

LSR[5]

THR and TSR empty. This bit is the Transmit Empty indicator.

logic 0 = transmitter hold and shift registers are not empty

logic 1 = transmitter hold and shift registers are empty

THR empty. This bit is the Transmit Holding Register Empty indicator.

logic 0 = Transmit Holding Register is not empty

logic 1 = Transmit Holding Register is empty. The processor can now load

up to 64 bytes of data into the THR if the transmit FIFO is enabled.

4

3

LSR[4]

LSR[3]

Break interrupt.

logic 0 = No break condition (normal default condition)

logic 1 = A break condition occurred and associated byte is 00, i.e.,

RXn was LOW for one character time frame

Framing error.

logic 0 = no framing error in data being read from receive FIFO (normal

default condition)

logic 1 = framing error occurred in data being read from receive FIFO, i.e.,

received data did not have a valid stop bit.

2

1

0

LSR[2]

LSR[1]

LSR[0]

Parity error.

logic 0 = no parity error (normal default condition)

logic 1 = parity error in data being read from receive FIFO

Overrun error.

logic 0 = no overrun error (normal default condition)

logic 1 = overrun error has occurred

Data in receiver.

logic 0 = no data in receive FIFO (normal default condition)

logic 1 = at least one character in the receive FIFO

When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the

top of the receive FIFO (next character to be read). The LSR[4:2] registers do not

physically exist, as the data read from the receive FIFO is output directly onto the output

data bus, DI[4:2], when the LSR is read. Therefore, errors in a character are identified by

reading the LSR and then reading the RHR.

LSR[7] is set when there is an error anywhere in the receive FIFO, and is cleared only

when there are no more errors remaining in the FIFO.

Reading the LSR does not cause an increment of the receive FIFO read pointer. The

receive FIFO read pointer is incremented by reading the RHR.

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5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

7.6 Modem Control Register (MCR)

The MCR controls the interface with the mode, data set, or peripheral device that is

emulating the modem. Table 14 shows modem control register bit settings.

Table 14. Modem Control Register bits description

Bit

Symbol

MCR[7]^[1]Clock select.

logic 0 = divide-by-1 clock input

logic 1 = divide-by-4 clock input

MCR[6]^[1]TCR and TLR enable.

Description

7

6

5

4

logic 0 = no action

logic 1 = enable access to the TCR and TLR registers

MCR[5]^[1]Xon Any.

logic 0 = disable Xon Any function

logic 1 = enable Xon Any function

Enable loopback.

MCR[4]

MCR[3]

logic 0 = normal operating mode.

logic 1 = enable local Loopback mode (internal). In this mode the MCR[3:0]

signals are looped back into MSR[7:4] and the TXn output is looped back to

the RXn input internally.

3

IRQ enable OP.

logic 0 = forces INTA, INTB outputs to the 3-state mode and OP output to

HIGH state

logic 1 = forces the INTA-INTB outputs to the active state and OP output to

LOW state. In Loopback mode, controls MSR[7].

2

1

MCR[2]

MCR[1]

FIFO Ready enable.

logic 0 = disable the FIFO Rdy register

logic 1 = enable the FIFO Rdy register. In Loopback mode, controls MSR[6].

RTS

logic 0 = force RTSn output to inactive (HIGH)

logic 1 = force RTSn output to active (LOW). In loopback mode, controls

MSR[4]. If auto-RTS is enabled, the RTSn output is controlled by hardware

flow control.

0

MCR[0]

DTR

logic 0 = force DTRn output to inactive (HIGH)

logic 1 = force DTRn output to active (LOW). In Loopback mode, controls

MSR[5].

[1] MCR[7:5] can only be modified when EFR[4] is set, i.e., EFR[4] is a write enable.

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7.7 Modem Status Register (MSR)

This 8-bit register provides information about the current state of the control lines from the

mode, data set, or peripheral device to the processor. It also indicates when a control

input from the modem changes state. Table 15 shows Modem Status Register bit settings

per channel.

Table 15. Modem Status Register bits description

Bit

Symbol

Description

7

MSR[7]

CD (active HIGH, logic 1)^[1]. This bit is the complement of the CDn input

during normal mode. During internal Loopback mode, it is equivalent to

MCR[3].

6

5

4

MSR[6]

MSR[5]

MSR[4]

RI (active HIGH, logic 1)^[1]. This bit is the complement of the RIn input during

normal mode. During internal Loopback mode, it is equivalent to MCR[2].

DSR (active HIGH, logic 1)^[1]. This bit is the complement of the DSRn input

during normal mode. During Internal Loopback mode, it is equivalent MCR[0].

CTS (active HIGH, logic 1)^[1]. This bit is the complement of the CTSn input

during normal mode. During internal Loopback mode, it is equivalent to

MCR[1].

3

2

1

0

MSR[3]

MSR[2]

MSR[1]

MSR[0]

ΔCD. Indicates that CDn input (or MCR[3] in Loopback mode) has changed

state. Cleared on a read.

ΔRI. Indicates that RIn input (or MCR[2] in Loopback mode) has changed

state from LOW to HIGH. Cleared on a read.

ΔDSR. Indicates that DSRn input (or MCR[0] in Loopback mode) has changed

state. Cleared on a read.

ΔCTS. Indicates that CTSn input (or MCR[1] in Loopback mode) has changed

state. Cleared on a read.

[1] The primary inputs RIn, CDn, CTSn, DSRn are all active LOW, but their registered equivalents in the MSR

and MCR (in Loopback) registers are active HIGH.

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7.8 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver

error, RHR interrupt, THR interrupt, Xoff received, or CTSn/RTSn change of state from

LOW to HIGH. The INTA/INTB output signal is activated in response to interrupt

generation. Table 16 shows Interrupt Enable Register bit settings.

Table 16. Interrupt Enable Register bits description

Bit

Symbol

Description

7

IER[7]^[1]

CTS interrupt enable.

logic 0 = disable the CTS interrupt (normal default condition)

logic 1 = enable the CTS interrupt

RTS interrupt enable.

6

5

4

3

IER[6]^[1]

IER[5]^[1]

IER[4]^[1]

IER[3]

logic 0 = disable the RTS interrupt (normal default condition)

logic 1 = enable the RTS interrupt

Xoff interrupt.

logic 0 = disable the Xoff interrupt (normal default condition)

logic 1 = enable the Xoff interrupt

Sleep mode.

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode. See Section 6.7 “Sleep mode” for details.

Modem Status Interrupt.

logic 0 = disable the Modem Status Register interrupt (normal default

condition)

logic 1 = enable the Modem Status Register interrupt

Receive Line Status interrupt.

2

1

0

IER[2]

IER[1]

IER[0]

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

Transmit Holding Register interrupt.

logic 0 = disable the THR interrupt (normal default condition)

logic 1 = enable the THR interrupt

Receive Holding Register interrupt.

logic 0 = disable the RHR interrupt (normal default condition)

logic 1 = enable the RHR interrupt

[1] IER[7:4] can only be modified if EFR[4] is set, i.e., EFR[4] is a write enable. Re-enabling IER[1] will not

cause a new interrupt if the THR is below the threshold.

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7.9 Interrupt Identification Register (IIR)

The IIR is a read-only 8-bit register which provides the source of the interrupt in a

prioritized manner. Table 17 shows Interrupt Identification Register bit settings.

Table 17. Interrupt Identification Register bits description

Bit

7:6

5

Symbol

IIR[7:6]

IIR[5]

Description

Mirror the contents of FCR[0]

RTSn/CTSn LOW-to-HIGH change of state

1 = Xoff/Special character has been detected

3-bit encoded interrupt. See Table 18.

Interrupt status.

4

IIR[4]

3:1

0

IIR[3:1]

IIR[0]

logic 0 = an interrupt is pending

logic 1 = no interrupt is pending

The interrupt priority list is shown in Table 18.

Table 18. Interrupt priority list

Priority IIR[5] IIR[4] IIR[3] IIR[2] IIR[1] IIR[0] Source of the interrupt

level

1

2

3

4

5

0

1

0

1

0

1

0

1

0

1

0

Receiver Line Status error

Receiver time-out interrupt

RHR interrupt

THR interrupt

Modem interrupt

Received Xoff signal/ special

character

6

1

0

CTSn, RTSn change of state from

active (LOW) to inactive (HIGH)

7.10 Enhanced Feature Register (EFR)

This 8-bit register enables or disables the enhanced features of the UART. Table 19

shows the Enhanced Feature Register bit settings.

Table 19. Enhanced Feature Register bits description

Bit Symbol Description

7

EFR[7]

CTS flow control enable.

logic 0 = CTS flow control is disabled (normal default condition)

logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH

signal is detected on the CTSn pin.

6

EFR[6]

RTS flow control enable.

logic 0 = RTS flow control is disabled (normal default condition)

logic 1 = RTS flow control is enabled. The RTSn pin goes HIGH when the

receiver FIFO halt trigger level TCR[3:0] is reached, and goes LOW when the

receiver FIFO resume transmission trigger level TCR[7:4] is reached.

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Table 19. Enhanced Feature Register bits description …continued

Bit Symbol Description

5

EFR[5]

Special character detect.

logic 0 = special character detect disabled (normal default condition)

logic 1 = special character detect enabled. Received data is compared with

Xoff2 data. If a match occurs, the received data is transferred to FIFO and IIR[4]

is set to a logic 1 to indicate a special character has been detected.

4

EFR[4]

Enhanced functions enable bit.

logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],

MCR[7:5]

logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] can

be modified, i.e., this bit is therefore a write enable.

3:0 EFR[3:0] Combinations of software flow control can be selected by programming these bits.

See Table 3 “Software flow control options (EFR[0:3])”.

7.11 Divisor latches (DLL, DLM)

These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock

in the baud rate generator. DLM stores the most significant part of the divisor. DLL stores

the least significant part of the divisor.

Note that DLL and DLM can only be written to before Sleep mode is enabled, i.e., before

IER[4] is set.

7.12 Transmission Control Register (TCR)

This 8-bit register is used to store the receive FIFO threshold levels to stop/start

transmission during hardware/software flow control. Table 20 shows Transmission Control

Register bit settings.

Table 20. Transmission Control Register bits description

Bit

7:4

3:0

Symbol

TCR[7:4]

TCR[3:0]

Description

receive FIFO trigger level to resume transmission (0 to 60).

receive FIFO trigger level to halt transmission (0 to 60).

TCR trigger levels are available from 0 bytes to 60 bytes with a granularity of four.

Remark: TCR can only be written to when EFR[4] = logic 1 and MCR[6] = logic 1. The

programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in

hardware check to make sure this condition is met. Also, the TCR must be programmed

with this condition before auto-RTS or software flow control is enabled to avoid spurious

operation of the device.

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7.13 Trigger Level Register (TLR)

This 8-bit register is pulsed to store the transmit and received FIFO trigger levels used for

DMA and interrupt generation. Trigger levels from 4 to 60 can be programmed with a

granularity of 4. Table 21 shows trigger level register bit settings.

Table 21. Trigger Level Register bits description

Bit

7:4

3:0

Symbol

TLR[7:4]

TLR[3:0]

Description

receive FIFO trigger levels (4 to 60), number of characters available

transmit FIFO trigger levels (4 to 60), number of spaces available

Remark: TLR can only be written to when EFR[4] = logic 1 and MCR[6] = logic 1. If

TLR[3:0] or TLR[7:4] are logic 0, the selectable trigger levels via the FIFO Control

Register (FCR) are used for the transmit and receive FIFO trigger levels. Trigger levels

from 4 bytes to 60 bytes are available with a granularity of four. The TLR should be

programmed for ^N⁄₄, where N is the desired trigger level.

When the trigger level setting in TLR is zero, the SC16C752B uses the trigger level setting

defined in FCR. If TLR has non-zero trigger level value, the trigger level defined in FCR is

discarded. This applies to both transmit FIFO and receive FIFO trigger level setting.

When TLR is used for RX trigger level control, FCR[7:6] should be left at the default state,

i.e., ‘00’.

7.14 FIFO ready register

The FIFO ready register provides real-time status of the transmit and receive FIFOs of

both channels.

Table 22. FIFO Ready Register bits description

Bit

7:6

5

Symbol

Description

FIFO Rdy[7:6]

FIFO Rdy[5]

FIFO Rdy[4]

FIFO Rdy[3:2]

FIFO Rdy[1]

FIFO Rdy[0]

unused; always 0

receive FIFO B status. Related to DMA.

receive FIFO A status. Related to DMA.

unused; always 0

4

3:2

1

transmit FIFO B status. Related to DMA.

transmit FIFO A status. Related to DMA.

0

The FIFO Rdy register is a read-only register that can be accessed when any of the two

UARTs is selected CSA or CSB = logic 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and

loopback is disabled. The address is 111.

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8. Programmer’s guide

The base set of registers that is used during high-speed data transfer have a

straightforward access method. The extended function registers require special access

bits to be decoded along with the address lines. The following guide will help with

programming these registers. Note that the descriptions below are for individual register

access. Some streamlining through interleaving can be obtained when programming all

the registers.

Table 23. Register programming guide

Command

Actions

Read LCR (03h), save in temp

Set baud rate to VALUE1, VALUE2

Set LCR (03h) to 80h

Set DLL (00h) to VALUE1

SET DLM (01h) to VALUE2

Set LCR (03h) to temp

Set Xoff1, Xon1 to VALUE1, VALUE2

Set Xoff2, Xon2 to VALUE1, VALUE2

Read LCR (03h), save in temp

Set LCR (03h) to BFh

Set Xoff1 (06h) to VALUE1

SET Xon1 (04h) to VALUE2

Set LCR (03h) to temp

Read LCR (03h), save in temp

Set LCR (03h) to BFh

Set Xoff2 (07h) to VALUE1

SET Xon2 (05h) to VALUE2

Set LCR (03h) to temp

Set software flow control mode to VALUE

Set flow control threshold to VALUE

Read LCR (03h), save in temp

Set LCR (03h) to BFh

Set EFR (02h) to VALUE

Set LCR (03h) to temp

Read LCR (03h), save in temp1

Set LCR (03h) to BFh

Read EFR (02h), save in temp2

Set EFR (02h) to 10h + temp2

Set LCR (03h) to 00h

Read MCR (04h), save in temp3

Set MCR (04h) to 40h + temp3

Set TCR (06h) to VALUE

Set MCR (04h) to temp3

Set LCR (03h) to BFh

Set EFR (02h) to temp2

Set LCR (03h) to temp1

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Table 23. Register programming guide …continued

Command Actions

Read LCR (03h), save in temp1

Set TX FIFO and RX FIFO thresholds

to VALUE

Set LCR (03h) to BFh

Read EFR (02h), save in temp2

Set EFR (02h) to 10h + temp2

Set LCR (03h) to 00h

Read MCR (04h), save in temp3

Set MCR (04h) to 40h + temp3

Set TLR (07h) to VALUE

Set MCR (04h) to temp3

Set LCR (03h) to BFh

Set EFR (02h) to temp2

Set LCR (03h) to temp1

Read FIFO Rdy register

Read MCR (04h), save in temp1

Set temp2 = temp1 × EFh^[1]

Set MCR (04h) = 40h + temp2

Read FFR (07h), save in temp2

Pass temp2 back to host

Set MCR (04h) to temp1

Set prescaler value to divide-by-1

Read LCR (03h), save in temp1

Set LCR (03h) to BFh

Read EFR (02h), save in temp2

Set EFR (02h) to 10h + temp2

Set LCR (03h) to 00h

Read MCR (04h), save in temp3

Set MCR (04h) to temp3 × 7Fh^[1]

Set LCR (03h) to BFh

Set EFR (02h) to temp2

Set LCR (03h) to temp1

Set prescaler value to divide-by-4

Read LCR (03h), save in temp1

Set LCR (03h) to BFh

Read EFR (02h), save in temp2

Set EFR (02h) to 10h + temp2

Set LCR (03h) to 00h

Read MCR (04h), save in temp3

Set MCR (04h) to temp3 + 80h

Set LCR (03h) to BFh

Set EFR (02h) to temp2

Set LCR (03h) to temp1

[1] × sign here means bit-AND.

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9. Limiting values

Table 24. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC

Parameter

Conditions

Min

Max

7

Unit

V

supply voltage

-

V_n

voltage on any other pin

at D7 to D0 pins

GND − 0.3

−40

V_CC+ 0.3

5.3

V

at any input only pin

operating in free-air

V

T_amb

T_stg

ambient temperature

storage temperature

+85

°C

−65

+150

10. Static characteristics

Table 25. Static characteristics

V_CC= 2.5 V, 3.3 V ± 10 % or 5 V ± 10 %.

Symbol Parameter

Conditions

V_CC= 2.5 V

Typ

V_CC− 10 % V_CCV_CC+ 10 % V_CC− 10 % V_CCV_CC+ 10 % V

V_CC= 3.3 V or 5 V

Unit

Min

Max

Min

Typ

Max

V_CC

V_I

supply voltage

input voltage

0

-

V_CC

0

-

V_CC

V

[1]

V_IH

HIGH-level input

voltage

1.6

2.0

V_IL

LOW-level input

voltage

-

0.65

-

0.8

V

[2]

[3]

[4]

[3]

[4]

[3]

[4]

[3]

[4]

V_O

output voltage

0

-

V_CC

0

-

V_CC

V

V_OH

HIGH-level

output voltage

I_OH= −8 mA

I_OH= −4 mA

I_OH= −800 μA

I_OH= −400 μA

-

2.0

-

V

-

2.0

-

V

1.85

-

V

1.85

-

V

V_OL

LOW-level output I_OL= 8 mA

voltage^[5]

-

0.4

-

V

I_OL= 4 mA

-

V

I_OL= 2 mA

I_OL= 1.6 mA

-

0.4

18

+85

-

V

-

V

C_i

input capacitance

18

+85

pF

°C

T_amb

ambient

temperature

operating

f = 5 MHz

−40

+25

−40

+25

[6]

T_j

junction

temperature

0

25

125

0

25

125

°C

δ

clock duty cycle

supply current

-

50

-

50

-

%

[7]

[8]

I_CC

3.5

50

4.5

50

mA

μA

I_CC(sleep)sleep mode

supply current

-

[1] Meets TTL levels, V_IH(min)= 2 V and V_IL(max)= 0.8 V on non-hysteresis inputs.

[2] Applies for external output buffers.

[3] These parameters apply for D7 to D0.

[4] These parameters apply for DTRA, DTRB, INTA, INTB, RTSA, RTSB, RXRDYA, RXRDYB, TXRDYA, TXRDYB, TXA, TXB.

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[5] Except XTAL2, V_OL= 1 V typical.

[6] These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150 °C. The customer is

responsible for verifying junction temperature.

[7] Measurement condition, normal operation other than Sleep mode:

V_CC= 3.3 V; T_amb= 25 °C. Full duplex serial activity on all two serial (UART) channels at the clock frequency specified in the

recommended operating conditions with divisor of 1.

[8] Sleep mode current might be higher if there is activity on the UART data bus during Sleep mode.

11. Dynamic characteristics

Table 26. Dynamic characteristics

T_amb= −40 °C to +85 °C; V_CC= 2.5 V, 3.3 V ± 10 % or 5 V ± 10 %, unless specified otherwise.

Symbol Parameter

Conditions

V_CC= 2.5 V

V_CC= 3.3 V or 5 V Unit

Min

Max

-

Min

Max

t_d1

IOR delay from chip select

read cycle delay

10

20

-

0

20

-

ns

s

t_d2

25 pF load

-

t_d3

delay from IOR to data

77

26

t_d4

data disable time

-

15

-

15

t_d5

IOW delay from chip select

write cycle delay

10

25

-

10

25

-

t_d6

-

t_d7

delay from IOW to output

25 pF load

100

1T_RCLK

100

33

t_d8

delay to set interrupt from modem input

delay to reset interrupt from IOR

delay from stop to set interrupt

delay from IOR to reset interrupt

delay from start to set interrupt

delay from IOW to transmit start

delay from IOW to reset interrupt

delay from stop to set RXRDYn

delay from IOR to reset RXRDYn

delay from IOW to set TXRDYn

delay from start to reset TXRDYn

-

24

t_d9

-

24

[1]

t_d10

t_d11

t_d12

t_d13

t_d14

t_d15

t_d16

t_d17

t_d18

t_d19

-

1T_RCLK

29

25 pF load

-

ns

s

-

100

[1]

8

-

24T_RCLK

100

8

-

24T_RCLK

70

ns

s

[1]

-

1T_RCLK

100

-

1T_RCLK

75

-

ns

s

-

100

-

70

[1]

-

16T_RCLK

20

-

16T_RCLK

20

delay between successive assertion of

IOW and IOR

-

ns

t_h1

t_h2

t_h3

t_h4

t_h5

chip select hold time from IOR

chip select hold time from IOW

data hold time

0

-

0

-

ns

15

0

15

0

address hold time

hold time from XTAL1 clock HIGH-to-LOW

transition to IOW or IOR release

20

t_p1

clock cycle period

10

-

6

-

ns

t_p2

clock cycle period

ns

[2]

[3]

f_XTAL1

frequency on pin XTAL1

48

-

80

-

MHz

ns

t_w(RESET)pulse width on pin RESET

100

0

40

0

t_su1

address set-up time

-

ns

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Table 26. Dynamic characteristics …continued

T_amb= −40 °C to +85 °C; V_CC= 2.5 V, 3.3 V ± 10 % or 5 V ± 10 %, unless specified otherwise.

Symbol Parameter

Conditions

V_CC= 2.5 V

V_CC= 3.3 V or 5 V Unit

Min

Max

Min

16

Max

t_su2

t_su3

data set-up time

16

20

-

ns

set-up time from IOW or IOR assertion to

XTAL1 clock LOW-to-HIGH transition

20

t_w1

t_w2

IOR strobe width

IOW strobe width

77

30

-

30

-

ns

[1] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.

[2] Applies to external clock; crystal oscillator max 24 MHz.

[3] Reset pulse must happen when CSA, CSB, IOR, IOW are inactive.

11.1 Timing diagrams

valid

address

A0 to A2

t

h4

t

su1

active

CSA, CSB

t

h1

d1

t

w1

t

d2

IOR

active

t

d3

d4

D0 to D7

data

002aaa235

Fig 14. General read timing

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valid

address

A0 to A2

t

h4

su1

active

CSA, CSB

t

h2

d5

t

w2

t

d6

IOW

active

t

h3

su2

D0 to D7

data

002aaa236

Fig 15. General write timing

active

IOW

t

d7

RTSA, RTSB

DTRA, DTRB

change of state

CDA, CDB

CTSA, CTSB

DSRA, DSRB

change of state

t

d8

t

d8

INTA, INTB

active

t

d9

IOR

t

d8

change of state

RIA, RIB

002aaa238

Fig 16. Modem input/output timing

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Start

bit

parity Stop Start

bit

data bits (0 to 7)

RXA, RXB

D0

D1

D2

D3

D4

D5

D6

D7

5 data bits

6 data bits

7 data bits

t

d10

active

INTA, INTB

t

d11

active

IOR

16 baud rate clock

002aaa239

Fig 17. Receive timing

start

bit

parity stop start

bit bit

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RXA, RXB

t

d15

active data

ready

RXRDYA

RXRDYB

t

d16

active

IOR

002aab240

Fig 18. Receive ready timing in non-FIFO mode

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SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

start

bit

parity stop

bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

RXA, RXB

first byte that

reaches the

trigger level

t

d15

active data

ready

RXRDYA

RXRDYB

t

d16

active

IOR

002aaa241

Fig 19. Receive ready timing in FIFO mode

Start

bit

parity Stop Start

bit bit bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

TXA, TXB

5 data bits

6 data bits

7 data bits

t

d12

active

TX ready

INTA, INTB

IOW

t

d14

d13

active

16 baud rate clock

002aaa242

Fig 20. Transmit timing

SC16C752B

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Product data sheet

Rev. 6 — 30 November 2010

38 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

start

bit

parity stop start

bit

data bits (0 to 7)

D3 D4

TXA, TXB

D0

D1

D2

D5

D6

D7

active

IOW

D0 to D7

byte #1

t

d18

t

d17

TXRDYA

TXRDYB

active

transmitter ready

transmitter

not ready

002aaa243

Fig 21. Transmit ready timing in non-FIFO mode

start

bit

parity stop

bit bit

data bits (0 to 7)

D3 D4

D0

D1

D2

D5

D6

D7

TXA, TXB

5 data bits

6 data bits

7 data bits

IOW

active

t

d18

D0 to D7

byte #64

t

d17

TXRDYA

TXRDYB

trigger

lead

002aaa244

Fig 22. Transmit ready timing in FIFO mode

SC16C752B

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Product data sheet

Rev. 6 — 30 November 2010

39 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

12. Package outline

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

c

y

X

36

25

A

E

37

24

Z

E

e

H

E

A

2

A

(A )

3

A

1

w M

p

θ

pin 1 index

b

L

p

L

13

48

detail X

1

12

Z

v M

D

A

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT313-2

136E05

MS-026

Fig 23. Package outline SOT313-2 (LQFP48)

SC16C752B

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Product data sheet

Rev. 6 — 30 November 2010

40 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

SOT617-1

B

A

D

terminal 1

index area

A

1

E

c

detail X

C

e

1

y

e

1/2 e

v

M

b

C

A B

C

1

w

9

16

L

17

8

e

E

h

2

1/2 e

1

24

terminal 1

index area

32

25

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

5.1

4.9

3.25

2.95

5.1

4.9

3.25

2.95

0.5

0.3

mm

0.05 0.1

1

0.2

0.5

3.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-18

SOT617-1

- - -

MO-220

- - -

Fig 24. Package outline SOT617-1 (HVQFN32)

SC16C752B

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Product data sheet

Rev. 6 — 30 November 2010

41 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

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Product data sheet

Rev. 6 — 30 November 2010

42 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

13.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 25) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 27 and 28

Table 27. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 28. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 25.

SC16C752B

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Product data sheet

Rev. 6 — 30 November 2010

43 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 25. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

14. Abbreviations

Table 29. Abbreviations

Acronym

CPU

Description

Central Processing Unit

DMA

Direct Memory Access

FIFO

First In, First Out

TTL

Transistor-Transistor Logic

Universal Asynchronous Receiver/Transmitter

UART

15. Revision history

Table 30. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

SC16C752B v.6 20101130

Modifications:

Product data sheet

-

SC16C752B v.5

• Table 2 “Pin description”: signal names CTSB, DTRB, OPB and RXRDYB are corrected by adding

overbar to indicate they are active LOW signals (CTSB, DTRB, OPB and RXRDYB)

• Table 25 “Static characteristics”: Table note [1] corrected from “V_IO(min)= 2 V and V_IH(max)= 0.8 V”

to “V_IH(min)= 2 V and V_IL(max)= 0.8 V”

SC16C752B v.5 20081002

SC16C752B v.4 20060714

SC16C752B v.3 20041214

SC16C752B v.2 20040527

SC16C752B v.1 20040326

Product data sheet

Product data

-

SC16C752B v.4

SC16C752B v.3

SC16C752B v.2

SC16C752B v.1

-

Product data

SC16C752B

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Product data sheet

Rev. 6 — 30 November 2010

44 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

16.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

16.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

SC16C752B

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Product data sheet

Rev. 6 — 30 November 2010

45 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

SC16C752B

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Product data sheet

Rev. 6 — 30 November 2010

46 of 47

SC16C752B

NXP Semiconductors

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

18. Contents

1

2

3

4

General description. . . . . . . . . . . . . . . . . . . . . . 1

8

Programmer’s guide . . . . . . . . . . . . . . . . . . . . 31

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 33

Static characteristics . . . . . . . . . . . . . . . . . . . 33

Dynamic characteristics. . . . . . . . . . . . . . . . . 34

Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 35

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 40

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

9

10

11

11.1

12

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

13

Soldering of SMD packages. . . . . . . . . . . . . . 42

Introduction to soldering. . . . . . . . . . . . . . . . . 42

Wave and reflow soldering. . . . . . . . . . . . . . . 42

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 42

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 43

6

6.1

6.2

Functional description . . . . . . . . . . . . . . . . . . . 7

Trigger levels . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Hardware flow control. . . . . . . . . . . . . . . . . . . . 7

Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Software flow control . . . . . . . . . . . . . . . . . . . . 9

Receive flow control . . . . . . . . . . . . . . . . . . . . 10

Transmit flow control. . . . . . . . . . . . . . . . . . . . 10

Software flow control example . . . . . . . . . . . . 11

Assumptions. . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Interrupt mode operation . . . . . . . . . . . . . . . . 14

Polled mode operation . . . . . . . . . . . . . . . . . . 14

DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 15

Single DMA transfers

13.1

13.2

13.3

13.4

6.2.1

6.2.2

6.3

6.3.1

6.3.2

6.3.3

6.3.3.1

6.4

14

15

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 44

Revision history . . . . . . . . . . . . . . . . . . . . . . . 44

16

Legal information . . . . . . . . . . . . . . . . . . . . . . 45

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 45

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 46

16.1

16.2

16.3

16.4

6.5

17

18

Contact information . . . . . . . . . . . . . . . . . . . . 46

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.5.1

6.5.2

6.6

6.6.1

(DMA mode 0/FIFO disable). . . . . . . . . . . . . . 15

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Block DMA transfers (DMA mode 1). . . . . . . . 16

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Break and time-out conditions . . . . . . . . . . . . 17

Programmable baud rate generator . . . . . . . . 17

6.6.1.1

6.6.1.2

6.6.2

6.6.2.1

6.6.2.2

6.7

6.8

6.9

7

Register descriptions . . . . . . . . . . . . . . . . . . . 19

Receiver Holding Register (RHR). . . . . . . . . . 21

Transmit Holding Register (THR) . . . . . . . . . . 21

FIFO Control Register (FCR) . . . . . . . . . . . . . 22

Line Control Register (LCR) . . . . . . . . . . . . . . 23

Line Status Register (LSR). . . . . . . . . . . . . . . 24

Modem Control Register (MCR). . . . . . . . . . . 25

Modem Status Register (MSR). . . . . . . . . . . . 26

Interrupt Enable Register (IER) . . . . . . . . . . . 27

Interrupt Identification Register (IIR). . . . . . . . 28

Enhanced Feature Register (EFR) . . . . . . . . . 28

Divisor latches (DLL, DLM). . . . . . . . . . . . . . . 29

Transmission Control Register (TCR). . . . . . . 29

Trigger Level Register (TLR) . . . . . . . . . . . . . 30

FIFO ready register . . . . . . . . . . . . . . . . . . . . 30

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.13

7.14

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 30 November 2010

Document identifier: SC16C752B


型号：	SC16C752BIB48,128
厂家：	NXP
描述：	SC16C752B - 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs QFP 48-Pin 通信时钟数据传输先进先出芯片外围集成电路
文件：	总47页 (文件大小：338K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SC16C752BIB48,128 [NXP]

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