SC16C752BIB48-S [NXP]

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SC16C752BIB48-S
型号: SC16C752BIB48-S
厂家: NXP    NXP
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SC16C752B  
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with  
64-byte FIFOs  
Rev. 03 — 14 December 2004  
Product data  
1. Description  
The SC16C752B is a dual universal asynchronous receiver/transmitter (UART) with  
64-byte FIFOs, automatic hardware/software flow control, and data rates up to  
5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a  
transmission control register (TCR) that stores receiver FIFO threshold levels to  
start/stop transmission during hardware and software flow control. With the FIFO  
RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one  
access. On-chip status registers provide the user with error indications, operational  
status, and modem interface control. System interrupts may be tailored to meet user  
requirements. An internal loop-back capability allows on-board diagnostics.  
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and  
receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or  
8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be  
programmed to interrupt at different trigger levels. The UART generates its own  
desired baud rate based upon a programmable divisor and its input clock. It can  
transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect  
break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can  
detect FIFO underflow. The UART also contains a software interface for modem  
control operations, and has software flow control and hardware flow control  
capabilities.  
The SC16C752B is available in plastic LQFP48 and HVQFN32 packages.  
2. Features  
Dual channel  
Pin compatible with SC16C2550 with additional enhancements  
Up to 5 Mbit/s baud rate (at 3.3 V and 5 V; at 2.5 V maximum baud rate is  
3 Mbit/s)  
64-byte transmit FIFO  
64-byte receive FIFO with error flags  
Programmable and selectable transmit and receive FIFO trigger levels for DMA  
and interrupt generation  
Software/hardware flow control  
Programmable Xon/Xoff characters  
Programmable auto-RTS and auto-CTS  
Optional data flow resume by Xon any character  
DMA signalling capability for both received and transmitted data  
Supports 5 V, 3.3 V and 2.5 V operation  
5 V tolerant inputs  
SC16C752B  
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs  
Philips Semiconductors  
Software selectable baud rate generator  
Prescaler provides additional divide-by-4 function  
Industrial temperature range (40 °C to +85 °C)  
Pin and software compatible with SC16C752, TL16C752  
Fast databus access time  
Programmable sleep mode  
Programmable serial interface characteristics  
5, 6, 7, or 8-bit characters  
Even, odd, or no parity bit generation and detection  
1, 1.5, or 2 stop bit generation  
False start bit detection  
Complete status reporting capabilities in both normal and sleep mode  
Line break generation and detection  
Internal test and loop-back capabilities  
Fully prioritized interrupt system controls  
Modem control functions (CTS, RTS, DSR, DTR, RI, and CD).  
3. Ordering information  
Table 1:  
Ordering information  
Type number  
Package  
Name  
Description  
Version  
SC16C752BIB48  
SC16C752BIBS  
LQFP48  
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm  
SOT313-2  
SOT617-1  
HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;  
32 terminals; body 5 × 5 × 0.85 mm  
9397 750 14443  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 — 14 December 2004  
2 of 47  
SC16C752B  
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs  
Philips Semiconductors  
4. Block diagram  
SC16C752B  
TRANSMIT  
FIFO  
TRANSMIT  
SHIFT  
TXA, TXB  
REGISTER  
REGISTER  
D0–D7  
IOR  
IOW  
DATA BUS  
AND  
CONTROL LOGIC  
RESET  
FLOW  
CONTROL  
LOGIC  
RECEIVE  
FIFO  
RECEIVE  
SHIFT  
RXA, RXB  
REGISTER  
REGISTER  
FLOW  
CONTROL  
LOGIC  
A0–A2  
CSA  
CSB  
REGISTER  
SELECT  
LOGIC  
DTRA, DTRB  
RTSA, RTSB  
OPA, OPB  
MODEM  
CONTROL  
LOGIC  
CTSA, CTSB  
RIA, RIB  
INTA, INTB  
TXRDYA, TXRDYB  
RXRDYA, RXRDYB  
CLOCK AND  
BAUD RATE  
GENERATOR  
INTERRUPT  
CONTROL  
LOGIC  
CDA, CDB  
DSRA, DSRB  
002aaa600  
XTAL1  
XTAL2  
Fig 1. Block diagram.  
9397 750 14443  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 — 14 December 2004  
3 of 47  
SC16C752B  
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs  
Philips Semiconductors  
5. Pinning information  
5.1 Pinning  
D5  
D6  
1
2
3
4
5
6
7
8
9
36 RESET  
35 DTRB  
34 DTRA  
33 RTSA  
32 OPA  
31 RXRDYA  
30 INTA  
29 INTB  
28 A0  
D7  
RXB  
RXA  
TXRDYB  
TXA  
SC16C752BIB48  
TXB  
OPB  
CSA 10  
CSB 11  
n.c. 12  
27 A1  
26 A2  
25 n.c.  
002aaa601  
Fig 2. LQFP48 pin configuration.  
terminal 1  
index area  
D6  
D7  
1
2
3
4
5
6
7
8
24 RESET  
23 RTSA  
22 OPA  
21 INTA  
20 INTB  
19 A0  
RXB  
RXA  
TXA  
TXB  
OPB  
CSA  
SC16C752BIBS  
(top view)  
18 A1  
17 A2  
002aaa950  
Fig 3. HVQFN32 pin configuration.  
9397 750 14443  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 — 14 December 2004  
4 of 47  
SC16C752B  
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs  
Philips Semiconductors  
5.2 Pin description  
Table 2:  
Symbol  
Pin description  
Pin  
Type  
Description  
LQFP48 HVQFN32  
A0  
A1  
A2  
28  
27  
26  
19  
18  
17  
-
I
I
I
I
Address 0 select bit. Internal registers address selection.  
Address 1 select bit. Internal registers address selection.  
Address 2 select bit. Internal registers address selection.  
CDA, CDB 40, 16  
Carrier Detect (Active-LOW). These inputs are associated with individual  
UART channels A and B. A logic LOW on these pins indicates that a carrier  
has been detected by the modem for that channel. The state of these inputs  
is reflected in the modem status register (MSR).  
CSA, CSB  
10, 11  
38, 23  
8, 9  
I
I
Chip Select (Active-LOW). These pins enable data transfers between the  
user CPU and the SC16C752B for the channel(s) addressed. Individual  
UART sections (A, B) are addressed by providing a logic LOW on the  
respective CSA and CSB pins.  
CTSA,  
CTSB  
25, 16  
Clear to Send (Active-LOW). These inputs are associated with individual  
UART channels A and B. A logic 0 (LOW) on the CTS pins indicates the  
modem or data set is ready to accept transmit data from the SC16C752B.  
Status can be tested by reading MSR[4]. These pins only affect the transmit  
and receive operations when Auto-CTS function is enabled via the Enhanced  
Feature Register EFR[7] for hardware flow control operation.  
D0-D4,  
D5-D7  
44-48,  
1-3  
27-31, 32, I/O  
1-2  
Data bus (bi-directional). These pins are the 8-bit, 3-state data bus for  
transferring information to or from the controlling CPU. D0 is the least  
significant bit and the first data bit in a transmit or receive serial data stream.  
DSRA,  
DSRB  
39, 20  
-
I
Data Set Ready (Active-LOW). These inputs are associated with individual  
UART channels A and B. A logic 0 (LOW) on these pins indicates the modem  
or data set is powered-on and is ready for data exchange with the UART. The  
state of these inputs is reflected in the modem status register (MSR).  
DTRA,  
DTRB  
34, 35  
-
O
Data Terminal Ready (Active-LOW). These outputs are associated with  
individual UART channels A and B. A logic 0 (LOW) on these pins indicates  
that the SC16C752B is powered-on and ready. These pins can be controlled  
via the modem control register. Writing a logic 1 to MCR[0] will set the DTR  
output to logic 0 (LOW), enabling the modem. The output of these pins will  
be a logic 1 after writing a logic 0 to MCR[0], or after a reset.  
GND  
17  
13  
I
Signal and power ground.  
INTA, INTB 30, 29  
21, 20  
O
Interrupt A and B (Active-HIGH). These pins provide individual channel  
interrupts INTA and INTB. INTA and INTB are enabled when MCR[3] is set to  
a logic 1, interrupt sources are enabled in the interrupt enable register (IER).  
Interrupt conditions include: receiver errors, available receiver buffer data,  
available transmit buffer space, or when a modem status flag is detected.  
INTA, INTB are in the high-impedance state after reset.  
IOR  
19  
15  
14  
12  
I
I
Input/Output Read strobe (Active-LOW). A HIGH-to-LOW transition on  
IOR will load the contents of an internal register defined by address bits  
A0-A2 onto the SC16C752B data bus (D0-D7) for access by external CPU.  
IOW  
Input/Output Write strobe (Active-LOW). A LOW-to-HIGH transition on  
IOW will transfer the contents of the data bus (D0-D7) from the external CPU  
to an internal register that is defined by address bits A0-A2 and CSA and  
CSB.  
n.c.  
12, 24,  
25, 37  
-
-
Not connected.  
9397 750 14443  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 — 14 December 2004  
5 of 47  
SC16C752B  
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs  
Philips Semiconductors  
Table 2:  
Symbol  
Pin description…continued  
Pin  
Type  
Description  
LQFP48 HVQFN32  
OPA, OPB  
32, 9  
22, 7  
O
User defined outputs. This function is associated with individual channels A  
and B. The state of these pins is defined by the user through the software  
settings of MCR[3]. INTA-INTB are set to active mode and OPA-OPB to a  
logic 0 when MCR[3] is set to a logic 1. INTA-INTB are set to the 3-State  
mode and OPA-OPB to a logic 1 when MCR[3] is set to a logic 0. The output  
of these two pins is HIGH after reset.  
RESET  
36  
24  
-
I
I
Reset. This pin will reset the internal registers and all the outputs. The UART  
transmitter output and the receiver input will be disabled during reset time.  
RESET is an active-HIGH input.  
RIA, RIB  
41, 21  
Ring Indicator (Active-LOW). These inputs are associated with individual  
UART channels, A and B. A logic 0 on these pins indicates the modem has  
received a ringing signal from the telephone line. A LOW-to-HIGH transition  
on these input pins generates a modem status interrupt, if enabled. The state  
of these inputs is reflected in the modem status register (MSR).  
RTSA,  
RTSB  
33, 22  
23, 15  
O
Request to Send (Active-LOW). These outputs are associated with  
individual UART channels, A and B. A logic 0 on the RTS pin indicates the  
transmitter has data ready and waiting to send. Writing a logic 1 in the  
modem control register MCR[1] will set this pin to a logic 0, indicating data is  
available. After a reset these pins are set to a logic 1. These pins only affect  
the transmit and receive operations when Auto-RTS function is enabled via  
the Enhanced Feature Register (EFR[6]) for hardware flow control operation.  
RXA, RXB  
5, 4  
4, 3  
I
Receive data input. These inputs are associated with individual serial  
channel data to the SC16C752B. During the local loop-back mode, these RX  
input pins are disabled and TX data is connected to the UART RX input  
internally.  
RXRDYA,  
RXRDYB  
31, 18  
7, 8  
-
O
O
Receive Ready (Active-LOW). RXRDYA or RXRDYB goes LOW when the  
trigger level has been reached or the FIFO has at least one character. It goes  
HIGH when the RX FIFO is empty.  
TXA, TXB  
5, 6  
Transmit data A, B. These outputs are associated with individual serial  
transmit channel data from the SC16C752B. During the local loop-back  
mode, the TX output pin is disabled and TX data is internally connected to  
the UART RX input.  
TXRDYA,  
TXRDYB  
43, 6  
-
O
Transmit Ready (Active-LOW). TXRDYA or TXRDYB go LOW when there  
are at least a trigger level number of spaces available or when the FIFO is  
empty. It goes HIGH when the FIFO is full or not empty.  
VCC  
42  
13  
26  
10  
I
I
Power supply input.  
XTAL1  
Crystal or external clock input. Functions as a crystal input or as an  
external clock input. A crystal can be connected between XTAL1 and XTAL2  
to form an internal oscillator circuit (see Figure 13). Alternatively, an external  
clock can be connected to this pin to provide custom data rates.  
XTAL2  
14  
11  
O
Output of the crystal oscillator or buffered clock. (See also XTAL1.)  
XTAL2 is used as a crystal oscillator output or a buffered clock output.  
9397 750 14443  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 — 14 December 2004  
6 of 47  
SC16C752B  
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs  
Philips Semiconductors  
6. Functional description  
The SC16C752B UART is pin-compatible with the SC16C2550 UART. It provides  
more enhanced features. All additional features are provided through a special  
enhanced feature register.  
The UART will perform serial-to-parallel conversion on data characters received from  
peripheral devices or modems, and parallel-to-parallel conversion on data characters  
transmitted by the processor. The complete status of each channel of the  
SC16C752B UART can be read at any time during functional operation by the  
processor.  
The SC16C752B can be placed in an alternate mode (FIFO mode) relieving the  
processor of excessive software overhead by buffering received/transmitted  
characters. Both the receiver and transmitter FIFOs can store up to 64 bytes  
(including three additional bits of error status per byte for the receiver FIFO) and have  
selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow  
signalling of DMA transfers.  
The SC16C752B has selectable hardware flow control and software flow control.  
Hardware flow control significantly reduces software overhead and increases system  
efficiency by automatically controlling serial data flow using the RTS output and CTS  
input signals. Software flow control automatically controls data flow by using  
programmable Xon/Xoff characters.  
The UART includes a programmable baud rate generator that can divide the timing  
reference clock input by a divisor between 1 and (216 1).  
6.1 Trigger levels  
The SC16C752B provides independent selectable and programmable trigger levels  
for both receiver and transmitter DMA and interrupt generation. After reset, both  
transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the  
default value of one byte. The selectable trigger levels are available via the FCR. The  
programmable trigger levels are available via the TLR.  
6.2 Hardware flow control  
Hardware flow control is comprised of Auto-CTS and Auto-RTS. Auto-CTS and  
Auto-RTS can be enabled/disabled independently by programming EFR[7:6].  
With Auto-CTS, CTS must be active before the UART can transmit data.  
Auto-RTS only activates the RTS output when there is enough room in the FIFO to  
receive data and de-activates the RTS output when the RX FIFO is sufficiently full.  
The halt and resume trigger levels in the TCR determine the levels at which RTS is  
activated/deactivated.  
If both Auto-CTS and Auto-RTS are enabled, when RTS is connected to CTS, data  
transmission does not occur unless the receiver FIFO has empty space. Thus,  
overrun errors are eliminated during hardware flow control. If not enabled, overrun  
errors occur if the transmit data rate exceeds the receive FIFO servicing latency.  
9397 750 14443  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 — 14 December 2004  
7 of 47  
SC16C752B  
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs  
Philips Semiconductors  
UART 1  
UART 2  
SERIAL TO  
PARALLEL  
PARALLEL  
TO SERIAL  
RX  
TX  
RX  
TX  
FIFO  
FIFO  
RTS  
CTS  
FLOW  
FLOW  
CONTROL  
CONTROL  
D7 to D0  
D7 to D0  
PARALLEL  
TO SERIAL  
SERIAL TO  
PARALLEL  
TX  
RX  
TX  
RX  
FIFO  
FIFO  
CTS  
RTS  
FLOW  
FLOW  
CONTROL  
CONTROL  
002aaa228  
Fig 4. Autoflow control (Auto-RTS and Auto-CTS) example.  
6.2.1 Auto-RTS  
Auto-RTS data flow control originates in the receiver block (see Figure 1 “Block  
diagram.on page 3). Figure 5 shows RTS functional timing. The receiver FIFO  
trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO  
level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger  
level is reached, RTS is deasserted. The sending device (e.g., another UART) may  
send an additional byte after the trigger level is reached (assuming the sending UART  
has another byte to send) because it may not recognize the deassertion of RTS until  
it has begun sending the additional byte. RTS is automatically reasserted once the  
receiver FIFO reaches the resume trigger level programmed via TCR[7:4]. This  
reassertion allows the sending device to resume transmission.  
RX  
Start  
byte N  
Stop  
Start  
byte N + 1  
Stop  
Start  
RTS  
1
2
N
N+1  
IOR  
002aaa226  
(1) N = receiver FIFO trigger level.  
(2) The two blocks in dashed lines cover the case where an additional byte is sent, as described in Section 6.2.1.  
Fig 5. RTS functional timing.  
9397 750 14443  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 — 14 December 2004  
8 of 47  
SC16C752B  
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs  
Philips Semiconductors  
6.2.2 Auto-CTS  
The transmitter circuitry checks CTS before sending the next data byte. When CTS is  
active, the transmitter sends the next byte. To stop the transmitter from sending the  
following byte, CTS must be deasserted before the middle of the last stop bit that is  
currently being sent. The auto-CTS function reduces interrupts to the host system.  
When flow control is enabled, CTS level changes do not trigger host interrupts  
because the device automatically controls its own transmitter. Without auto-CTS, the  
transmitter sends any data present in the transmit FIFO and a receiver overrun error  
may result.  
Start  
byte 0 to 7  
Stop  
TX  
Start  
byte 0 to 7  
Stop  
CTS  
002aaa227  
(1) When CTS is LOW, the transmitter keeps sending serial data out.  
(2) When CTS goes HIGH before the middle of the last stop bit of the current byte, the transmitter finishes sending the current  
byte, but is does not send the next byte.  
(3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.  
Fig 6. CTS functional timing.  
6.3 Software flow control  
Software flow control is enabled through the enhanced feature register and the  
modem control register. Different combinations of software flow control can be  
enabled by setting different combinations of EFR[3:0]. Table 3 shows software flow  
control options.  
Table 3:  
Software flow control options (EFR[0:3])  
EFR[3] EFR[2] EFR[1] EFR[0] TX, RX software flow controls  
0
1
0
1
X
X
X
1
0
0
1
1
X
X
X
0
X
X
X
X
0
1
0
1
X
X
X
X
0
0
1
1
no transmit flow control  
transmit Xon1, Xoff1  
transmit Xon2, Xoff2  
transmit Xon1, Xon2, Xoff1, Xoff2  
no receive flow control  
receiver compared Xon1, Xoff1  
receiver compares Xon2, Xoff2  
transmit Xon1, Xoff1  
receiver compares Xon1 and Xon2, Xoff1 and Xoff2  
transmit Xon2, Xoff2  
0
1
1
1
1
1
1
1
receiver compares Xon1 and Xon2, Xoff1 and Xoff2  
transmit Xon1, Xon2, Xoff1, Xoff2  
receiver compares Xon1 and Xon2, Xoff1 and Xoff2  
9397 750 14443  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 — 14 December 2004  
9 of 47  
SC16C752B  
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs  
Philips Semiconductors  
There are two other enhanced features relating to software flow control:  
Xon Any function (MCR[5]): Operation will resume after receiving any character  
after recognizing the Xoff character. It is possible that an Xon1 character is  
recognized as an Xon Any character, which could cause an Xon2 character to be  
written to the RX FIFO.  
Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the  
special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The  
Xoff interrupt is cleared by a read of the IIR. The special character is transferred to  
the RX FIFO.  
6.3.1 RX  
When software flow control operation is enabled, the SC16C752B will compare  
incoming data with Xoff1,2 programmed characters (in certain cases, Xoff1 and Xoff2  
must be received sequentially). When the correct Xoff character are received,  
transmission is halted after completing transmission of the current character. Xoff  
detection also sets IIR[4] (if enabled via IER[5]) and causes INT to go HIGH.  
To resume transmission, an Xon1,2 character must be received (in certain cases  
Xon1 and Xon2 must be received sequentially). When the correct Xon characters are  
received, IIR[4] is cleared, and the Xoff interrupt disappears.  
6.3.2 TX  
Xoff1/2 character is transmitted when the RX FIFO has passed the HALT trigger level  
programmed in TCR[3:0].  
Xon1/2 character is transmitted when the RX FIFO reaches the RESUME trigger  
level programmed in TCR[7:4].  
The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of  
an ordinary byte from the FIFO. This means that even if the word length is set to be 5,  
6, or 7 characters, then the 5, 6, or 7 least significant bits of Xoff1,2/Xon1,2 will be  
transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom  
done, but this functionality is included to maintain compatibility with earlier designs.)  
It is assumed that software flow control and hardware flow control will never be  
enabled simultaneously. Figure 7 shows an example of software flow control.  
9397 750 14443  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 — 14 December 2004  
10 of 47  
SC16C752B  
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs  
Philips Semiconductors  
6.3.3 Software flow control example  
UART1  
UART2  
TRANSMIT FIFO  
RECEIVE FIFO  
data  
PARALLEL-TO-SERIAL  
SERIAL-TO-PARALLEL  
Xon-1 WORD  
SERIAL-TO-PARALLEL  
PARALLEL-TO-SERIAL  
Xon-1 WORD  
Xoff–Xon–Xoff  
Xon-2 WORD  
Xon-2 WORD  
Xoff-1 WORD  
Xoff-1 WORD  
compare  
programmed  
Xon-Xoff  
Xoff-2 WORD  
Xoff-2 WORD  
characters  
002aaa229  
Fig 7. Software flow control example.  
Assumptions: UART1 is transmitting a large text file to UART2. Both UARTs are  
using software flow control with single character Xoff (0F) and Xon (0D) tokens. Both  
have Xoff threshold (TCR[3:0] = F) set to 60, and Xon threshold (TCR[7:4] = 8) set to  
32. Both have the interrupt receive threshold (TLR[7:4] = D) set to 52.  
UART 1 begins transmission and sends 52 characters, at which point UART2 will  
generate an interrupt to its processor to service the RCV FIFO, but assume the  
interrupt latency is fairly long. UART1 will continue sending characters until a total of  
60 characters have been sent. At this time, UART2 will transmit a 0F to UART1,  
informing UART1 to halt transmission. UART1 will likely send the 61st character while  
UART2 is sending the Xoff character. Now UART2 is serviced and the processor  
reads enough data out of the RX FIFO that the level drops to 32. UART2 will now  
send a 0D to UART1, informing UART1 to resume transmission.  
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6.4 Reset  
Table 4 summarizes the state of register after reset.  
Table 4:  
Register  
Register reset functions  
Reset control  
RESET  
RESET  
RESET  
RESET  
RESET  
RESET  
RESET  
RESET  
RESET  
RESET  
RESET  
RESET  
Reset state  
Interrupt enable register  
Interrupt identification register  
FIFO control register  
All bits cleared.  
Bit 0 is set. All other bits cleared.  
All bits cleared.  
Line control register  
Reset to 00011101 (1D hex).  
All bits cleared.  
Modem control register  
Line status register  
Bits 5 and 6 set. All other bits cleared.  
Bits 0-3 cleared. Bits 4-7 input signals.  
All bits cleared.  
Modem status register  
Enhanced feature register  
Receiver holding register  
Transmitter holding register  
Transmission control register  
Trigger level register  
Pointer logic cleared.  
Pointer logic cleared.  
All bits cleared.  
All bits cleared.  
[1] Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the top-level reset signal  
RESET, i.e., they hold their initialization values during reset.  
Table 5 summarizes the state of registers after reset.  
Table 5:  
Signal  
TX  
Signal RESET functions  
Reset control  
Reset state  
high  
RESET  
RESET  
RESET  
RESET  
RESET  
RTS  
high  
DTR  
high  
RXRDY  
TXRDY  
high  
low  
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6.5 Interrupts  
The SC16C752B has interrupt generation and prioritization (six prioritized levels of  
interrupts) capability. The interrupt enable register (IER) enables each of the six types  
of interrupts and the INT signal in response to an interrupt generation. The IER can  
also disable the interrupt system by clearing bits 0-3, 5-7. When an interrupt is  
generated, the IIR indicates that an interrupt is pending and provides the type of  
interrupt through IIR[5;0]. Table 6 summarizes the interrupt control functions.  
Table 6:  
IIR[5:0]  
Interrupt control functions  
Priority  
level  
Interrupt type  
Interrupt source  
Interrupt reset method  
000001  
000110  
None  
1
none  
none  
none  
receiver line status  
OE, FE, PE, or BI errors occur in  
characters in the RX FIFO  
FE, PE, BI: all erroneous  
characters are read from the  
RX FIFO.  
OE: read LSR  
read RHR  
001100  
000100  
2
2
RX time-out  
stale data in RX FIFO  
DRDY (data ready)  
(FIFO disable)  
RHR interrupt  
read RHR  
RX FIFO above trigger level  
(FIFO enable)  
000010  
3
THR interrupt  
TFE (THR empty)  
(FIFO disable)  
read IIR or a write to the THR  
TX FIFO passes above trigger level  
(FIFO enable)  
000000  
010000  
4
5
modem status  
Xoff interrupt  
MSR[3:0] = 0  
read MSR  
receive Xoff character(s)/special  
character  
receive Xon character(s)/Read of  
IIR  
100000  
6
CTS, RTS  
RTS pin or CTS pin change state from read IIR  
active (LOW) to inactive (HIGH)  
It is important to note that for the framing error, parity error, and break conditions,  
LSR[7] generates the interrupt. LSR[7] is set when there is an error anywhere in the  
RX FIFO, and is cleared only when there are no more errors remaining in the FIFO.  
LSR[4:2] always represent the error status for the received character at the top of the  
RX FIFO. Reading the RX FIFO updates LSR[4:2] to the appropriate status for the  
new character at the top of the FIFO. If the RX FIFO is empty, then LSR[4:2] are all  
zeros.  
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the  
interrupt is cleared by an Xon flow character detection. If a special character  
detection caused the interrupt, the interrupt is cleared by a read of the LSR.  
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6.5.1 Interrupt mode operation  
In interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of  
the receiver and transmitter by an interrupt signal, INT. Therefore, it is not necessary  
to continuously poll the line status register (LSR) to see if any interrupt needs to be  
serviced. Figure 8 shows interrupt mode operation.  
IIR  
IOW / IOR  
INT  
PROCESSOR  
IER  
1
1
1
1
THR  
RHR  
002aaa230  
Fig 8. Interrupt mode operation.  
6.5.2 Polled mode operation  
In polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be  
checked by polling the line status register (LSR). This mode is an alternative to the  
FIFO interrupt mode of operation where the status of the receiver and transmitter is  
automatically known by means of interrupts sent to the CPU. Figure 9 shows FIFO  
polled mode operation.  
LSR  
IOW / IOR  
PROCESSOR  
IER  
0
0
0
0
THR  
RHR  
002aaa231  
Fig 9. FIFO polled mode operation.  
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6.6 DMA operation  
There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by  
FCR[3].  
In DMA mode 0 or FIFO disable (FCR[0] = 0) DMA occurs in single character  
transfers. In DMA mode 1, multi-character (or block) DMA transfers are managed to  
relieve the processor for longer periods of time.  
6.6.1 Single DMA transfers (DMA mode 0/FIFO disable)  
Figure 10 shows TXRDY and RXRDY in DMA mode 0/FIFO disable.  
TX  
RX  
TXRDY  
RXRDY  
at least one  
at least one  
wrptr  
rdptr  
location filled  
location filled  
TXRDY  
RXRDY  
FIFO EMPTY  
FIFO EMPTY  
wrptr  
rdptr  
002aaa232  
Fig 10. TXRDY and RXRDY in DMA mode 0/FIFO disable.  
Transmitter: When empty, the TXRDY signal becomes active. TXRDY will go inactive  
after one character has been loaded into it.  
Receiver: RXRDY is active when there is at least one character in the FIFO. It  
becomes inactive when the receiver is empty.  
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6.6.2 Block DMA transfers (DMA mode 1)  
Figure 11 shows TXRDY and RXRDY in DMA mode 1.  
TX  
RX  
wrptr  
trigger  
level  
TXRDY  
rdptr  
RXRDY  
at least one  
FIFO full  
location filled  
trigger  
level  
TXRDY  
wrptr  
RXRDY  
FIFO EMPTY  
rdptr  
002aaa234  
Fig 11. TXRDY and RXRDY in DMA mode 1.  
Transmitter: TXRDY is active when there is a trigger level number of spaces  
available. It becomes inactive when the FIFO is full.  
Receiver: RXRDY becomes active when the trigger level has been reached, or when  
a time-out interrupt occurs. It will go inactive when the FIFO is empty or an error in  
the RX FIFO is flagged by LSR[7].  
6.7 Sleep mode  
Sleep mode is an enhanced feature of the SC16C752B UART. It is enabled when  
EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is  
entered when:  
The serial data input line, RX, is idle (see Section 6.8 “Break and time-out  
conditions”).  
The TX FIFO and TX shift register are empty.  
There are no interrupts pending except THR and time-out interrupts.  
Remark: Sleep mode will not be entered if there is data in the RX FIFO.  
In sleep mode, the UART clock and baud rate clock are stopped. Since most registers  
are clocked using these clocks, the power consumption is greatly reduced. The UART  
will wake up when any change is detected on the RX line, when there is any change  
in the state of the modem input pins, or if data is written to the TX FIFO.  
Remark: Writing to the divisor latches, DLL and DLH, to set the baud clock, must not  
be done during sleep mode. Therefore, it is advisable to disable sleep mode using  
IER[4] before writing to DLL or DLH.  
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6.8 Break and time-out conditions  
An RX idle condition is detected when the receiver line, RX, has been HIGH for  
4 character time. The receiver line is sampled midway through each bit.  
When a break condition occurs, the TX line is pulled LOW. A break condition is  
activated by setting LCR[6].  
6.9 Programmable baud rate generator  
The SC16C752B UART contains a programmable baud generator that takes any  
clock input and divides it by a divisor in the range between 1 and (216 1). An  
additional divide-by-4 prescaler is also available and can be selected by MCR[7], as  
shown in Figure 12. The output frequency of the baud rate generator is 16× the baud  
rate. The formula for the divisor is:  
XTAL1 crystal input frequency  
---------------------------------------------------------------------------  
prescaler  
divisor =  
--------------------------------------------------------------------------------  
(desired baud rate × 16)  
Where:  
prescaler = 1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected)  
prescaler = 4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected).  
Remark: The default value of prescaler after reset is divide-by-1.  
Figure 12 shows the internal prescaler and baud rate generator circuitry.  
PRESCALER  
MCR[7] = 0  
LOGIC  
(DIVIDE-BY-1)  
internal  
XTAL1  
INTERNAL  
OSCILLATOR  
LOGIC  
BAUD RATE  
GENERATOR  
LOGIC  
baud rate  
clock for  
transmitter  
and receive  
input clock  
XTAL2  
reference  
clock  
PRESCALER  
LOGIC  
(DIVIDE-BY-4)  
MCR[7] = 1  
002aaa233  
Fig 12. Prescaler and baud rate generator block diagram.  
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are  
the least significant and most significant byte of the baud rate divisor. If DLL and DLH  
are both zero, the UART is effectively disabled, as no baud clock will be generated.  
Remark: The programmable baud rate generator is provided to select both the  
transmit and receive clock rates.  
Table 7 and Table 8 show the baud rate and divisor correlation for crystal with  
frequency 1.8432 MHz and 3.072 MHz, respectively.  
Figure 13 shows the crystal clock circuit reference.  
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Table 7:  
Baud rates using a 1.8432 MHz crystal  
Desired baud rate  
Divisor used to generate  
Percent error difference  
16 × clock  
between desired and actual  
50  
2304  
1536  
1047  
857  
768  
384  
192  
96  
75  
110  
0.026  
0.058  
134.5  
150  
300  
600  
1200  
1800  
2000  
2400  
3600  
4800  
7200  
9600  
19200  
38400  
56000  
64  
58  
0.69  
48  
32  
24  
16  
12  
6
3
2
2.86  
Table 8:  
Baud rates using a 3.072 MHz crystal  
Desired baud rate  
Divisor used to generate  
Percent error difference  
16 × clock  
between desired and actual  
50  
2304  
2560  
1745  
1428  
1280  
640  
320  
160  
107  
96  
75  
110  
0.026  
0.034  
134.5  
150  
300  
600  
1200  
1800  
2000  
2400  
3600  
4800  
7200  
9600  
19200  
38400  
0.312  
80  
53  
0.628  
1.23  
40  
27  
20  
10  
5
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1.5 k  
X1  
X1  
1.8432 MHz  
1.8432 MHz  
C1  
22 pF  
C2  
33 pF  
C1  
22 pF  
C2  
47 pF  
002aaa586  
Fig 13. Crystal oscillator connections.  
7. Register descriptions  
Each register is selected using address lines A0, A1, A2, and in some cases, bits  
from other registers. The programming combinations for register selection are shown  
in Table 9.  
Table 9:  
Register map - read/write properties  
A2 A1 A0 Read mode  
Write mode  
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
1
receive holding register (RHR)  
interrupt enable register (IER)  
interrupt identification register (IIR)  
line control register (LCR)  
modem control register (MCR)[1]  
line status register (LSR)  
modem status register (MSR)  
scratchpad register (SPR)  
divisor latch LSB (DLL)[2], [3]  
divisor latch MSB (DLH)[2], [3]  
enhanced feature register (EFR)[2], [4]  
Xon1 word[2], [4]  
transmit holding register (THR)  
interrupt enable register  
FIFO control register (FCR)  
line control register  
modem control register[1]  
scratchpad register  
divisor latch LSB[2], [3]  
divisor latch MSB[2], [3]  
enhanced feature register[2], [4]  
Xon1 word[2], [4]  
Xon2 word[2], [4]  
Xoff1 word[2], [4]  
Xoff2 word[2], [4]  
Xon2 word[2], [4]  
Xoff1 word[2], [4]  
Xoff2 word[2], [4]  
transmission control register (TCR)[2], [5] transmission control register[2], [5]  
trigger level register (TLR)[2], [5]  
FIFO ready register[2], [6]  
trigger level register[2], [5]  
[1] MCR[7] can only be modified when EFR[4] is set.  
[2] Accessed by a combination of address pins and register bits.  
[3] Accessible only when LCR[7] is logic 1.  
[4] Accessible only when LCR is set to 10111111 (xBF).  
[5] Accessible only when EFR[4] = 1 and MCR[6] = 1, i.e., EFR[4] and MCR[6] are read/write enables.  
[6] Accessible only when CSA or CSB = 0, MCR[2] = 1, and loop-back is disabled (MCR[4] = 0).  
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Table 10 lists and describes the SC16C752B internal registers.  
Table 10: SC16C752B internal registers  
Shaded bits are only accessible when EFR[4] is set.  
Read/  
Write  
A2 A1 A0 Register Bit 7  
General Register Set[1]  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0
0
0
0
0
0
0
0
1
RHR  
THR  
IER  
bit 7  
bit 6  
bit 5  
bit 5  
bit 4  
bit 4  
bit 3  
bit 3  
bit 2  
bit 2  
bit 1  
bit 1  
THR  
bit 0  
bit 0  
R
bit 7  
bit 6  
W
0/CTS  
interrupt interrupt  
enable[2] enable[2]  
0/RTS  
0/Xoff[2] 0/X sleep modem receive  
Rx data  
available  
interrupt  
R/W  
mode[2]  
status  
interrupt interrupt  
linestatus empty  
interrupt  
TX FIFO RX FIFO  
0
1
0
FCR  
RX  
trigger  
level  
RX trigger 0/TX  
level (LSB) trigger  
level  
0/TX  
trigger  
level  
DMA  
mode  
select  
FIFO  
enable  
W
reset  
reset  
(MSB)  
(MSB)[2] (LSB)[2]  
0
0
1
1
1
1
0
0
0
1
0
1
IIR  
FCR[0]  
FCR[0]  
0/CTS,  
RTS  
0/Xoff  
interrupt interrupt  
priority priority  
interrupt  
priority  
bit 0  
interrupt  
status  
R
bit 2  
bit 1  
LCR  
MCR  
LSR  
DLAB  
break  
control bit  
set parity parity  
type  
parity  
number of word  
word  
length  
bit 0  
R/W  
R/W  
R
enable stop bits length  
bit 1  
select  
1× or  
1×/4  
clock  
TCR and  
TLR  
enable  
0/Xon  
Any  
0/enable IRQ  
loop-back enable ready  
FIFO  
RTS  
DTR  
OP  
enable  
0/error in THR and  
RX FIFO TSR  
empty  
THR  
empty  
break  
interrupt error  
framing parity  
overrun  
error  
data in  
receiver  
error  
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
MSR  
SPR  
TCR  
TLR  
CD  
bit 7  
bit 7  
bit 7  
0
RI  
DSR  
bit 5  
bit 5  
bit 5  
CTS  
bit 4  
bit 4  
bit 4  
CD  
bit 3  
bit 3  
bit 3  
0
RI  
bit 2  
bit 2  
bit 2  
0
DSR  
bit 1  
CTS  
bit 0  
bit 0  
bit 0  
R
bit 6  
bit 6  
bit 6  
0
R/W  
R/W  
R/W  
R
bit 1  
bit 1  
FIFO  
Rdy  
RX FIFO RX FIFO  
B status A status  
TX FIFO B TX FIFO  
status  
A status  
Special Register Set[3]  
0
0
0
DLL  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 9  
bit 0  
bit 8  
R/W  
R/W  
0
0
1
DLH  
bit 15  
bit 14  
bit 13  
bit 12  
bit 11  
bit 10  
Enhanced Register Set[4]  
0
1
0
EFR  
Auto  
CTS  
Auto RTS Special  
Enable  
software software software  
software  
flow  
R/W  
character enhanced flow  
flow  
flow  
detect  
functions control control  
control  
bit 1  
control  
bit 0  
[2]  
bit 3  
bit 3  
bit 3  
bit 3  
bit 3  
bit 2  
bit 2  
bit 2  
bit 2  
bit 2  
1
1
1
1
0
0
1
1
0
1
0
1
Xon1  
Xon2  
Xoff1  
Xoff2  
bit 7  
bit 7  
bit 7  
bit 7  
bit 6  
bit 6  
bit 6  
bit 6  
bit 5  
bit 5  
bit 5  
bit 5  
bit 4  
bit 4  
bit 4  
bit 4  
bit 1  
bit 1  
bit 1  
bit 1  
bit 0  
bit 0  
bit 0  
bit 0  
R/W  
R/W  
R/W  
R/W  
[1] These registers are accessible only when LCR[7] = 0.  
[2] The shaded bits in the above table can only be modified if register bit EFR[4] is enabled, i.e., if enhanced functions are enabled.  
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[3] The Special Register set is accessible only when LCR[7] is set to a logic 1.  
[4] Enhanced Feature Register; Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BFHex’.  
Remark: Refer to the notes under Table 9 for more register access information.  
7.1 Receiver holding register (RHR)  
The receiver section consists of the receiver holding register (RHR) and the receiver  
shift register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial  
data from the RX terminal. The data is converted to parallel data and moved to the  
RHR. The receiver section is controlled by the line control register. If the FIFO is  
disabled, location zero of the FIFO is used to store the characters.  
Remark: In this case, characters are overwritten if overflow occurs.  
If overflow occurs, characters are lost. The RHR also stores the error status bits  
associated with each character.  
7.2 Transmit holding register (THR)  
The transmitter section consists of the transmit holding register (THR) and the  
transmit shift register (TSR). The THR is actually a 64-byte FIFO. The THR receives  
data and shifts it into the TSR, where it is converted to serial data and moved out on  
the TX terminal. If the FIFO is disabled, the FIFO is still used to store the byte.  
Characters are lost if overflow occurs.  
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7.3 FIFO control register (FCR)  
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs,  
setting transmitter and receiver trigger levels, and selecting the type of DMA  
signalling. Table 11 shows FIFO control register bit settings.  
Table 11: FIFO Control Register bits description  
Bit  
Symbol  
Description  
7:6  
FCR[7]  
(MSB),  
FCR[6]  
(LSB)  
RCVR trigger. Sets the trigger level for the RX FIFO.  
00 - 8 characters  
01 - 16 characters  
10 - 56 characters  
11 - 60 characters  
5:4  
FCR[5]  
(MSB),  
FCR[4]  
(LSB)  
TX trigger. Sets the trigger level for the TX FIFO.  
00 - 8 spaces  
01 - 16 spaces  
10 - 32 spaces  
11 - 56 spaces  
FCR[5:4] can only be modified and enabled when EFR[4] is set. This is  
because the transmit trigger level is regarded as an enhanced function.  
3
2
FCR[3]  
FCR[2]  
DMA mode select.  
Logic 0 = Set DMA mode ‘0’  
Logic 1 = Set DMA mode ‘1’  
Reset TX FIFO.  
Logic 0 = No FIFO transmit reset (normal default condition).  
Logic 1 = Clears the contents of the transmit FIFO and resets the  
FIFO counter logic (the transmit shift register is not cleared or  
altered). This bit will return to a logic 0 after clearing the FIFO.  
1
0
FCR[1]  
FCR[0]  
Reset RX FIFO.  
Logic 0 = No FIFO receive reset (normal default condition).  
Logic 1 = Clears the contents of the receive FIFO and resets the FIFO  
counter logic (the receive shift register is not cleared or altered). This  
bit will return to a logic 0 after clearing the FIFO.  
FIFO enable.  
Logic 0 = Disable the transmit and receive FIFO (normal default  
condition).  
Logic 1 = Enable the transmit and receive FIFO.  
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7.4 Line control register (LCR)  
This register controls the data communication format. The word length, number of  
stop bits, and parity type are selected by writing the appropriate bits to the LCR.  
Table 12 shows the line control register bit settings.  
Table 12: Line Control Register bits description  
Bit  
Symbol  
Description  
7
LCR[7]  
Divisor latch enable.  
Logic 0 = Divisor latch disabled (normal default condition).  
Logic 1 = Divisor latch enabled.  
6
5
LCR[6]  
LCR[5]  
Break control bit. When enabled, the Break control bit causes a break  
condition to be transmitted (the TX output is forced to a logic 0 state).  
This condition exists until disabled by setting LCR[6] to a logic 0.  
Logic 0 = no TX break condition (normal default condition).  
Logic 1 = forces the transmitter output (TX) to a logic 0 to alert the  
communication terminal to a line break condition.  
Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1).  
Logic 0 = parity is not forced (normal default condition).  
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1  
for the transmit and receive data.  
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0  
for the transmit and receive data.  
4
3
LCR[4]  
LCR[3]  
Parity type select.  
Logic 0 = ODD Parity is generated (if LCR[3] = 1).  
Logic 1 = EVEN Parity is generated (if LCR[3] = 1).  
Parity enable.  
Logic 0 = no parity (normal default condition).  
Logic 1 = a parity bit is generated during transmission and the  
receiver checks for received parity.  
2
LCR[2]  
Number of Stop bits. Specifies the number of stop bits.  
0 - 1 stop bit (word length = 5, 6, 7, 8)  
1 - 1.5 stop bits (word length = 5)  
1 = 2 stop bits (word length = 6, 7, 8)  
1:0  
LCR[1:0]  
Word length bits 1, 0. These two bits specify the word length to be  
transmitted or received.  
00 - 5 bits  
01 - 6 bits  
10 - 7 bits  
11 - 8 bits  
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7.5 Line status register (LSR)  
Table 13 shows the line status register bit settings.  
Table 13: Line Status Register bits description  
Bit  
Symbol  
Description  
7
LSR[7]  
FIFO data error.  
Logic 0 = No error (normal default condition).  
Logic 1 = At least one parity error, framing error, or break indication is  
in the receiver FIFO. This bit is cleared when no more errors are  
present in the FIFO.  
6
5
LSR[6]  
LSR[5]  
THR and TSR empty. This bit is the Transmit Empty indicator.  
Logic 0 = Transmitter hold and shift registers are not empty.  
Logic 1 = Transmitter hold and shift registers are empty.  
THR empty. This bit is the Transmit Holding Register Empty indicator.  
Logic 0 = Transmit hold register is not empty.  
Logic 1 = Transmit hold register is empty. The processor can now load  
up to 64 bytes of data into the THR if the TX FIFO is enabled.  
4
3
LSR[4]  
LSR[3]  
Break interrupt.  
Logic 0 = No break condition (normal default condition).  
Logic 1 = A break condition occurred and associated byte is 00, i.e.,  
RX was LOW for one character time frame.  
Framing error.  
Logic 0 = No framing error in data being read from RX FIFO (normal  
default condition).  
Logic 1 = Framing error occurred in data being read from RX FIFO, i.e.,  
received data did not have a valid stop bit.  
2
1
0
LSR[2]  
LSR[1]  
LSR[0]  
Parity error.  
Logic 0 = No parity error (normal default condition).  
Logic 1 = Parity error in data being read from RX FIFO.  
Overrun error.  
Logic 0 = No overrun error (normal default condition).  
Logic 1 = Overrun error has occurred.  
Data in receiver.  
Logic 0 = No data in receive FIFO (normal default condition).  
Logic 1 = At least one character in the RX FIFO.  
When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at  
the top of the RX FIFO (next character to be read). The LSR[4:2] registers do not  
physically exist, as the data read from the RX FIFO is output directly onto the output  
data bus, DI[4:2], when the LSR is read. Therefore, errors in a character are identified  
by reading the LSR and then reading the RHR.  
LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only  
when there are no more errors remaining in the FIFO.  
Reading the LSR does not cause an increment of the RX FIFO read pointer. The  
RX FIFO read pointer is incremented by reading the RHR.  
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Remark: The three error bits (parity, framing, break) may not be updated correctly in  
the first read of the LSR when the input clock (XTAL1) is running faster than 36 MHz.  
However, the second read is always correct. It is strongly recommended that when  
using this device with a clock faster than 36 MHz, that the LSR be read twice and only  
the second read be used for decision making. All other bits in the LSR are correct on  
all reads.  
7.6 Modem control register (MCR)  
The MCR controls the interface with the mode, data set, or peripheral device that is  
emulating the modem. Table 14 shows modem control register bit settings.  
Table 14: Modem Control Register bits description  
Bit  
Symbol  
MCR[7] [1] Clock select.  
Logic 0 = Divide-by-1 clock input.  
Logic 1 = Divide-by-4 clock input.  
MCR[6] [1] TCR and TLR enable.  
Description  
7
6
5
4
Logic 0 = no action.  
Logic 1 = Enable access to the TCR and TLR registers.  
MCR[5] [1] Xon Any.  
Logic 0 = Disable Xon Any function.  
Logic 1 = Enable Xon Any function.  
Enable loop-back.  
MCR[4]  
MCR[3]  
Logic 0 = Normal operating mode.  
Logic 1 = Enable local loop-back mode (internal). In this mode the  
MCR[3:0] signals are looped back into MSR[7:4] and the TX output  
is looped back to the RX input internally.  
3
IRQ enable OP.  
Logic 0 = Forces INTA-INTB outputs to the 3-State mode and OP  
output to HIGH state.  
Logic 1 = Forces the INTA-INTB outputs to the active state and OP  
output to LOW state. In loop-back mode, controls MSR[7].  
2
1
MCR[2]  
MCR[1]  
FIFO Ready enable.  
Logic 0 = Disable the FIFO Rdy register.  
Logic 1 = Enable the FIFO Rdy register.  
In loop-back mode, controls MSR[6].  
RTS  
Logic 0 = Force RTS output to inactive (HIGH).  
Logic 1 = Force RTS output to active (LOW).  
In loop-back mode, controls MSR[4]. If Auto-RTS is enabled, the  
RTS output is controlled by hardware flow control.  
0
MCR[0]  
DTR  
Logic 0 = Force DTR output to inactive (HIGH).  
Logic 1 = Force DTR output to active (LOW).  
In loop-back mode, controls MSR[5].  
[1] MCR[7:5] can only be modified when EFR[4] is set, i.e., EFR[4] is a write enable.  
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7.7 Modem status register (MSR)  
This 8-bit register provides information about the current state of the control lines  
from the mode, data set, or peripheral device to the processor. It also indicates when  
a control input from the modem changes state. Table 15 shows modem status  
register bit settings per channel.  
Table 15: Modem Status Register bits description  
Bit  
Symbol  
Description  
7
MSR[7]  
CD (Active-HIGH, logical 1). This bit is the complement of the CD input  
during normal mode. During internal loop-back mode, it is equivalent to  
MCR[3].  
6
5
4
MSR[6]  
MSR[5]  
MSR[4]  
RI (Active-HIGH, logical 1). This bit is the complement of the RI input  
during normal mode. During internal loop-back mode, it is equivalent to  
MCR[2].  
DSR (Active-HIGH, logical 1). This bit is the complement of the DSR  
input during normal mode. During internal loop-back mode, it is  
equivalent MCR[0].  
CTS (Active-HIGH, logical 1). This bit is the complement of the CTS  
input during normal mode. During internal loop-back mode, it is  
equivalent to MCR[1].  
3
2
1
0
MSR[3]  
MSR[2]  
MSR[1]  
MSR[0]  
CD. Indicates that CD input (or MCR[3] in loop-back mode) has  
changed state. Cleared on a read.  
RI. Indicates that RI input (or MCR[2] in loop-back mode) has changed  
state from LOW to HIGH. Cleared on a read.  
DSR. Indicates that DSR input (or MCR[0] in loop-back mode) has  
changed state. Cleared on a read.  
CTS. Indicates that CTS input (or MCR[1] in loop-back mode) has  
changed state. Cleared on a read.  
[1] The primary inputs RI, CD, CTS, DSR are all Active-LOW, but their registered equivalents in the MSR  
and MCR (in loop-back) registers are Active-HIGH.  
7.8 Interrupt enable register (IER)  
The interrupt enable register (IER) enables each of the six types of interrupt, receiver  
error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from  
LOW to HIGH. The INT output signal is activated in response to interrupt generation.  
Table 16 shows interrupt enable register bit settings.  
Table 16: Interrupt Enable Register bits description  
Bit  
Symbol  
IER[7] [1] CTS interrupt enable.  
Logic 0 = Disable the CTS interrupt (normal default condition).  
Logic 1 = Enable the CTS interrupt.  
IER[6] [1] RTS interrupt enable.  
Description  
7
6
5
Logic 0 = Disable the RTS interrupt (normal default condition).  
Logic 1 = Enable the RTS interrupt.  
IER[5] [1] Xoff interrupt.  
Logic 0 = Disable the Xoff interrupt (normal default condition).  
Logic 1 = Enable the Xoff interrupt.  
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Table 16: Interrupt Enable Register bits description…continued  
Bit  
Symbol  
IER[4] [1] Sleep mode.  
Logic 0 = Disable sleep mode (normal default condition).  
Description  
4
Logic 1 = Enable sleep mode. See Section 6.7 “Sleep mode” for details.  
Modem Status Interrupt.  
3
2
IER[3]  
Logic 0 = Disable the modem status register interrupt (normal default  
condition).  
Logic 1 = Enable the modem status register interrupt.  
Receive Line Status interrupt.  
IER[2]  
Logic 0 = Disable the receiver line status interrupt (normal default  
condition).  
Logic 1 = Enable the receiver line status interrupt.  
Transmit Holding Register interrupt.  
1
0
IER[1]  
IER[0]  
Logic 0 = Disable the THR interrupt (normal default condition).  
Logic 1 = Enable the THR interrupt.  
Receive Holding Register interrupt.  
Logic 0 = Disable the RHR interrupt (normal default condition).  
Logic 1 = Enable the RHR interrupt.  
[1] IER[7:4] can only be modified if EFR[4] is set, i.e., EFR[4] is a write enable. Re-enabling IER[1] will  
not cause a new interrupt if the THR is below the threshold.  
7.9 Interrupt identification register (IIR)  
The IIR is a read-only 8-bit register which provides the source of the interrupt in a  
prioritized manner. Table 17 shows interrupt identification register bit settings.  
Table 17: Interrupt Identification Register bits description  
Bit  
7:6  
5
Symbol  
IIR[7:6]  
IIR[5]  
Description  
Mirror the contents of FCR[0].  
RTS/CTS LOW-to-HIGH change of state.  
1 = Xoff/Special character has been detected.  
3-bit encoded interrupt. See Table 18.  
Interrupt status.  
4
IIR[4]  
3:1  
0
IIR[3:1]  
IIR[0]  
Logic 0 = An interrupt is pending.  
Logic 1 = No interrupt is pending.  
The interrupt priority list is shown in Table 18.  
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Table 18: Interrupt priority list  
Priority IIR[5]  
level  
IIR[4]  
IIR[3]  
IIR[2]  
IIR[1]  
IIR[0]  
Source of the interrupt  
1
2
2
3
4
5
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
Receiver Line Status error  
Receiver time-out interrupt  
RHR interrupt  
THR interrupt  
Modem interrupt  
Received Xoff signal/  
special character  
6
1
0
0
0
0
0
CTS, RTS change of state  
from active (LOW) to  
inactive (HIGH)  
7.10 Enhanced feature register (EFR)  
This 8-bit register enables or disables the enhanced features of the UART. Table 19  
shows the enhanced feature register bit settings.  
Table 19: Enhanced Feature Register bits description  
Bit  
Symbol  
Description  
7
EFR[7]  
CTS flow control enable.  
Logic 0 = CTS flow control is disabled (normal default condition).  
Logic 1 = CTS flow control is enabled. Transmission will stop when a  
HIGH signal is detected on the CTS pin.  
6
5
EFR[6]  
EFR[5]  
EFR[4]  
RTS flow control enable.  
Logic 0 = RTS flow control is disabled (normal default condition).  
Logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when  
the receiver FIFO HALT trigger level TCR[3:0] is reached, and goes  
LOW when the receiver FIFO RESUME transmission trigger level  
TCR[7:4] is reached.  
Special character detect.  
Logic 0 = Special character detect disabled (normal default condition).  
Logic 1 = Special character detect enabled. Received data is  
compared with Xoff-2 data. If a match occurs, the received data is  
transferred to FIFO and IIR[4] is set to a logical 1 to indicate a special  
character has been detected.  
4
Enhanced functions enable bit.  
Logic 0 = Disables enhanced functions and writing to IER[7:4],  
FCR[5:4], MCR[7:5].  
Logic 1 = Enables the enhanced function IER[7:4], FCR[5:4], and  
MCR[7:5] can be modified, i.e., this bit is therefore a write enable.  
3:0  
EFR[3:0] Combinations of software flow control can be selected by programming  
these bits. See Table 3 “Software flow control options (EFR[0:3])” on  
page 9.  
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7.11 Divisor latches (DLL, DLH)  
These are two 8-bit registers which store the 16-bit divisor for generation of the baud  
clock in the baud rate generator. DLH stores the most significant part of the divisor.  
DLL stores the least significant part of the divisor.  
Note that DLL and DLH can only be written to before sleep mode is enabled, i.e.,  
before IER[4] is set.  
7.12 Transmission control register (TCR)  
This 8-bit register is used to store the RX FIFO threshold levels to stop/start  
transmission during hardware/software flow control. Table 20 shows transmission  
control register bit settings.  
Table 20: Transmission Control Register bits description  
Bit  
7:4  
3:0  
Symbol  
Description  
TCR[7:4] RX FIFO trigger level to resume transmission (0-60).  
TCR[3:0] RX FIFO trigger level to halt transmission (0-60).  
TCR trigger levels are available from 0-60 bytes with a granularity of four.  
Remark: TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The  
programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is no  
built-in hardware check to make sure this condition is met. Also, the TCR must be  
programmed with this condition before Auto-RTS or software flow control is enabled  
to avoid spurious operation of the device.  
7.13 Trigger level register (TLR)  
This 8-bit register is pulsed to store the transmit and received FIFO trigger levels  
used for DMA and interrupt generation. Trigger levels from 4-60 can be programmed  
with a granularity of 4. Table 21 shows trigger level register bit settings.  
Table 21: Trigger Level Register bits description  
Bit  
7:4  
3:0  
Symbol  
Description  
TLR[7:4] RX FIFO trigger levels (4-60), number of characters available.  
TLR[3:0] TX FIFO trigger levels (4-60), number of spaces available.  
Remark: TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or  
TLR[7:4] are logical 0, the selectable trigger levels via the FIFO control register (FCR)  
are used for the transmit and receive FIFO trigger levels. Trigger levels from 4-60  
bytes are available with a granularity of four. The TLR should be programmed for N4,  
where N is the desired trigger level.  
When the trigger level setting in TLR is zero, the SC16C752B uses the trigger level  
setting defined in FCR. If TLR has non-zero trigger level value, the trigger level  
defined in FCR is discarded. This applies to both transmit FIFO and receive FIFO  
trigger level setting.  
When TLR is used for RX trigger level control, FCR[7:6] should be left at the default  
state, i.e., ‘00’.  
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7.14 FIFO ready register  
The FIFO ready register provides real-time status of the transmit and receive FIFOs  
of both channels.  
Table 22: FIFO Ready Register bits description  
Bit  
7:6  
5
Symbol  
Description  
FIFO Rdy[7:6]  
FIFO Rdy[5]  
FIFO Rdy[4]  
FIFO Rdy[3:2]  
FIFO Rdy[1]  
FIFO Rdy[0]  
Unused; always 0.  
RX FIFO B status. Related to DMA.  
RX FIFO A status. Related to DMA.  
Unused; always 0.  
4
3:2  
1
TX FIFO B status. Related to DMA.  
TX FIFO A status. Related to DMA.  
0
The FIFO Rdy register is a read-only register that can be accessed when any of the  
two UARTs is selected CSA or CSB = 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and  
loop-back is disabled. The address is 111.  
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8. Programmer’s guide  
The base set of registers that is used during high-speed data transfer have a  
straightforward access method. The extended function registers require special  
access bits to be decoded along with the address lines. The following guide will help  
with programming these registers. Note that the descriptions below are for individual  
register access. Some streamlining through interleaving can be obtained when  
programming all the registers.  
Table 23: Register programming guide  
Command  
Actions  
Read LCR (03), save in temp  
Set baud rate to VALUE1, VALUE2  
Set LCR (03) to 80  
Set DLL (00) to VALUE1  
SET DLM (01) to VALUE2  
Set LCR (03) to temp  
Set Xoff-1, Xon-1 to VALUE1, VALUE2  
Set Xoff-2, Xon-2 to VALUE1, VALUE2  
Read LCR (03), save in temp  
Set LCR (03) to BF  
Set Xoff-1 (06) to VALUE1  
SET Xon-1 (04) to VALUE2  
Set LCR (03) to temp  
Read LCR (03), save in temp  
Set LCR (03) to BF  
Set Xoff-2 (07) to VALUE1  
SET Xon-2 (05) to VALUE2  
Set LCR (03) to temp  
Set software flow control mode to  
VALUE  
Read LCR (03), save in temp  
Set LCR (03) to BF  
Set EFR (02) to VALUE  
Set LCR (03) to temp  
Set flow control threshold to VALUE  
Read LCR (03), save in temp1  
Set LCR (03) to BF  
Read EFR (02), save in temp2  
Set EFR (02) to 10 + temp2  
Set LCR (03) to 00  
Read MCR (04), save in temp3  
Set MCR (04) to 40 + temp3  
Set TCR (06) to VALUE  
Set MCR (04) to temp3  
Set LCR (03) to BF  
Set EFR (02) to temp2  
Set LCR (03) to temp1  
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Table 23: Register programming guide…continued  
Command Actions  
Read LCR (03), save in temp1  
Set TX FIFO and RX FIFO thresholds  
to VALUE  
Set LCR (03) to BF  
Read EFR (02), save in temp2  
Set EFR (02) to 10 + temp2  
Set LCR (03) to 00  
Read MCR (04), save in temp3  
Set MCR (04) to 40 + temp3  
Set TLR (07) to VALUE  
Set MCR (04) to temp3  
Set LCR (03) to BF  
Set EFR (02) to temp2  
Set LCR (03) to temp1  
Read FIFO Rdy register  
Read MCR (04), save in temp1  
Set temp2 = temp1 × EF [1]  
Set MCR (04) = 40 + temp2  
Read FFR (07), save in temp2  
Pass temp2 back to host  
Set MCR (04) to temp1  
Read LCR (03), save in temp1  
Set LCR (03) to BF  
Set prescaler value to divide-by-1  
Read EFR (02), save in temp2  
Set EFR (02) to 10 + temp2  
Set LCR (03) to 00  
Read MCR (04), save in temp3  
Set MCR (04) to temp3 × 7F [1]  
Set LCR (03) to BF  
Set EFR (02) to temp2  
Set LCR (03) to temp1  
Set prescaler value to divide-by-4  
Read LCR (03), save in temp1  
Set LCR (03) to BF  
Read EFR (02), save in temp2  
Set EFR (02) to 10 + temp2  
Set LCR (03) to 00  
Read MCR (04), save in temp3  
Set MCR (04) to temp3 + 80  
Set LCR (03) to BF  
Set EFR (02) to temp2  
Set LCR (03) to temp1  
[1] × sign here means bit-AND.  
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9. Limiting values  
Table 24: Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VCC  
VI  
Parameter  
Conditions  
Min  
-
Max  
Unit  
V
supply voltage  
7
input voltage  
0.3  
0.3  
40  
65  
VCC + 0.3  
VCC + 0.3  
+85  
V
VO  
output voltage  
V
Tamb  
Tstg  
operating ambient temperature  
storage temperature  
in free-air  
°C  
°C  
+150  
[1] Stresses beyond those listed under Limiting values may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is  
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
10. Static characteristics  
Table 25: DC electrical characteristics  
VCC = 2.5 V, 3.3 V ±10% or 5 V ±10%.  
Symbol Parameter  
Conditions  
2.5 V  
3.3 V and 5 V  
Nom Max  
Unit  
Min  
Nom Max  
Min  
VCC  
VI  
supply voltage  
input voltage  
V
CC 10% VCC  
VCC + 10% VCC 10% VCC  
VCC + 10% V  
0
-
-
VCC  
VCC  
0
-
-
VCC  
VCC  
V
V
[1]  
[1]  
VIH  
HIGH-level input  
voltage  
1.6  
2.0  
VIL  
LOW-level input  
voltage  
-
-
0.65  
-
-
0.8  
V
[2]  
[4]  
[5]  
[4]  
[5]  
[4]  
[5]  
[4]  
[5]  
VO  
output voltage  
0
-
VCC  
0
-
VCC  
V
VOH  
HIGH-level output IOH = 8 mA  
voltage  
-
-
-
2.0  
-
-
V
IOH = 4 mA  
-
-
-
2.0  
-
-
V
IOH = 800 µA  
IOH = 400 µA  
1.85  
-
-
-
-
-
V
1.85  
-
-
-
-
-
V
VOL  
LOW-level output IOL = 8 mA  
voltage[7]  
-
-
-
-
-
0.4  
0.4  
-
V
IOL = 4 mA  
-
-
-
-
-
V
IOL = 2 mA  
IOL = 1.6 mA  
-
-
0.4  
0.4  
18  
85  
-
-
V
-
-
-
-
-
V
Ci  
input capacitance  
-
-
-
-
18  
85  
pF  
°C  
Tamb  
operating ambient  
temperature  
40  
25  
40  
25  
[3]  
[8]  
Tj  
junction  
temperature  
0
25  
125  
0
25  
125  
°C  
clock speed  
-
-
-
-
50  
-
-
-
-
-
80  
-
MHz  
%
clock duty cycle  
50  
-
50  
-
[6]  
ICC  
supply current  
f = 5 MHz  
3.5  
4.5  
mA  
[1] Meets TTL levels, VIO(min) = 2 V and VIH(max) = 0.8 V on non-hysteresis inputs.  
[2] Applies for external output buffers.  
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[3] These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150 °C. The customer is  
responsible for verifying junction temperature.  
[4] These parameters apply for D7-D0.  
[5] These parameters apply for DTRA, DTRB, INIA, INTB, RTSA, RTSB, RXRDYA, RXRDYB, TXRDYA, TXRDYB, TXA, TXB.  
[6] Measurement condition, normal operation other than sleep mode:  
VCC = 3.3 V; Tamb = 25 °C. Full duplex serial activity on all two serial (UART) channels at the clock frequency specified in the  
recommended operating conditions with divisor of 1.  
[7] Except x2, VOL = 1 V typical.  
[8] Applies to external clock; crystal oscillator max. 24 MHz.  
11. Dynamic characteristics  
Table 26: AC electrical characteristics  
Tamb = 40 °C to +85 °C; VCC = 2.5 V, 3.3 V ± 10% or 5 V ± 10%, unless specified otherwise.  
Symbol Parameter  
Conditions  
2.5 V  
Max  
3.3 V and 5 V  
Unit  
Min  
10  
20  
-
Min  
Max  
-
td1  
td2  
td3  
td4  
td5  
td6  
td7  
td8  
td9  
td10  
IOR delay from chip select  
-
0
20  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
read cycle delay  
25 pF load  
25 pF load  
25 pF load  
-
-
delay from IOR to data  
data disable time  
77  
15  
-
26  
15  
-
-
-
IOW delay from chip select  
write cycle delay  
10  
25  
-
10  
25  
-
-
-
delay from IOW to output  
25 pF load  
100  
100  
100  
1
33  
24  
24  
1
delay to set interrupt from modem input 25 pF load  
-
-
delay to reset interrupt from IOR  
delay from stop to set interrupt  
25 pF load  
-
-
-
-
Rclk baud  
rate  
td11  
td12  
td13  
delay from IOR to reset interrupt  
delay from start to set interrupt  
delay from IOW to transmit start  
25 pF load  
-
100  
100  
24  
-
29  
ns  
ns  
-
-
100  
24  
8
8
Rclk baud  
rate  
td14  
td15  
delay from IOW to reset interrupt  
delay from stop to set RXRDY  
-
-
100  
1
-
-
70  
1
ns  
Rclk baud  
rate  
td16  
td17  
td18  
delay from IOR to reset RXRDY  
delay from IOW to set TXRDY  
delay from start to reset TXRDY  
-
-
-
100  
100  
16  
-
-
-
75  
70  
16  
ns  
ns  
Rclk baud  
rate  
td19  
delay between successive assertion of  
IOW and IOR  
-
20  
-
20  
ns  
th1  
th2  
th3  
th4  
th5  
chip select hold time from IOR  
chip select hold time from IOW  
data hold time  
0
-
-
-
-
-
0
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
0
0
15  
0
15  
0
address hold time  
hold time from XTAL1 clock  
HIGH-to-LOW transition to IOW or IOR  
release  
20  
20  
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Table 26: AC electrical characteristics…continued  
Tamb = 40 °C to +85 °C; VCC = 2.5 V, 3.3 V ± 10% or 5 V ± 10%, unless specified otherwise.  
Symbol Parameter  
Conditions  
2.5 V  
Max  
3.3 V and 5 V  
Unit  
Min  
10  
-
Min  
Max  
tp1, tp2  
tp3  
t(RESET)  
tsu1  
clock cycle period  
-
6
-
ns  
[1]  
clock speed  
48  
-
-
80  
-
MHz  
ns  
RESET pulse width  
address set-up time  
data set-up time  
200  
0
200  
0
-
-
ns  
tsu2  
16  
20  
-
16  
20  
-
ns  
tsu3  
set-up time from IOW or IOR assertion  
to XTAL1 clock LOW-to-HIGH transition  
-
-
ns  
tw1  
tw2  
IOR strobe width  
IOW strobe width  
77  
30  
-
-
30  
30  
-
-
ns  
ns  
[1] Applies to external clock; crystal oscillator max 24 MHz.  
11.1 Timing diagrams  
VALID  
ADDRESS  
A0–A2  
t
t
h4  
su1  
ACTIVE  
CSA,  
CSB  
t
t
h1  
d1  
t
t
d2  
w1  
IOR  
ACTIVE  
t
d4  
t
d3  
D0–D7  
DATA  
002aaa235  
Fig 14. General read timing.  
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VALID  
ADDRESS  
A0–A2  
t
t
h4  
su1  
ACTIVE  
CSA,  
CSB  
t
t
h2  
d5  
t
t
d6  
w2  
IOW  
ACTIVE  
t
t
h3  
su2  
D0–D7  
DATA  
002aaa236  
Fig 15. General write timing.  
t
d19  
IOW  
IOR  
t
t
h5  
su3  
XTAL1  
002aaa237  
Fig 16. Alternate read/write strobe timing.  
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active  
IOW  
t
d7  
RTSA, RTSB  
DTRA, DTRB  
change of state  
change of state  
CDA, CDB  
CTSA, CTSB  
DSRA, DSRB  
change of state  
change of state  
t
t
d8  
d8  
INTA, INTB  
active  
active  
active  
active  
active  
t
d9  
active  
IOR  
t
d8  
change of state  
RIA, RIB  
002aaa238  
Fig 17. Modem input/output timing.  
next  
data  
Start  
bit  
parity Stop Start  
bit  
bit  
bit  
data bits (0 to 7)  
RXA, RXB  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
5 data bits  
6 data bits  
7 data bits  
t
d10  
active  
INTA, INTB  
t
d11  
active  
IOR  
16 baud rate clock  
002aaa239  
Fig 18. Receive timing.  
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NEXT  
DATA  
START  
BIT  
START  
BIT  
PARITY STOP  
BIT BIT  
DATA BITS (5-8)  
RXA  
RXB  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
t
d15  
ACTIVE  
DATA  
READY  
RXRDYA  
RXRDYB  
t
d16  
ACTIVE  
IOR  
002aaa240  
Fig 19. Receive ready timing in non-FIFO mode.  
PARITY STOP  
BIT BIT  
START  
BIT  
DATA BITS (5-8)  
RXA  
RXB  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
FIRST BYTE THAT  
REACHES THE  
TRIGGER LEVEL  
t
d15  
ACTIVE  
DATA  
READY  
RXRDYA  
RXRDYB  
t
d16  
ACTIVE  
IOR  
002aaa241  
Fig 20. Receive ready timing in FIFO mode.  
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next  
data  
Start  
bit  
parity Stop Start  
bit  
bit  
bit  
data bits (0 to 7)  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
TXA, TXB  
5 data bits  
6 data bits  
7 data bits  
t
d12  
active  
TX ready  
INTA, INTB  
t
t
d14  
d13  
active  
active  
IOW  
16 baud rate clock  
002aaa242  
Fig 21. Transmit timing.  
NEXT  
DATA  
START  
BIT  
PARITY STOP START  
BIT BIT  
BIT  
DATA BITS (5-8)  
TXA,  
TXB  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
ACTIVE  
IOW  
D0–D7  
BYTE #1  
t
d18  
t
d17  
ACTIVE  
TRANSMITTER READY  
TXRDYA,  
TXRDYB  
TRANSMITTER  
NOT READY  
002aaa243  
Fig 22. Transmit ready timing in non-FIFO mode.  
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START  
BIT  
PARITY STOP  
BIT  
BIT  
DATA BITS (5-8)  
TXA,  
TXB  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
5 DATA BITS  
6 DATA BITS  
7 DATA BITS  
ACTIVE  
IOW  
t
d18  
D0–D7  
BYTE #32  
t
d17  
TXRDYA,  
TXRDYB  
TRIGGER  
LEAD  
002aaa244  
Fig 23. Transmit ready timing in FIFO mode.  
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12. Package outline  
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm  
SOT313-2  
c
y
X
36  
25  
A
E
37  
24  
Z
E
e
H
E
A
2
A
(A )  
3
A
1
w M  
p
θ
pin 1 index  
b
L
p
L
13  
48  
detail X  
1
12  
Z
v M  
D
A
e
w M  
b
p
D
B
H
v
M
B
D
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.  
7o  
0o  
0.20 1.45  
0.05 1.35  
0.27 0.18 7.1  
0.17 0.12 6.9  
7.1  
6.9  
9.15 9.15  
8.85 8.85  
0.75  
0.45  
0.95 0.95  
0.55 0.55  
1.6  
mm  
0.25  
0.5  
1
0.2 0.12 0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
00-01-19  
03-02-25  
SOT313-2  
136E05  
MS-026  
Fig 24. LQFP48 (SOT313-2).  
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HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;  
32 terminals; body 5 x 5 x 0.85 mm  
SOT617-1  
B
A
D
terminal 1  
index area  
A
A
1
E
c
detail X  
C
e
1
y
y
e
1/2 e  
v
M
b
C
C
A B  
C
1
w M  
9
16  
L
17  
8
e
e
2
E
h
1/2 e  
1
24  
terminal 1  
index area  
32  
25  
X
D
h
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
(1)  
(1)  
UNIT  
A
b
c
E
e
e
e
2
y
D
D
E
L
v
w
y
1
1
h
1
h
max.  
0.05 0.30  
0.00 0.18  
5.1  
4.9  
3.25  
2.95  
5.1  
4.9  
3.25  
2.95  
0.5  
0.3  
mm  
0.05 0.1  
1
0.2  
0.5  
3.5  
3.5  
0.1  
0.05  
Note  
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
01-08-08  
02-10-18  
SOT617-1  
- - -  
MO-220  
- - -  
Fig 25. HVQFN32 (SOT617-1).  
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13. Soldering  
13.1 Introduction to soldering surface mount packages  
This text gives a very brief insight to a complex technology. A more in-depth account  
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit  
Packages (document order number 9398 652 90011).  
There is no soldering method that is ideal for all surface mount IC packages. Wave  
soldering can still be used for certain surface mount ICs, but it is not suitable for fine  
pitch SMDs. In these situations reflow soldering is recommended. In these situations  
reflow soldering is recommended.  
13.2 Reflow soldering  
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and  
binding agent) to be applied to the printed-circuit board by screen printing, stencilling  
or pressure-syringe dispensing before package placement. Driven by legislation and  
environmental forces the worldwide use of lead-free solder pastes is increasing.  
Several methods exist for reflowing; for example, convection or convection/infrared  
heating in a conveyor type oven. Throughput times (preheating, soldering and  
cooling) vary between 100 and 200 seconds depending on heating method.  
Typical reflow peak temperatures range from 215 to 270 °C depending on solder  
paste material. The top-surface temperature of the packages should preferably be  
kept:  
below 225 °C (SnPb process) or below 245 °C (Pb-free process)  
for all BGA, HTSSON..T and SSOP..T packages  
for packages with a thickness 2.5 mm  
for packages with a thickness < 2.5 mm and a volume 350 mm3 so called  
thick/large packages.  
below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with  
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.  
Moisture sensitivity precautions, as indicated on packing, must be respected at all  
times.  
13.3 Wave soldering  
Conventional single wave soldering is not recommended for surface mount devices  
(SMDs) or printed-circuit boards with a high component density, as solder bridging  
and non-wetting can present major problems.  
To overcome these problems the double-wave soldering method was specifically  
developed.  
If wave soldering is used the following conditions must be observed for optimal  
results:  
Use a double-wave soldering method comprising a turbulent wave with high  
upward pressure followed by a smooth laminar wave.  
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For packages with leads on two sides and a pitch (e):  
larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be  
parallel to the transport direction of the printed-circuit board;  
smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the  
transport direction of the printed-circuit board.  
The footprint must incorporate solder thieves at the downstream end.  
For packages with leads on four sides, the footprint must be placed at a 45° angle  
to the transport direction of the printed-circuit board. The footprint must  
incorporate solder thieves downstream and at the side corners.  
During placement and before soldering, the package must be fixed with a droplet of  
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the adhesive is cured.  
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or  
265 °C, depending on solder material applied, SnPb or Pb-free respectively.  
A mildly-activated flux will eliminate the need for removal of corrosive residues in  
most applications.  
13.4 Manual soldering  
Fix the component by first soldering two diagonally-opposite end leads. Use a low  
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time  
must be limited to 10 seconds at up to 300 °C.  
When using a dedicated tool, all other leads can be soldered in one operation within  
2 to 5 seconds between 270 and 320 °C.  
13.5 Package related soldering information  
Table 27: Suitability of surface mount IC packages for wave and reflow soldering  
methods  
Package[1]  
Soldering method  
Wave  
Reflow[2]  
BGA, HTSSON..T[3], LBGA, LFBGA, SQFP,  
SSOP..T[3], TFBGA, USON, VFBGA  
not suitable  
suitable  
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, not suitable[4]  
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,  
HVSON, SMS  
suitable  
PLCC[5], SO, SOJ  
suitable  
suitable  
LQFP, QFP, TQFP  
not recommended[5][6]  
not recommended[7]  
not suitable  
suitable  
SSOP, TSSOP, VSO, VSSOP  
CWQCCN..L[8], PMFP[9], WQCCN..L[8]  
suitable  
not suitable  
[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note  
(AN01026); order a copy from your Philips Semiconductors sales office.  
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the  
maximum temperature (with respect to time) and body size of the package, there is a risk that internal  
or external package cracks may occur due to vaporization of the moisture in them (the so called  
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated  
Circuit Packages; Section: Packing Methods.  
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Philips Semiconductors  
[3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must  
on no account be processed through more than one soldering cycle or subjected to infrared reflow  
soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow  
oven. The package body peak temperature must be kept as low as possible.  
[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom  
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with  
the heatsink on the top side, the solder might be deposited on the heatsink surface.  
[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave  
direction. The package footprint must incorporate solder thieves downstream and at the side corners.  
[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it  
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.  
[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSOP packages with a pitch (e) equal to or  
larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than  
0.5 mm.  
[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered  
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex  
foil by using a hot bar soldering process. The appropriate soldering profile can be provided on  
request.  
[9] Hot bar soldering or manual soldering is suitable for PMFP packages.  
14. Revision history  
Table 28: Revision history  
Rev Date  
CPCN  
-
Description  
03 20041214  
Product data (9397 750 14443)  
Modifications:  
There is no modification to the data sheet. However, reader is advised to refer to  
AN10333 (Rev. 02) “SC16CXXXB baud rate deviation tolerance” (9397 750 14411)  
that was released together with this revision.  
02 20040527  
01 20040326  
-
-
Product data (9397 750 13337)  
Product data (9397 750 11981)  
9397 750 14443  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 — 14 December 2004  
45 of 47  
SC16C752B  
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs  
Philips Semiconductors  
15. Data sheet status  
Level Data sheet status[1]  
Product status[2][3]  
Definition  
I
Objective data  
Development  
This data sheet contains data from the objective specification for product development. Philips  
Semiconductors reserves the right to change the specification in any manner without notice.  
II  
Preliminary data  
Qualification  
This data sheet contains data from the preliminary specification. Supplementary data will be published  
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in  
order to improve the design and supply the best possible product.  
III  
Product data  
Production  
This data sheet contains data from the product specification. Philips Semiconductors reserves the  
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant  
changes will be communicated via a Customer Product/Process Change Notification (CPCN).  
[1]  
[2]  
Please consult the most recently issued data sheet before initiating or completing a design.  
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at  
URL http://www.semiconductors.philips.com.  
[3]  
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.  
16. Definitions  
17. Disclaimers  
Short-form specification The data in a short-form specification is  
extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Life support — These products are not designed for use in life support  
appliances, devices, or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors  
customers using or selling these products for use in such applications do so  
at their own risk and agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Limiting values definition Limiting values given are in accordance with  
the Absolute Maximum Rating System (IEC 60134). Stress above one or  
more of the limiting values may cause permanent damage to the device.  
These are stress ratings only and operation of the device at these or at any  
other conditions above those given in the Characteristics sections of the  
specification is not implied. Exposure to limiting values for extended periods  
may affect device reliability.  
Right to make changes — Philips Semiconductors reserves the right to  
make changes in the products - including circuits, standard cells, and/or  
software - described or contained herein in order to improve design and/or  
performance. When the product is in full production (status ‘Production’),  
relevant changes will be communicated via a Customer Product/Process  
Change Notification (CPCN). Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no  
licence or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are  
free from patent, copyright, or mask work right infringement, unless otherwise  
specified.  
Application information Applications that are described herein for any  
of these products are for illustrative purposes only. Philips Semiconductors  
make no representation or warranty that such applications will be suitable for  
the specified use without further testing or modification.  
Contact information  
For additional information, please visit http://www.semiconductors.philips.com.  
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.  
Fax: +31 40 27 24825  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
46 of 47  
9397 750 14443  
Product data  
Rev. 03 — 14 December 2004  
SC16C752B  
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs  
Philips Semiconductors  
Contents  
1
2
3
4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
9
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 33  
Static characteristics . . . . . . . . . . . . . . . . . . . 33  
Dynamic characteristics. . . . . . . . . . . . . . . . . 34  
Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 35  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 41  
10  
11  
11.1  
12  
5
5.1  
5.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5  
13  
13.1  
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Introduction to soldering surface mount  
packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 43  
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 43  
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 44  
Package related soldering information. . . . . . 44  
6
6.1  
6.2  
6.2.1  
6.2.2  
6.3  
6.3.1  
6.3.2  
6.3.3  
6.4  
Functional description . . . . . . . . . . . . . . . . . . . 7  
Trigger levels. . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Hardware flow control. . . . . . . . . . . . . . . . . . . . 7  
Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Software flow control . . . . . . . . . . . . . . . . . . . . 9  
RX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Software flow control example . . . . . . . . . . . . 11  
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Interrupt mode operation . . . . . . . . . . . . . . . . 14  
Polled mode operation . . . . . . . . . . . . . . . . . . 14  
DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 15  
Single DMA transfers (DMA mode 0/FIFO  
13.2  
13.3  
13.4  
13.5  
14  
15  
16  
17  
Revision history . . . . . . . . . . . . . . . . . . . . . . . 45  
Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 46  
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
6.5  
6.5.1  
6.5.2  
6.6  
6.6.1  
disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Block DMA transfers (DMA mode 1). . . . . . . . 16  
Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Break and time-out conditions . . . . . . . . . . . . 17  
Programmable baud rate generator . . . . . . . . 17  
6.6.2  
6.7  
6.8  
6.9  
7
Register descriptions . . . . . . . . . . . . . . . . . . . 19  
Receiver holding register (RHR). . . . . . . . . . . 21  
Transmit holding register (THR) . . . . . . . . . . . 21  
FIFO control register (FCR) . . . . . . . . . . . . . . 22  
Line control register (LCR) . . . . . . . . . . . . . . . 23  
Line status register (LSR). . . . . . . . . . . . . . . . 24  
Modem control register (MCR) . . . . . . . . . . . . 25  
Modem status register (MSR). . . . . . . . . . . . . 26  
Interrupt enable register (IER) . . . . . . . . . . . . 26  
Interrupt identification register (IIR) . . . . . . . . 27  
Enhanced feature register (EFR) . . . . . . . . . . 28  
Divisor latches (DLL, DLH) . . . . . . . . . . . . . . . 29  
Transmission control register (TCR) . . . . . . . . 29  
Trigger level register (TLR) . . . . . . . . . . . . . . . 29  
FIFO ready register. . . . . . . . . . . . . . . . . . . . . 30  
7.1  
7.2  
7.3  
7.4  
7.5  
7.6  
7.7  
7.8  
7.9  
7.10  
7.11  
7.12  
7.13  
7.14  
8
Programmer’s guide . . . . . . . . . . . . . . . . . . . . 31  
© Koninklijke Philips Electronics N.V. 2004.  
Printed in the U.S.A.  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior  
written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or  
contract, is believed to be accurate and reliable and may be changed without notice. No  
liability will be accepted by the publisher for any consequence of its use. Publication  
thereof does not convey nor imply any license under patent- or other industrial or  
intellectual property rights.  
Date of release: 14 December 2004  
Document order number: 9397 750 14443  

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