SAA2503 [NXP]
MPEG2 audio decoder; MPEG2音频解码器
| 型号： | SAA2503 |
| 厂家： | 
NXP |
| 描述： | MPEG2 audio decoder |
| 文件： | 总20页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA2503
MPEG2 audio decoder
1997 Jul 02
Objective specification
File under Integrated Circuits, IC01
Philips Semiconductors
Objective specification
MPEG2 audio decoder
SAA2503
FEATURES
• Single-chip MPEG2 multichannel audio decoder
• Decodes MPEG high quality audio:
– MPEG1 layer 2 (44.1 kHz)
– MPEG2 multichannel layer 2 (48 kHz)
– Supports pause frames
• Outputs 2 channels
– Quasi surround down-mixing for Left and Right Dolby
surround channel (Lt and Rt)
APPLICATIONS
– Stereo down-mixing for stereo reproduction
– Stereo signal selection
This IC is mainly intended for use in Digital Versatile Disc
(DVD) players. However it may also be used in any
application that is able to accept an MPEG2 audio
bitstreams such as:
– Single channel down-mixing
• Karaoke modes
• Linear PCM modes:
• Set top boxes
– Down-sampling from 96 to 48 kHz
– Pass 48 kHz signals
• Bitstream input interface I2S-bus (IEC 1937 formatted)
• Multimedia PCs
• Digital television
• Next generation audio equipment.
• IEC 958 output interface (IEC 1937 formatted)
• IEC 958 output simultaneously available while decoding
MPEG2
GENERAL DESCRIPTION
The SAA2503 incorporates all necessary functions, such
as MPEG2 multichannel audio decoding plus
• I2C-bus control
• Output flags for direct control
• Stand-alone operation possible (self-booting)
• No external DRAM or SRAM required
• On-chip PLL for internal clock generation
• 13.5 or 27 MHz master clock
• 100 pins plastic LQFP package
• 5 V power supply.
down-mixing, MPEG1 layer 2 decoding, Linear PCM
(LPCM) processing all producing high quality audio.
Together with the serial audio interfaces and the IEC 958
transmitter this allows for the complete audio function of a
DVD player in a single chip.
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
SAA2503HT
LQFP100 plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
1997 Jul 02
2
Philips Semiconductors
Objective specification
MPEG2 audio decoder
SAA2503
FUNCTIONAL I/O DIAGRAM
H0 to H7
HA2
HA0
HA0 to HA2
HR/W
2
I C-BUS
SERIAL
HOST
INTERFACE
PARALLEL
HOST
INTERFACE
SDA
HEN
SLK
HOREQ
HACK/PB14
HREQ
SDB
SCKR
WSR
SCKT
WST
SAA2503
GPIO0 to GPIO3
I2CEN
SERIAL
AUDIO
INTERFACE
SDI0
BUSY
SDI1
FLAGS
MUTE
SDO0
SDO1
SDO2
ADO
ACI
IEC 958
TRANSMITTER
DSCK/OS1
DSI/OS0
DSO
OnCE
resrved (19)
DR
MODC
MODB
MODA
reset
interrupt
PLOCK
PCAP
PINIT
PLL
RESET
EXTAL
MGK396
Fig.1 Functional I/O diagram.
3
1997 Jul 02
Philips Semiconductors
Objective specification
MPEG2 audio decoder
SAA2503
PINNING
SYMBOL
n.c.
PIN
I/O
DESCRIPTION
1
−
−
not connected
not connected
n.c.
2
GNDA1
n.c.
3
GND ground 1 for some sections of internal logic
4
−
−
not connected
not connected
not used
n.c.
5
H7/PB7
H6/PB6
GNDH1
HOA2/PB10
VCCH1
6
I/O
I/O
7
not used
8
GND isolated ground 1 for the HI I/O drivers
I/O not used
supply isolated power supply 1 for some sections of the internal chip logic
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
HOA1/PB9
HR/W/PB11
HEN/PB12
VCCQ1
I/O
I/O
I/O
not used
not used
not used
supply isolated power supply 1 for the HI I/O drivers
GND isolated ground 1 for the internal logic
GNDQ1
HACK/PB14
GNDH2
HOA0/PB8
H5/PB5
VCCH2
I/O
not used
GND isolated ground 2 for the HI I/O drivers
I/O
I/O
not used
not used
supply isolated power supply 2 for the HI I/O drivers
H4/PB4
H3/PB3
GNDH3
H2/PB2
H1/PB1
H0/PB0
HOREQ/PB13
GNDH4
VCCH3
I/O
I/O
not used
not used
GND isolated ground 3 for the HI I/O drivers
I/O
I/O
I/O
I/O
not used
not used
not used
not used
GND isolated ground 4 for the HI I/O drivers
supply isolated power supply 3 for the HI I/O drivers
ADO
O
I
digital audio data output
audio clock input
ACI
n.c.
−
−
−
O
not connected
n.c.
not connected
n.c.
not connected
PLOCK
VCCQ2
HIGH when PLL is phase locked
supply isolated power supply 2 for some sections of the internal chip logic
GND isolated ground 2 for the internal logic
GNDQ2
PINIT
I
PLL enable/disable control
GND ground dedicated for the PLL
PLL capacitor input
GNDP
PCAP
I
1997 Jul 02
4
Philips Semiconductors
Objective specification
MPEG2 audio decoder
SAA2503
SYMBOL
VCCP
PIN
I/O
DESCRIPTION
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
supply supply voltage for the Phase Locked Loop (PLL)
EXTAL
SCL
I
I
external clock/crystal Input
I2C-bus serial clock
GNDS1
SDA
GND isolated ground 1 for the SHI I/O drivers
I/O
I2C-bus data and acknowledge
hardware reset for the microcontroller
mode select A
RESET
MODA
MODB
MODC
VCCS1
HA0
I
I
I
I
mode select B
mode select C
supply isolated power supply 1 for the SHI I/O drivers
I/O
I2C-bus slave address 0
I2C-bus slave address 2
host request
HA2
I
I
HREQ
GNDS2
SDO2
SDO1
SDO0
VCCS2
SCKT
WST
GND isolated ground 2 for the SHI I/O drivers
O
O
O
not used
not used
serial data output 0
supply isolated power supply 2 for the SHI I/O drivers
O
O
I
transmit serial clock
transmit word select
receive serial clock
SCKR
GNDQ3
VCCQ3
GNDS3
WSR
GND ground 3 dedicated for the PLL
supply isolated power supply 3 for some sections of the internal chip logic
GND isolated ground 3 for the SHI I/O drivers
I
I
receive word select
serial data input 1
not used
SDI1
SDI0
I
DSO
O
O
O
−
not used
DSI/OS0
DSCK/OS1
n.c.
not used
not used
not connected
not connected
not connected
not connected
not used
n.c.
−
n.c.
−
n.c.
−
DR
I
SDB
I/O
I/O
general purpose I/O
general purpose I/O
MUTE
GNDD1
BUSY
I2CEN
VCCD1
GND ground 1 for some sections of internal logic
I/O
I/O
general purpose I/O
general purpose I/O
supply isolated power supply 1 for some sections of the internal chip logic
1997 Jul 02
5
Philips Semiconductors
Objective specification
MPEG2 audio decoder
SAA2503
SYMBOL
GPIO3
PIN
I/O
DESCRIPTION
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
I/O
not used
not used
GPIO2
GNDD2
GPIO1
GPIO0
GNDQ4
VCCQ4
n.c.
GND ground 2 for some sections of internal logic
I/O
I/O
not used
not used
GND ground 4 for some sections of internal logic
supply isolated power supply 4 for some sections of the internal chip logic
−
−
not connected
not connected
n.c.
GNDA2
n.c.
GND ground 2 for some sections of internal logic
not connected
supply isolated power supply 1 for some sections of the internal chip logic
−
VCCA1
n.c.
−
−
not connected
not connected
n.c.
GNDA3
n.c.
GND ground 3 for some sections of internal logic
−
−
−
not connected
not connected
not connected
n.c.
n.c.
VCCA2
supply isolated power supply 2 for some sections of the internal chip logic
1997 Jul 02
6
Philips Semiconductors
Objective specification
MPEG2 audio decoder
SAA2503
n.c.
n.c.
1
2
75 DR
n.c
n.c
74
73
GNDA1
n.c
3
4
72 n.c
71 n.c
n.c
5
H7/PB7
H6/PB6
GNDH1
HOA2/PB10
6
DSCK/OS1
DSI/OS0
70
69
7
8
68 DSO
67 SDI0
9
V
10
11
12
13
14
15
SDI1
WSR
66
65
CCH1
HOA1/PB9
HR/W/PB11
HEN/PB12
64 GNDS3
V
SAA2503
63
62
61
CCQ3
V
GNDQ3
CCQ1
GNDQ1
SCKR
HACK/PB14 16
GNDH2 17
60 WST
59 SCKT
V
HOA0/PB8
H5/PB5
18
19
20
58
57
CCS2
SDO0
V
56 SDO1
55 SDO2
CCH2
H4/PB4 21
H3/PB3 22
GNDH3 23
H2/PB2 24
H1/PB1 25
GNDS2
HREQ
54
53
52 HA2
51 HA0
MGK395
Fig.2 Pin configuration.
7
1997 Jul 02
Philips Semiconductors
Objective specification
MPEG2 audio decoder
SAA2503
• LPCM down-sampling DVD (96 kHz: 4 channel input;
48 kHz 2 channel output)
FUNCTIONAL DESCRIPTION
Operating modes
• LPCM DVD (48 kHz: 8 channel input; 2 channel output).
The SAA2503 can operate in 2 modes.
Stand-alone (mode 4)
System clock
The preferred system clock to be applied to the EXTAL pin
of the SAA2503 is 27 MHz if booted in mode 4
(stand-alone operation).
In this mode (modC = 1, modB = 0 and modA = 0) the
SAA2503 boots itself from the internal program ROM after
power-up and can start decoding when a decoding mode
has been selected via the I2C-bus.
The internal PLL multiplies this clock by a factor of 3 to
obtain an 81 MHz internal clock.
Booting via the I2C-bus (mode 7)
If using another external clock frequency it is advisable to
ensure that:
In this mode (modC = 1, modB = 1 and modA = 1) the
SAA2503 starts executing an internal boot program that
will receive 1536 bytes via the I2C-bus and then write
those to an on-chip program RAM.
• The internal PLL is disabled during booting when
fclk(ext) > 27 MHz
• That 10 MHz < (fclk(ext) × 3) < 81 MHz.
This mode allows the standard behaviour (I/O interfaces,
additional processing) to be modified as specified in the
stand-alone mode.
INTERFACING TO THE A/V SPLITTER
Serial audio interface
Decoding modes
The serial audio interface can be configured as an I2S-bus
interface and when required, as Quad I2S interface.
The signal received via the I2S-bus is an encoded audio
bitstream in accordance with IEC 1937, or LPCM.
The SAA2503 has the following decoding modes:
• MPEG decoding (48 kHz DVD; 44.1 kHz VCD) IEC 958
LPCM
• MPEG decoding (48 kHz DVD; 44.1 kHz VCD) IEC 958
BITSTR
• LPCM CD-DA (44.1 kHz)
Table 1 Pinning of the I2S-bus interface
PINS
SDI0
DESCRIPTION
high impedance
PIN NUMBER
DIRECTION
67
66
57
56
55
61
65
76
59
60
not used
input/output
output
not used
not used
input
SDI1
serial data
SDO0
SDO1
SDO2
SCKR
WSR
SDB
serial data
serial data
serial data
I2S-bus clock; notes 1 and 2
word select receive
serial data begin
I2S-bus clock; notes 1 and 2
word select transmit
input
input
SCKT
WST
input
input
Notes
1. SCKT is equal to SCKR when the I2S-bus format is the format of the input signal. When Quad I2S-bus is used
SCKT = 1⁄4SCKR.
2. The maximum allowed clock frequency for SCK is 1⁄3fclk (fclk is the internal clock generated by the PLL of the
SAA2503).
1997 Jul 02
8
Philips Semiconductors
Objective specification
MPEG2 audio decoder
SAA2503
QUAD I2S-BUS
MPEG2 bitstreams
The MPEG2 audio bitstream is received via the I2S-bus in
the same format as specified in IEC 1937. The MPEG2
audio bitstream consists of data bursts of 1 frame.
The data is formatted in 16-bit chunks. The time period
until the next frame is filled with logic 0. The serial data is
received by the SAA2503 via the SDI1 pin (pin 66).
Quad I2S-bus is the interface providing audio samples in
LPCM with 4 times the sampling frequency. The interface
is an extension of the I2S-bus where the Serial Data Begin
(SDB) indicates the first 2 channels out of 8 channels.
The audio samples are transferred with MSB first, where
each sample occupies 32 bits, filled with logic 0.
For more information on transporting MPEG2 bitstreams
via IEC 958 see IEC 1937.
Linear PCM (LPCM)
I2S-BUS
Linear PCM samples are received in an I2S-bus format.
Serial audio data is received via SDI1 (pin 66).
The I2S-bus clock is received via SCKR (pin 61) and the
I2S-bus word select is received via WSR (pin 65); the
I2S-bus clock operates at 64fs.
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SD
WS
SDB
SCK
2
2
1 S-bus clock/Quad 1 S-bus clock
1 sampling period
MGK398
Fig.3 Quad I2S-bus frame format.
The SDB remains HIGH when only 2 channels LPCM or encode bitstreams (in accordance with IEC 1937) are
transferred (Quad I2S-bus is equal to I2S-bus).
1997 Jul 02
9
Philips Semiconductors
Objective specification
MPEG2 audio decoder
SAA2503
Table 2 Allocation of LPCM channels on Quad I2S-bus, fs = 48 or 96 kHz
INPUT
CH3
NUMBER OF
fs (kHz)
LPCM CHANNELS
CH0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
CH1
mute
Q1
CH2
mute
mute
Q2
CH4
mute
mute
mute
mute
Q4
CH5
mute
mute
mute
mute
mute
Q5
CH6
mute
mute
mute
mute
mute
mute
Q6
CH7
mute
mute
mute
mute
mute
mute
mute
Q7
1
2
3
4
5
6
7
8
1
2
3
4
48
48
48
48
48
48
48
48
96
96
96
96
mute
mute
mute
Q3
Q1
Q1
Q2
Q1
Q2
Q3
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q5
Q1
Q2
Q3
Q4
Q5
Q6
mute
Q1
mute
mute
Q2
mute
mute
mute
Q3
Q0
mute
Q1
mute
mute
Q2
mute
mute
mute
Q3
Q0
Q1
Q0
Q1
Q1
Q2
Q0
Q1
Q2
SD
channel n + 1
WS
channel n
SDB
SCK
0
31 0
31
channel 0, 2, 4 or 6
channel 1, 3, 5 or 7
MGK397
Fig.4 Quad I2S-bus channel format.
1997 Jul 02
10
Philips Semiconductors
Objective specification
MPEG2 audio decoder
SAA2503
The burst_preamble provides a sync_word, information on
the burst_payload and the bitstream number.
AUDIO OUTPUTS INTERFACING
Also see Chapter “Interfacing to the A/V splitter”.
The interface may convey one or more bitstreams. Each
type of bitstream may impose a particular requirement for
the repetition time for the data bursts that make up the
bitstream.
Stereo output for DAC
The output stereo down-mixing signal is in I2S-bus format
and can be directly connected to a DAC. The SDO0
(pin 57) provides the output for the serial audio data.
Furthermore, SCKT (pin 59) provides the I2S-bus clock
and WST (pin 60), the I2S-bus word select.
The 16-bit data words of a data burst are placed in time
slots 12 to 27 of an IEC 958 sub frame. In the consumer
application, both odd and even IEC 958-sub frames (CH1
and CH2) are simultaneously used to carry 32-bit data
words (32-bit mode). This allows the consumer IEC 958 to
convey either 2-channel LPCM audio, or a set of
alternating data words, but not both simultaneously.
For more information see IEC 1937.
IEC 958 transmitter
The format of the IEC 958 interface consists of a sequence
of IEC 958 sub frames. Each IEC 958 sub frame is
normally used to carry one LPCM sample. The IEC 958
sub frame may also be used to convey data words.
The non-PCM encoded audio bitstreams to be transferred
are formed into data bursts. These bitstreams consist of a
sequence of data words.
The IEC 958 interface is of the digital audio interface. This
conveys LPCM or encoded audio bitstreams according to
IEC 1937 (IEC 1937), using the ‘network layer’ of IEC 958
(IEC 958). The audio data will be accompanied by a
validity bit, channel status and user data (sub code).
Each data burst contains a 64-bit burst_preamble,
followed by the burst_payload.
Table 3 Pinning of IEC 958 interface
PINS
DESCRIPTION
Audio Data Output
Audio Clock Input; note 1
PIN NUMBER
DIRECTION
ADO
ACI
30
31
output
input
Note
1. The ACI clock is 256fs (or 512 or 384fs).
3. MPEG decoding active and synchronised (pin 77);
MUTE: when the SAA2503 operates in the MPEG
decoding mode, this flag indicates the state of the
SAA2503 (synchronized or not). When this pin is at
logic 1 the SAA2503 is out of sync, when set to logic 0
the SAA2503 is synchronized. It will not change state
when the SAA2503 remains synchronized. When the
SAA2503 is operating in one of the LPCM modes, the
MUTE pin is set at logic 1 during initialization and
logic 0 during processing.
INTERFACING WITH THE MICROCONTROLLER
Flags
The SAA2503 has 3 flags which, after a hardware reset,
are all initialized to logic 1.
1. I2C-bus communication disabled (pin 80); I2CEN: this
flag is set to logic 0 when the SAA2503 is ready to
accept messages via the I2C-bus.
2. Life test (pin 79); BUSY: when the SAA2503 operates
in the MPEG decoding mode, this flag toggles
whenever the SAA2503 has detected a
I2C-bus interface
synchronization pattern. The flag will then produce a
20.833 Hz (fas = 48 kHz) and a 19.140 Hz
The I2C-bus interface supports data rates of up to
400 kbits/s. For a description of the I2C-bus see
“The I2C-bus and how to use it”, ordering number
9398 393 40011.
(fas = 44.1 kHz) signal. It can be used to monitor the
MPEG decoding process. When this flag no longer
toggles there is an error. When the SAA2503 operates
in one of the LPCM modes however, the flag produces
either a 23.437 Hz (fas = 48 kHz) or a 21.533 Hz
(fas = 44.1 kHz) signal.
For a description of the I2C-bus commands controlling the
SAA2503 see Table 1.
1997 Jul 02
11
Philips Semiconductors
Objective specification
MPEG2 audio decoder
SAA2503
APPLICATION SCHEMATIC
RESET
L14
POWER
V
C73
C74
C75
C76
SS
GND
100 nF
100 nF
100 nF
100 nF
41
93 100
81
10 20 29
14 36 63 88
50 58
65
WS-IN
SCK-IN
SD-IN
26
H0/PB0
A
B
C
WSR
SCKR
SDI0
SDI1
WST
61
67
66
60
59
57
56
55
25
H1/PB1
24
H2/PB2
22
H3/PB3
21
H4/PB4
D
E
F
19
H5/PB5
SCKT
SDO0
SDO1
SDO2
7
H6/PB6
6
H7/PB7
18
HOA0/PB8
11
IEC 958
OUT (EBU)
HOA1/PB9
30
31
9
HOA2/PB10
ADO
ACI
G
12
HR/W/PB11
R134
SAA2503
13
HEN/PB12
10 kΩ
70
69
68
75
27
HOREQ/PB13
DSCK/OS1
DSI/OS0
DSO
R135
16
HACK/PB14
10 kΩ
86
GPIO0
DR
JP37
85
GPIO1
jumper
83
35
40
38
42
GPIO2
H
I
PLOCK
PCAP
PINIT
JP38
82
GPIO3
jumper
I2CEN 80
I2CEN
J
JP39
BUSY
MUTE
SDB
79
77
76
EXTAL
BUSY
MUTE
SDB
jumper
JP40
jumper
JP41
39
3
91 96 78 84
51 52 45 43 53
47 48 49 46
8
17 23 28 15 37 62 87 44
RESET
4
54
jumper
jumper
jumper
jumper
R136
JP42
JP43
JP44
10 kΩ
R137
MODE SETTINGS
10 kΩ
R138
10 kΩ
R139
jumper
jumper
JP45
JP46
2
I C-BUS ADDRESS
SETTINGS
10 kΩ
R140
K
10 kΩ
JP
U11B
SCL
1
MUTE
3
4
SDA
2
I C-BUS CONTROL
2
3
74HC04
MGK399
HEADER 3
Fig.5 Application diagram (continued in Fig.6).
12
1997 Jul 02
Philips Semiconductors
Objective specification
MPEG2 audio decoder
SAA2503
serial audio data
from A/V splitter
JP
HEADER 4
D/A-CLK
1
2
3
4
A
B
C
SDB
D
E
F
16
14 15
7
8
R
47 kΩ
C
22
23
25
24
26
28
27
12
VOL
FILTCL
VOR
J2
BNC
SYSCLK1
WS
C
1 nF
10 µF
G
V
SWS
SCK
5
4
via OP-AMP to
analog output
CC
BCK
D8
C
LED
DATA-L-R
6
DATA
17
C
1 nF
10 µF
DEEM1
EMP1
47 kΩ
18
21
19
20
13
3
R142
470 Ω
EMP2
DEEM2
ATSB
MUSB
DSMB
n.c.
FILTCR
TDA1305
U11A
V
CC
1
2
V
ref
MUTE
V
C
CC
V
100
74HC04
CC
H
I
nF
V
DDO
C
TEST1
TEST2
100
nF
J
47 µF
11
V
C78
1.2 nF
SSO
10
kΩ
JP50
jumper
R141
10
9
1
2
C
47 µF
C
C
100 nF
100 nF
MGK400
V
V
CC
CC
74HC04 decoupling
C79
100 nF
R143
4.7 kΩ
DR
L7
V
CC
BLM21A10
8
V
CC
R110
100E
5
C32
100 nF
U54
27 MHz OSC
K
OUT
GND
4
Fig.6 Application diagram (continued from Fig.5).
13
1997 Jul 02
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Objective specification
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PACKAGE OUTLINE
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
y
X
A
51
75
50
26
(1)
76
Z
E
e
Q
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
L
pin 1 index
detail X
100
1
25
Z
D
v
M
A
B
e
w M
b
p
D
B
H
v
M
5
D
0
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.5
0.05 1.3
0.28 0.18 14.1 14.1
0.16 0.12 13.9 13.9
16.25 16.25
15.75 15.75
0.75 0.70
0.45 0.57
1.15 1.15
0.85 0.85
mm
1.6
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-12-19
SOT407-1
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If wave soldering cannot be avoided, the following
conditions must be observed:
SOLDERING
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1997 Jul 02
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DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Jul 02
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NOTES
1997 Jul 02
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NOTES
1997 Jul 02
18
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NOTES
1997 Jul 02
19
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547027/1200/01/pp20
Date of release: 1997 Jul 02
Document order number: 9397 750 01802
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