SAA2505H-T [NXP]
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NXP 
INTEGRATED CIRCUITS
DATA SHEET
SAA2505H
Digital multi-channel audio IC
(DUET)
1998 Mar 10
Preliminary specification
File under Integrated Circuits, IC01
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
FEATURES
Hardware features
• Two 40 MIPS 20-bit DSP cores
• All input and output buffer RAM is on-chip
• Program ROM on-chip for all decoding modes
• Two I2S-bus inputs with normal, double and quad speed
APPLICATIONS
The SAA2505H is intended for all markets where a
multi-channel audio decoder for Dolby AC-3 and MPEG 2
is required.
mode (slave only)
• Second serial input usable for ADC (Karaoke input)
• Three normal and double speed I2S-bus outputs (slave
and master from 256 and 384fs)
• One normal, double, quad speed I2S-bus output (slave
and master from 256 and 384fs)
Primary markets are for DVD video players, TV sets and
audio/video amplifiers.
• Japanese EIAJ serial input and output formats
• Sony Philips Digital Interface (SPDIF) output
• I2C-bus control (up to 400 kHz)
GENERAL
The SAA2505H decodes multi-channel audio up to
MPEG 7.1, AC-3 5.1 and pro-logic on a dual DSP core.
• 3.3 V supply with 5 V TTL compatible inputs/outputs
• Boundary scan for printed-circuit board testing.
The device contains all of the RAM and ROM necessary
for operation. This minimises the need for external
components and no microcode download is required.
Software features
The device is primarily intended for audio/video surround
sound amplifiers where the amplifier is connected to the
data source by means of SPDIF (IEC 60958). The input
interface is, therefore, made for SPDIF (IEC 60958) and
formatted for the I2S-bus.
• AC-3 up to 5.1 channels
• MPEG 2 L2 up to 7.1 channels
• MPEG 1 L2 (Video-CD) 2 channels at 44.1 kHz
• Dolby pro-logic decoding at 32, 44.1 and 48 kHz
The primary device output is PCM, sent via four I2S-bus
ports. There is also a SPDIF (IEC 60958) formatted
output.
• Output configuration for 7, 5, 4, 3, 2 and 1 channels
with or without Low Frequency Enhancement (LFE)
• Bass redirection for small satellite loudspeakers plus
subwoofer
User control is achieved via an I2C-bus. However, the
SAA2505H is capable of stand-alone operation.
• Karaoke voice mix
• Dynamic range compression (AC-3 and MPEG)
• Adjustable delay up to 15 ms for surround channels
(1.5 kbyte words)
• Adjustable delay up to 5 ms for centre channel
(250 words)
• Rounding to DAC word length
• Mute by pin and I2C-bus command
• AC-3 and MPEG bitstream information available via the
I2C-bus
• Concealment of CRC errors
• SPDIF coded output
• Fully programmable SPDIF channel status information.
1998 Mar 10
2
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
QUICK REFERENCE DATA
SYMBOL
VDDD
PARAMETER
digital supply voltage
CONDITIONS
MIN.
3.0
TYP.
3.3
MAX.
3.6
UNIT
V
IDDD
VDDA
IDDA
fxtal
digital supply current
analog supply voltage
analog supply current
crystal frequency
−
160
3.3
tbf
35
−
−
mA
V
3.0
3.6
−
−
mA
MHz
°C
V
−
−
Tamb
VESD
operating ambient temperature
0
70
electrostatic discharge sensitivity
for all pins
note 1
note 2
−2000
−300
−
+2000
+300
−
V
Notes
1. Human body model: equivalent to discharging a 100 pF capacitor through a 1500 Ω resistor.
2. Machine model: equivalent to discharging a 200 pF capacitor through a 0 Ω resistor.
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
SAA2505H
QFP64
plastic quad flat package; 64 leads (lead length 1.6 mm);
SOT393-1
body 14 × 14 × 2.7 mm
1998 Mar 10
3
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,kfullapgwedhit
2
I S-bus
DELAY
interface
L
8 channels
IEC 1397
PARSER
bitstream
IIS0
R
audio clock
256 or 384f
bitstream
e.g. from
microphone
C
IIS1
s
LFE
LS
RS
LC
RC
MPEG2
OR
AC-3
LT, RT
L, R, C, S
PRO LOGIC
DECODER
DOWN-
MIXING
AND
VOLUME
CONTROL
channels
1 to 8
SWITCH
2
I S-BUS
OUTPUTS
8 channels
channels
1 to 8
NOISE
GENERATOR
PCM
AND
DOWN-
SAMPLING
microphone
bitstream
L, R
DOWN-
MIXING
SPDIF
MGL324
Fig.1 Simplified block diagram.
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
PINNING
DRIVE/
SYMBOL
PIN
TYPE
DESCRIPTION
select stand-alone mode input
LOAD(1)
STANDALONE
EFO1
EFO2
EFO3
EFO4
EFO5
EFO6
VSSDI
1
2
A
F
F
F
F
F
F
−
I
O
O
O
O
O
O
S
S
I
output flag FO1; from DSP2
output flag FO2; from DSP2
output flag FO3; from DSP2
output flag FO4; from DSP1
output flag FO5; from DSP1
output flag FO6; from DSP1
3
4
5
6
7
8
digital ground for internal logic and memories; note 2
digital supply voltage for internal logic and memories (+3.3 V); note 3
input flag FI1; to DSP2
VDDDI
9
−
EFI1
10
11
12
13
14
A
A
A
−
EFI2
I
input flag FI2; to DSP1
EFI3
I
input flag FI3; to DSP1
VDDDE
WSO
S
I/O
digital supply voltage for I/O cells (+3.3 V); note 4
G
word select input/output for ports 0 to 2; also used for output port 3
when not in quad mode (I2S-bus)
SCK
15
G
I/O
serial clock input/output for ports 0 to 2; also used for output port 3
when not in quad mode (I2S-bus)
VSSDE
SDO0
SDO1
VDDDE
VSSDI
VDDDI
VSSDI
VDDDI
VDDDI
VSSDI
VDDDE
SDO2
SDO3
VSSDE
WSO3
SCKO3
VDDDE
SDB
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
−
F
F
−
−
−
−
−
−
−
−
F
F
−
F
F
−
F
F
−
−
−
S
O
O
S
S
S
S
S
S
S
S
O
O
S
O
O
S
O
O
S
S
S
digital ground for I/O cells; note 5
serial data output for port 0 (I2S-bus)
serial data output for port 1 (I2S-bus)
digital supply voltage for I/O cells (+3.3 V); note 4
digital ground for internal logic and memories; note 2
digital supply voltage for internal logic and memories (+3.3 V); note 3
digital ground for internal logic and memories; note 2
digital supply voltage for internal logic and memories (+3.3 V); note 3
digital supply voltage for internal logic and memories (+3.3 V); note 3
digital ground for internal logic and memories; note 2
digital supply voltage for I/O cells (+3.3 V); note 4
serial data output for port 2 (I2S-bus)
serial data output for port 3 (I2S-bus)
digital ground for I/O cells; note 5
word select output for port 3; used in quad mode (I2S-bus)
serial clock output for port 3; used in quad mode (I2S-bus)
digital supply voltage for I/O cells (+3.3 V); note 4
serial data begin output for port 3; used in quad mode (I2S-bus)
SPDIF output
SPDIF
VSSDE
VSSDI
VDDDI
digital ground for I/O cells; note 5
digital ground for internal logic and memories; note 2
digital supply voltage for internal logic and memories (+3.3 V); note 3
1998 Mar 10
5
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
DRIVE/
SYMBOL
VSSDE
PIN
TYPE
DESCRIPTION
LOAD(1)
38
39
40
41
42
43
44
45
46
47
−
E
−
S
O
S
S
I
digital ground for I/O cells; note 5
programmable system clock output
SYSCLK
VDDDE
VDDA
digital supply voltage for I/O cells (+3.3 V); note 4
analog supply voltage for crystal oscillator (+3.3 V)
oscillator input
−
CLKI
H
H
−
CLKO
VSSDA
ACLK
VSSDE
TDI
O
S
I
oscillator output
digital ground for crystal oscillator
audio clock input for master mode
digital ground for I/O cells; note 5
A
−
S
I
B
boundary scan test data input (this pin should be pulled HIGH for
normal operation)
TMS
48
B
I
boundary scan test mode select input (this pin should be pulled HIGH
for normal operation)
TCK
49
50
B
B
I
I
boundary scan test clock input
TRST
boundary scan test reset input (this pin should be pulled LOW for
normal operation)
TDO
51
52
53
54
55
56
57
58
59
60
61
62
63
64
B
−
O
S
S
I
boundary scan test data output
VDDDI
VSSDI
WSI
digital supply voltage for internal logic and memories (+3.3 V); note 3
digital ground for internal logic and memories; note 2
word select input for ports 0 and 1 (I2S-bus)
serial data begin input for port 0 (I2S-bus)
serial data input for port 0 (I2S-bus)
−
A
A
A
A
A
−
SDBI
SDI0
SDI1
SCKI
VSSDI
VDDDI
RESET
ADDR
SCL
I
I
I
serial data input for port 1 (I2S-bus)
I
serial clock input for ports 0 and 1 (I2S-bus)
digital ground for internal logic and memories; note 2
digital supply voltage for internal logic and memories (+3.3 V); note 3
hardware reset
select address input (I2C-bus)
serial clock input; external pull-up to +5 V (I2C-bus)
serial data input/output; external pull-up to +5 V (I2C-bus)
S
S
I
−
C
A
C
D
I
I
SDA
I/O
Notes
1. See Table 1.
2. All VSSDI pins are internally connected.
3. All VDDDI pins are internally connected.
4. All VDDDE pins are internally connected.
5. All VSSDE pins are internally connected.
1998 Mar 10
6
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
Table 1 Pin drive and load descriptions
DRIVE/LOAD
DESCRIPTION
A
B
C
D
E
F
+5 V tolerant input; TTL characterized with internal pull-down resistor
+5 V tolerant input; TTL characterized with internal pull-up resistor
+5 V tolerant input; TTL Schmitt-trigger characterized
+5 V tolerant 400 kHz (I2C-bus)
TTL characterised +5 V tolerant 3-state output with 3 mA drive capability
TTL characterised +5 V tolerant 3-state slew rate limited output with 3 mA drive capability
G
+5 V tolerant bidirectional 3-state pin; with 3 mA output drive and slew rate limiting; TTL level input;
without pull-up or pull-down resistor
H
crystal pins
STANDALONE
1
2
3
4
5
6
7
8
9
48 TMS
EFO1
EFO2
EFO3
EFO4
EFO5
EFO6
TDI
V
47
46
SSDE
45 ACLK
V
44
SSDA
43 CLKO
42 CLKI
V
V
41
40
SSDI
DDA
SAA2505H
V
V
DDDE
DDDI
EFI1 10
EFI2 11
EFI3 12
39 SYSCLK
V
V
V
V
38
37
36
35
34
SSDE
DDDI
SSDI
SSDE
V
V
13
14
15
16
DDDE
WSO
SCK
SPDIF
33 SDB
SSDE
MGL323
Fig.2 Pin configuration.
7
1998 Mar 10
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
In the I2S-bus slave mode the output data is clocked to
pin 15. This can either be the serial clock input at pin 58
(SCKI) or a suitable external clock. When in slave mode
the signal at pin 15 is replicated at pin 31.
CLOCK BUILD-UP
Up to four clocks provide the timing information for the
SAA2505H. These are as follows:
1. Data source clock
2. Data processing clock
3. I2C-bus data/control clock
4. Data sink clock.
FUNCTIONAL DESCRIPTION
Data sinks
Coded audio data or PCM audio data can be input to both
DSPs from two slave-only serial interfaces capable of
receiving data in either I2S-bus or EIAJ formats. Both serial
interfaces use the same serial clock (pin 58) and word
select input (pin 54). The serial clock must be at least 32fs.
Data source clock
Clocking of the input data is derived from the serial clock
input at pin 58 and is compliant with the I2S-bus and EIAJ
transfer formats. The ports are capable of operating at
normal, double and quad speed.
Serial data is applied to pins 56 and 57 (SDI0 and SDI1).
These pins are mode shared between the I2S-bus and
EIAJ formatted serial data. Port mode selection is
achieved via the I2C-bus interface, see Table 3.
Data processing clock
This clock is used for data processing and internal data
transfer. The clock can either be provided by an external
clock generator having a duty cycle between 40 and 60%
or by using the internal crystal clock generator and an
external crystal. The external clock should be connected
between pins 42 (CLKI) and 43 (CLKO) (see Fig.11).
I2S-BUS FORMATTED SPDIF INFORMATION
In the I2S-bus mode ‘big-endian’ data is received, MSB
justified to 1 clock period after a falling edge of the word
select output. The data stream should be formatted
according to “IEC 60958 - SPDIF” including the extensions
for non-PCM encoded audio data (“IEC 61937”).
To use the internal clock a 35 MHz crystal operating on the
3rd harmonic must be connected between pins 42 and 43
(CLKI and CLKO).
AC-3 and MPEG coded data is formatted in 16-bit words.
These words are expected at a sample rate (fs) of 48 kHz
and thus a minimum serial clock of 1.536 MHz; two 16-bit
words per word select period. If the transmission word
length is in excess of 16 bits all additional bits are
discarded.
A buffered version of this clock is available at pin 39
(SYSCLK). This can be optionally disabled or, a divided
version (4, 2 and 1) of the clock input at pin 42 (CLKI) can
be made available.
PCM sample lengths of up to 20-bit words are supported
with sample rates of 44.1 and 48 kHz. This mode is used
to transfer PCM and PCM with Dolby pro-logic encoded
data. Word select LOW corresponds to transmission of
data for the left channel, word select HIGH corresponds to
transmission of data for the right channel.
I2C-bus data/control clock
The I2C-bus control logic supports I2C-bus clock speeds
up to 400 kHz. This is supplied to pin 63 (SCL). If the
SAA2505H is in the stand-alone mode (pin 1 HIGH) no
I2C-bus clock needs to be supplied.
Pin 55 (SDBI) is reserved for a multi-channel extension to
the I2S-bus and is currently not supported.
Data sink clock
The data sink clock source is dependant on the mode of
operation of the I2S-bus output ports.
In the master mode the I2S-bus clock is derived form an
external 256 or 384fs source connected to pin 45 (ACLK).
This is internally divided and used to drive the serial clock
at pins 15 and 31 (SCK and SCKO3). To ensure that the
digital outputs poses good timing qualities (jitter and
wander) pin 45 should be a connected to a high quality
timing source.
1998 Mar 10
8
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
write
read
SCK
SD
MSB
MSB − 1
LSB + 1
LSB
first
WS
write
read
SCK
SD
MSB
MSB − 1
second
WS
MGL327
Fig.3 I2S-bus format (MSB fixed).
EIAJ FORMATTED INPUTS
In EIAJ mode ‘big-endian’ data is received LSB justified to the rising edge of word select output. Formatting of the data
is identical to that used in the I2S-bus mode.
SCK
write
read
SD
LSB + 1
LSB
first
first
WS
write read
SCK
SD
LSB + 1
LSB
second
WS
MGL328
Fig.4 EIAJ format (LSB justified).
9
1998 Mar 10
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
Data sources
SPDIF FORMATTED OUTPUT
I2S-BUS AND EIAJ FORMATTED OUTPUTS
The SPDIF output can transmit either coded data, as
received from the serial data input at pin 56 (SDI0), or
down-mixed 20-bit PCM stereo. The down-mixed stereo
may be Pro-logic encoded.
The device has four I2S-bus/EIAJ mode select outputs.
These outputs are capable of outputting data in EIAJ
20, 18 or 16-bit and I2S-bus modes. The EIAJ outputs are
capable of operating in single or double speed, the I2S-bus
output is capable of operating in single, double and quad
speed.
Together with the PCM samples additional control bits are
transmitted. These are the channel status, user data and
validity bits.
The first five bytes of the channel status bits are user
programmable, all following bytes are zeroed
automatically. Transmission is LSB first.
The output ports can either be in the slave or master mode.
In the slave mode they can either be slaved to the I2S-bus
serial clock input (pin 15) or to an external clock. In the
master mode an audio clock is applied to pin 45 that is
256 or 384fs. The master clocking scheme allows the
support of a 96 kHz sample rate DAC by use of the double
speed output option. The quad speed output option is
intended to allow multiple SAA2505H devices to be
connected together.
The user data can carry message lengths of 129 bytes.
These are transmitted over the SPDIF port at a rate of
2 bits per stereo sample. The message buffer of 129 bytes
is loaded via the I2C-bus, if no message is written the
SAA2505H outputs all zeros for the user data.
In order to obtain a high quality digital output in the master
mode the audio clock should be of high quality, having low
jitter and an even mark space ration.
Table 2 Output port timing information
AUDIO CLOCK
SAMPLING
FREQUENCY
WORD SELECT
SAMPLING
FREQUENCY
SERIAL CLOCK
SAMPLING
FREQUENCY
SERIAL DATA BEGIN
SAMPLING
MODE
Single
FREQUENCY
256 or 384fs
256 or 384fs
256fs
1fs
2fs
4fs
4fs
64fs
−
−
Double
Quad
Quad
128fs
256fs
192fs
1fs
1fs
384fs
When pin 1 is LOW a reset defaults the outputs to quiet,
however when pin 1 is HIGH a reset defaults the I2S-bus
output to active and the SPDIF output to mute. When pin 1
is HIGH some of the I2C-bus registers cannot be accessed
see Table 3.
Control Inputs
The SAA2505H can be operated in two stand-alone
modes or can be managed by the I2C-bus.
STAND-ALONE MODES
I2C-BUS REGISTER CONTROL
Two stand-alone modes exist to allow the device to be
used in systems without a microcontroller. These two
modes are STANDALONE (pin 1) held HIGH and
STANDALONE connected to RESET (pin 61).
The I2C-bus port supports 5 V, 400 kHz operation.
The details of the registers are given in Table 3.
1998 Mar 10
10
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Table 3 I2C-bus control register
DEFAULT VALUE
MEMORY
SECTION
General
REGISTER NAME
DESCRIPTION
ADDRESS
1(1)
2(2)
3(3)
SOFT_RESET
$8 000-b0
0
0
0
0: operation
1: reset
General
General
SYSCLCKEN
SYSCLKDIV
$8 000-b1
0
note 4
note 4
1
0: enable SYSCLK output
1: disable SYSCLK output
00: SYSCLK = 1⁄4CLK
$8 000-b3 and b2
00
10
01: SYSCLK = 1⁄2CLK
10: SYSCLK = CLK
11: reserved
General
General
General
General
General
General
EN_INP_INT_DSP1
$8 000-b4
0
0
0
0
0
0
note 4
note 4
note 4
note 4
note 4
note 4
1
0
1
0
0
0
0: disable input interrupts on DSP1
1: enable input interrupts on DSP1
0: disable output interrupts on DSP1
1: enable output interrupts on DSP1
0: disable input interrupts on DSP2
1: enable input interrupts on DSP2
0: disable output interrupts on DSP2
1: enable output interrupts on DSP2
0: ACLK = 256fs
EN_OUTP_INT_DSP1 $8 000-b5
EN_INP_INT_DSP1
$8 000-b6
EN_OUTP_INT_DSP1 $8 000-b7
ACLKSEL
$8 000-b8
$8 000-b9
1: ACLK = 384fs
MEMCONFIG
0: program memory on DSP1 = 12 kbytes
0: program memory on DSP2 = 8 kbytes
1: program memory on DSP1 = 8 kbytes
1: program memory on DSP2 = 12 kbytes
00: I2S-bus/EIAJ input format
01: reserved
I2SCONTROL IISMODE
$8 001-b1 and b0
00
note 4
00
10: reserved
11: reserved
I2SCONTROL IISINP
$8 001-b2
$8 001-b3
0
0
note 4
note 4
0
0
0: I2S-bus input format
1: EIAJ 16-bit input format
I2SCONTROL IISI_SDB_EN
0: SDBI is DSP1 Input flag
1: SDBI is aligned to WS to allow multi-channel I2S-bus input
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DEFAULT VALUE
MEMORY
SECTION
REGISTER NAME
DESCRIPTION
ADDRESS
1(1)
2(2)
3(3)
I2SCONTROL reserved
I2SCONTROL IISOUTMOD
$8 001-b4
0
note 4
note 4
0
reserved
$8 001-b6 and b5
00
00
00: I2S-bus format data output
01: EIAJ 16-bit format data output
10: EIAJ 18-bit format data output
11: EIAJ 20-bit format data output
0: I2S-bus outputs are slaves
1: I2S-bus outputs are masters
0: I2S-bus outputs 0 to 2 operate at normal speed
1: I2S-bus outputs 0 to 2 operate at double speed
00: I2S-bus output 3 operates at normal speed
01: I2S-bus output 3 operates at double speed
10: I2S-bus output 3 operates at quad speed
11: I2S-bus output 3 operates at normal speed
0: SDO0 output 3-stated
I2SCONTROL IISOUTMST
I2SCONTROL IISOUTSPD
I2SCONTROL IIS3OUTSPD
$8 001-b7
$8 001-b8
0
0
note 4
note 4
note 4
0
0
$8 001-b10 and b9 00
00
I2SCONTROL IISO0EN
I2SCONTROL IISO1EN
I2SCONTROL IISO2EN
I2SCONTROL IISO3EN
I2SCONTROL IIS3CLKEN
$8 001-b11
$8 001-b12
$8 001-b13
$8 001-b14
$8 001-b15
$8 002-b0
$8 002-b1
0
0
0
0
0
0
0
note 4
note 4
note 4
note 4
note 4
0
1
1
1
1
0
0
0
1: SDO0 output enabled
0: SDO1 output 3-stated
1: SDO1 output enabled
0: SDO2 output 3-stated
1: SDO2 output enabled
0: SDO3 output 3-stated
1: SDO3 output enabled
0: SCKO3, WSO3 and SDB outputs 3-stated
1: SCKO3, WSO3 and SDB outputs enabled
0: SPDIF validity bit = 0
SPDIF1
SPDIF1
SPDIFVAL
SPDIFBYP
1: SPDIF transmitting valid PCM
0: output PCM data from DSP1
1: output I2S-bus data from I2S-bus input
reserved
0
SPDIF1
SPDIF1
IISUBIT
$8 002-b2
$8 002-b3
0
0
0
0
0
0
SPDIFEN
0: 3-state SPDIF output and reset SPDIF block
1: enable SPDIF output
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DEFAULT VALUE
MEMORY
SECTION
REGISTER NAME
DESCRIPTION
ADDRESS
1(1)
2(2)
3(3)
Normal usage
SPDIF1
CSBYTE0
$8 002-b15 to b8
0000 0000
b8: consumer mode
b9: LPCM
b10: copy protection
b11 to b13: pre-emphasis
b14 to b15: mode
SPDIF2
SPDIF2
CSBYTE1
CSBYTE2
$8 003-b7 to b0
$8 003-b15 to b8
0000 0000
0000 0000
b0 to b7: category code
b8 to b11: source
b12 to b15: channel number
b0 to b3: source
SPDIF3
CSBYTE3
CSBYTE4
$8 003-b7 to b0
$8 003-b15 to b8
0000 0000
0000 0000
b4 to b6: clock accuracy
b0 to b3: word length
SPDIF3
Notes
1. STANDALONE held LOW.
2. STANDALONE held HIGH.
3. STANDALONE connected to RESET.
4. Controlled by DSP; no I2C-bus access.
All unused bits return a value of 0.
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
I2C-bus control and commands (pins 63 and 64)
START AND STOP CONDITIONS
Both data and clock line will remain HIGH when the bus in
not busy. A HIGH-to-LOW transition of the data line while
the clock is HIGH is defined as a STOP condition (P)
(see Fig.6).
INTRODUCTION
A general description of “The I2C-bus and how to use it”
can be obtained from Philips sales offices using ordering
number 9398 393 40011.
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as a START condition (S) (see Fig.6).
For the external control of the SAA2505H a fast I2C-bus is
implemented. This is a 400 kHz bus which is downward
compatible with the standard 100 kHz bus. There are two
different types of control instructions:
DATA TRANSFER
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’ (see Fig.7).
• Instructions to control the DSP program; programming
the coefficient RAM and reading the values of
parameters
• Instructions controlling source selection and
programmable parts; through the control registers as
detailed in Table 3.
ACKNOWLEDGE
The number of data bits transferred between the START
and STOP conditions from the transmitter to the receiver
is not limited. Each byte of 8 bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level left
on the bus by the transmitter whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to
pull-down the SDA line, left HIGH by the transmitter, during
the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related
clock pulse. Set-up and hold times must be taken into
account. A master receiver must signal an end-of-data to
the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the slave. In this
event the transmitter must leave the data line HIGH to
enable the master to generate a STOP condition
(see Fig.8).
The detailed description of the I2C-bus and commands is
given in the following sections.
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are the serial data
line (SDA) and the serial clock line (SCL). Both lines must
be connected to the supply rail via a pull-up resistor when
connected to the output stages of a microcontroller. For a
400 kHz I2C-bus, the recommendation from Philips
Semiconductors must be followed (e.g. up to loads of
200 pF on the bus a pull-up resistor can be used, between
200 and 400 pF a current source or switched resistor must
be used). Data transfer can only be initiated when the bus
is not busy.
BIT TRANSFER
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as control signals.
The maximum clock frequency is 400 kHz. To be able to
run at this high frequency all of the Inputs and outputs
connected to the bus must be designed for this high speed
I2C-bus according the Philips specification (see Fig.5).
STATE OF THE I2C-BUS INTERFACE DURING AND AFTER
POWER-ON RESET
During power-on reset the internal SDA line is kept HIGH
and the SDA pin is therefore high impedance. The SDA
line remains HIGH until a master pulls it down to initiate
communication.
1998 Mar 10
14
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBC621
Fig.5 Bit transfer on the I2C-bus.
SDA
SCL
SDA
SCL
S
P
STOP condition
START condition
MBC622
Fig.6 START and STOP conditions.
15
1998 Mar 10
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
SDA
MSB
acknowledgement
signal from receiver
acknowledgement
signal from receiver
byte complete,
interrupt within receiver
clock line held low while
interrupts are serviced
SCL
1
2
7
8
9
1
2
3 - 8
9
S
P
ACK
ACK
START
CONDITION
STOP
CONDITION
MBC601
Fig.7 Data transfer on the I2C-bus.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
8
SCL FROM
MASTER
1
2
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.8 Acknowledge on the I2C-bus.
16
1998 Mar 10
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
I2C-bus format
Table 5 I2C-bus write sequence
I2C-BUS MASTER
SAA2505H
ADDRESSING
Before any data is transmitted on the I2C-bus, the device
which should respond is addressed first. The addressing is
always done with the first byte transmitted after the start
procedure.
START
I2C-bus address of
SAA2505H
−
−
Write
−
−
acknowledge
SLAVE ADDRESS SELECTION (PIN 62)
Address high part
−
The SAA2505H acts as slave receiver or a slave
−
acknowledge
transmitter. Therefore the clock signal (SCL) is only an
input signal. The data signal (SDA) is a bidirectional line.
The SAA2505H slave addresses are shown in Table 4.
Address low part
−
−
acknowledge
Data high part
−
Table 4 I2C-bus address
−
acknowledge
I2C-BUS LEVEL
I2C-BUS ADDRESS
Data medium part
−
1
0
59H
58H
−
acknowledge
Data low part
−
−
acknowledge
The subaddress bit A0 corresponds to the hardware
address at pin 52 which allows the device to have
2 different addresses. This allows control of two DUET ICs
via the same I2C-bus.
Data high part
−
−
acknowledge
Data medium part
−
−
acknowledge
−
Data low part
WRITE AND READ CYCLES
−
acknowledge
The I2C-bus configuration for a write cycle is shown in
Table 5. The write cycle is used to write the bytes to
memory and control registers.
Continued exchanges
STOP Condition
−
The I2C-bus configuration for a read cycle is shown in
Table 6. The read cycle is used to read bytes from memory
and control registers.
1998 Mar 10
17
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
Table 6 I2C-bus read sequence
Table 7 SAA2505H I2C-bus address ranges
I2C-BUS MASTER
SAA2505H
START
$0
STOP
MEMORY BLOCK
START
I2C-bus address of
SAA2505H
−
−
$1FFF
$3FFF
$5FFF
$7FFF
$9FFF
DSP1 X memory
DSP1 Y memory
DSP2 X memory
DSP2 Y memory
control registers
$2000
$4000
$6000
$8000
Write
−
−
acknowledge
Address high part
−
Power supply connections and EMC
−
acknowledge
Address low part
−
The digital part of the chip has in total 13 positive supply
line connections and 13 ground connections. To minimise
radiation the device should be put on a double layer PCB
with, on one side, a large ground plane. The ground supply
lines should have a short connection to this ground plane.
The supply line connections should have minimum
−
acknowledge
START
I2C-bus address of
SAA2505H
−
−
Read
−
inter-pin PCB track impedances. A low reactance (Q)
ferrite bead/capacitor network in the positive supply line
can be used as a high frequency filter. Special attention
should be paid to the analog supply lines (VDDA and VSSA).
−
−
−
−
−
−
−
−
−
−
−
−
−
acknowledge
data high part
acknowledge
data medium part
acknowledge
data low part
acknowledge
data high part
acknowledge
data medium part
acknowledge
data low part
acknowledge
Boundary scan test interface
The SAA2505H has a 5 pin boundary scan test interface
which implements the three required commands of the
IEEE1149; BYPASS, SAMPLE and EXTEST.
The boundary scan test interface uses the following pins
TDI (pin 47), TMS (pin 48), TCK (pin 49), TRST (pin 50)
and TDO (pin 51). Naming and use of the pins is as per
IEEE recommendations.
Though TRST, TMS and TDI have internal pull-up
resistors there should also be system level pull-up
resistors.
Continued Exchanges
STOP Condition
−
All RAM and peripheral registers are mapped into a
common 16-bit address range. The data words are all
MSB padded to 24-bit, however, the on-chip RAM is 20-bit
and therefore the 4 MSBs are padded with zeros.
1998 Mar 10
18
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDDD
PARAMETER
CONDITIONS
MIN.
−0.3
MAX.
+3.3
UNIT
digital supply voltage
V
∆VDDD
voltage difference between two
supply voltage pins
−
330
mV
IIK
DC input clamp diode current
DC output clamp diode current
VI < −0.3 V or VI > VDDD + 0.3 V
−
−
±10
±10
mA
mA
IOK
output type 4 mA; VO < −0.3 V or
VO > VDDD + 0.3 V
IO
DC output source or sink current output type 4 mA;
−
−
±10
mA
mA
−0.3 V < VO < VDDD + 0.3 V
I
DDD ISSD DC current per supply pin
(VDDD or VSSD
operating ambient temperature
±500
)
Tamb
Tstg
0
70
°C
°C
mA
V
storage temperature range
latch-up protection
−55
100
−2000
−300
+125
−
LTCH
VESD
CIC specification/test method
electrostatic discharge sensitivity note 1
+2000
+300
for all pins
note 2
V
Notes
1. Human body model: equivalent to discharging a 100 pF capacitor through a 1500 Ω resistor.
2. Machine model: equivalent to discharging a 200 pF capacitor through a 0 Ω resistor.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient in free air
45
K/W
CHARACTERISTICS
Digital I/O at Tamb = 0 to 70 °C; VDDD = 3.0 to 3.6 V; unless otherwise specified.
SYMBOL
VDDD
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
digital supply voltage
3
3
3.3
3.3
3.6
3.6
V
V
VDDA
analog supply voltage for the
crystal oscillator
IDDD
digital supply current
fxtal = 41 MHz; maximum activity
of the DSP
−
tbf
tbf
tbf
tbf
tbf
tbf
mA
mA
W
IDD(xtal)
Ptot
supply current for the crystal
oscillator
fxtal = 41 MHz; functional mode
−
total power dissipation
fxtal = 41 MHz; maximum activity
of the DSP
−
Vhys
VIH
VIL
schmitt trigger hysteresis
HIGH-level input voltage
LOW-level input voltage
pin type SCHMITCD
0.4
−
−
−
0.7
−
V
V
V
Io = −3 mA; pin types A, B and C 2.0
VDDD = 3.0 V; Io = 3 mA;
pin types A, B and C
−
0.8
1998 Mar 10
19
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VOH
VOL
HIGH-level digital output voltage Io = −3 mA; pin types A, B and C 2.4
−
−
−
V
LOW-level digital output voltage VDDD = 3.0 V; Io = 3 mA;
pin types A, B and C
−
−
−
0.4
0.4
±5
V
VOL(I2C)
ILO(Z)
LOW-level digital output voltage Io = 8 mA; pin type D
and I2C-bus data output
−
−
V
output leakage current, 3-state
outputs
Vo = 0 or VDDD
;
µA
pin types A, B and C
Rpu(int)
Rpd(int)
internal pull-up resistor to VDDDX pin type B
−
−
76
76
−
−
kΩ
kΩ
internal pull-down resistor to
VSSDX
pin type A
ti(r)
ti(f)
to(r)
input rise time
input fall time
output rise time
VDDD = 3.6 V
VDDD = 3.6 V
−
−
−
tbf
tbf
−
3.6
3.6
3.0
ns
ns
ns
pin types E, F and G;
VDDD = 3.3 V; Tamb = 25 °C;
process = 0 σ; CL = 20 pF
to(f)
output fall time
pin types E, F and G;
−
−
3.5
ns
VDDD = 3.3 V; Tamb = 25 °C;
process = 0 σ; CL = 20 pF
Oscillator input/output
fxtal
Vxtal
gm
crystal frequency
40
3.0
10.5
3.6
−
40.5
3.3
19
−
MHz
V
voltage across the crystal
transconductance
3.6
32
38
1000
−
at start-up
mS
mS
fF
in operating range
−
CL(CLK)
capacitive load of clock output
500
1000
Tcy(STRTU) number of cycles in start-up time depends on quality of the
external crystal
−
cycles
1998 Mar 10
20
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
TIMING CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Serial digital inputs and outputs; (see Fig.9)
tr
rise time
Tcy = 50 ns
−
7.5
ns
tf
fall time
Tcy = 50 ns
−
7.5
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Tcy
bit clock cycle time
bit clock time HIGH
bit clock time LOW
data set-up time host
data set-up time I2S-bus input
data hold time host
data hold time I2S-bus input
70
17.5
17.5
320
10
50
10
100
100
−
tBCK(H)
tBCK(L)
ts;DAT
ts;DAT
th;DAT
th;DAT
ts;WS
th;WS
td;DAT
td;WS
Tcy = 50 ns
Tcy = 50 ns
Tcy = 50 ns
−
−
−
−
Tcy = 50 ns
−
−
word select set-up time I2S-bus input Tcy = 50 ns
word select hold time I2S-bus input
−
Tcy = 50 ns
−
data delay time host
20
15
word select delay time host
−
I2C-bus timing; (see Fig.10)
fSCL
tBUF
SCL clock frequency
0
400
kHz
bus free between a STOP and
START condition
1.3
−
µs
tHD;STA
hold time (repeated) start condition;
after this period the first clock pulse is
generated
0.6
−
µs
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
1.3
0.6
0.6
−
−
−
µs
µs
µs
tHIGH
tSU;STA
set-up time for a repeated start
condition
tHD;DAT
tSU;DAT
data hold time
0
0.9
µs
data set-up time
for standard mode I2C-bus 100
system tSU;DAT > 250 ns
−
ns
(1)
(1)
(1)
tr
rise time of both SDA and SCL
signals
fSCL = 400 kHz
fSCL = 100 kHz
20 + 0.1Cbus
300
1000
300
−
ns
ns
ns
µs
pF
ns
20 + 0.1Cbus
tf
fall time of both SDA and SCL signals
set-up time for STOP condition
capacitive load for each bus line
20 + 0.1Cbus
tSU;STO
CL(bus)
tSP
0.6
−
400
50
pulse width of spikes which must be fSCL = 400 kHz
suppressed by the input filter
0
Note
1. Cbus = bus line capacitance in pF.
1998 Mar 10
21
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
WS
OUTPUT
LEFT
WS
INPUT
RIGHT
t
t
t
s;WS
t
t
d;WS
h;WS
BCK(H)
BCK(L)
t
t
t
d;DAT
r
f
BCK
t
t
h;DAT
T
s;DAT
cy
DATA
INPUT
LSB
MSB
DATA
OUTPUT
MGL326
Fig.9 Timing definitions of the serial digital data inputs and outputs.
1998 Mar 10
22
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SDA
t
t
t
t
t
t
SP
r
BUF
LOW
HD;STA
f
SCL
t
t
SU;STO
HD;STA
t
t
t
t
SU;DAT
SU;STA
HD;DAT
HIGH
P
S
P
Sr
MBC611
ahdnbok,uflapegwidt
Fig.10 Timing definition of the I2C-bus.
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ahdnbok,uflapegwidt
SYSCLK
SYSCLK
SCK
WS
DAC
L/R
SCK
WS
SD
SPDIF
SD
SYSCLK
DAC
SCK
WS
LS/RS
SD
EFO1 to EFO6
SCKI
EFI1 to EFI3
TDI
TDO TMS TCK
SYSCLK
SCK
WS
ACLK
SCKO
WSO
WSI
ADC
SYSCLK
SCK
WS
SDI0
DAC
SD
SDI1
SDO0
SDO1
SDO2
SCKO3
WSO3
SDO3
SDBO3
SPDIF
SDBI
C/LFE
SD
SCL
SAA2505H
SDA
ADDR
STANDALONE
SYSCLK
SCK
SYSCLK
DAC
SCK
WS
SD
LC/RC
SDB
CLKO
V
V
V
V
SSDA
RESET
TRST CLKI
SSD
DDD
DDDA
40.5
MHz
47 nF
75 Ω
SCL
SDA
3 : 1
2
I C-bus from
SPDIF
microcontroller
47 µF
0.1 µF
3.3 µH
1 µF
4.7 kΩ
15
pF
15
pF
0.1 µF
10 nF
+3.3 V
MGL325
Fig.11 Application diagram for SAA2505H.
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
PACKAGE OUTLINE
QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm
SOT393-1
y
X
A
48
33
32
49
Z
E
e
A
2
H
A
E
(A )
3
E
A
1
θ
w M
p
L
p
b
pin 1 index
L
17
64
detail X
16
1
w M
v
M
A
b
p
Z
e
D
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.25 2.75
0.10 2.55
0.45 0.23 14.1 14.1
0.30 0.13 13.9 13.9
17.45 17.45
16.95 16.95
1.03
0.73
1.2
0.8
1.2
0.8
mm
3.00
0.25
0.8
1.60
0.16 0.16 0.10
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
96-05-21
97-08-04
SOT393-1
MS-022
1998 Mar 10
25
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Reflow soldering
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering techniques are suitable for all QFP
packages.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
Wave soldering
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
CAUTION
Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.
1998 Mar 10
26
Philips Semiconductors
Preliminary specification
Digital multi-channel audio IC (DUET)
SAA2505H
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Mar 10
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Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545102/1200/01/pp28
Date of release: 1998 Mar 10
Document order number: 9397 750 02979
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