SAA2510 [NXP]
Video CD VCD decoder; 视频CD，VCD解码器
| 型号： | SAA2510 |
| 厂家： | 
NXP |
| 描述： | Video CD VCD decoder |
| 文件： | 总28页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA2510
Video CD (VCD) decoder
1996 May 21
Preliminary specification
File under Integrated Circuits, IC02
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
FEATURES
(With standard microcode loaded)
• Decoding and display of MPEG1 video streams
(constrained parameters)
• Decoding of MPEG audio streams (layer II)
• Decoding, storage (compressed) and display of
high-resolution still pictures of 704 × 576 pixels
• EBU audio output, fully transparent from input to output
in CD-DA mode and generated in MPEG mode
• Requires only 4 Mbits of external 70 ns DRAM
• Audio transparency mode for CD-DA discs
• On-screen display capability
• Play options:
• Downloadable microcode for internal controllers
• Internal video timing generator
• Requires 40 MHz crystal for system clock generation
• Requires 27 MHz crystal or external 27 MHz source for
video timing generation
– Play
– Stop
• Requires 16.9344 MHz (384 × 44.1 kHz) clock locked to
CD drive
– Pause/continue
– Slow-motion forward
– Scan forward
• Internal generation of 90 kHz MPEG clock
• Capability of sharing external DRAM by 3-stating all
DRAM pins.
– Scan backward.
• Supports auto-pause feature
• Disc interface: Philips I2S, EIAJ, MEC formats and
APPLICATION
IEC 958 (EBU) interface
• Dedicated video CD players.
• Separate error flag input (EFIN) and data valid input
(NDAV)
GENERAL DESCRIPTION
• Performs basic block decoder functions:
– serial-to-parallel conversion
– sync detection
MPEG1 audio and video CD (VCD) decoder, intended for
use in low-cost dedicated video CD players. When used
with a 4 Mbit DRAM and a digital video encoder, the
decoder adds the required functionality to a CD decoder to
implement a low-cost video CD player capable of playing
discs coded to version 2.0 of the video CD specification.
The SAA2510 is an I2C-bus controlled chip and features
serial data input in four common bus formats. It provides
digital video output in CCIR601 and 656 formats.
– descrambling
– EDC calculation
– error-correction for mode 2 form 1 sectors
– header and sub-header interpretation.
• I2C-bus interface
A bit-mapped on-screen display is provided and output
video timing can be 525 lines/30 frames per second or
625 lines/25 frames per second. The chip is microcode
programmable for feature enhancement.
• Video output YUV 4 : 2 : 2 format. DMSD bus
compatible
• Also supports CCIR656 video interface, including line
and field timing codes
• Audio output: 44.1 kHz. 16, 18 or 20 bits per audio
sample in Philips I2S, Sony or MEC formats
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
SAA2510
QFP100
plastic quad flat package; 100 leads (lead length 1.95 mm);
SOT317-1
body 14 × 20 × 2.7 mm; high stand-off height
1996 May 21
2
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
3.6
UNIT
VDD3
VDD5
IDD
supply voltage
3.0
4.5
−
3.3
5.0
tbf
V
V
supply voltage
5.5
−
supply current
mA
fxtal s
fxtal v
fi
system clock crystal frequency
video clock crystal frequency
audio clock input frequency
operating ambient temperature
−
40.0
27.0
16.9344
−
−
MHz
MHz
MHz
°C
−
−
−
−
Tamb
−20
+70
1996 May 21
3
g
PLAY
CONTROL
BUFFER
OSD
BUFFER
VIDEO
BUFFER
0
VIDEO
BUFFER
1
VIDEO
BUFFER
2
EXTERNAL
4 Mbit DRAM
AUDIO
FIFO
VIDEO
FIFO
3 k
7 k
W
CAS
A0 to A8
Sys_osc_1
76
Sys_osc_0
74
RESET
27
CDIR
DR0 to DR15
RAS
79
84
86
82
80
Vid_osc_0
Vid_osc_1
CLK27
MEMORY MANAGEMENT UNIT
SYSTEM CLOCK
VIDEO
CLOCK
CREF
EBUIN
AUDIOCLK
WSIN
CLIN
EFIN
DAIN
BLOCK
DECODER
VIDEO DECODER
7 to 1
100
8
8
UV0 to UV7
Y0 to Y7
VSYNC
HREF
95 to 88
SYSTEM
CONTROLLER
99
97
11
9
FRAME
DATA
SORTER
VIDEO
GENERATOR
IDCT
RECON-
NDAV
SDA
SCL
STRUCTOR
HOST
TLSAND
CSYNC
2
I C
INTERFACE
INT
ASEL
12
13
16
14
SAA2510
EBUOUT
DAOUT
CLOUT
WSOUT
AUDIO DECODER
TEST CONTROL
77
TP1
78
TP2
28
MGE325
DRAMON
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
PINNING
SYMBOL
UV6
PIN
DESCRIPTION
1
video UV bus output bit 6;
16-bit video output mode: the UV bus outputs alternating U and V chroma samples
at 13.5 Mbytes/s
CCIR656 mode: this bus is not used (inactive)
video UV bus bit 5
UV5
2
3
UV4
video UV bus bit 4
UV3
4
video UV bus bit 3
UV2
5
video UV bus bit 2
UV1
6
video UV bus bit 1
UV0
7
video UV bus bit 0
VDD5
CSYNC
VSS5
8
5 V external pad power supply
composite sync output; 525 lines/60 Hz or 625 lines/50 Hz
0 V external pad power supply
9
10
11
TLSAND
two-level Sandcastle (composite blanking) output; requires external resistor network
to define horizontal/vertical blanking level
EBUOUT
DAOUT
WSOUT
VDD3
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
IEC 958 digital audio output
I2S data; digital audio output
I2S word select digital audio output
+3 V internal power supply
CLOUT
VSS
I2S bit clock output
0 V internal power supply
AUDIOCLK
VDD5
16.9 MHz audio clock input
5 V internal power supply
EBUIN
CLIN
EBU (IEC 958) input
I2S bit clock input
I2S word select input
I2S digital data input
WSIN
DAIN
VDD3
+3 V internal power supply
error flag input from I2S source
EFIN
VSS
0 V internal power supply
RESET
DRAMON
INT
active low reset input
DRAM pin 3-state control input; also 3-states video outputs and some timing signals
active low open drain interrupt request to host microcontroller
data not valid input (data on I2S or EBU input not valid)
I2C-bus address select pin
NDAV
ASEL
SDA
I2C-bus data pin
VDD5
5 V external pad power supply
I2C-bus clock input
SCL
VSS5
0 V external pad power supply
DRAM data input/output bit 5
DR15
1996 May 21
5
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
SYMBOL
DR14
PIN
DESCRIPTION
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
DRAM data input/output bit 14
DRAM data input/output bit 13
DRAM data input/output bit 12
DRAM data input/output bit 11
DRAM data input/output bit 10
DRAM data input/output bit 9
5 V external pad power supply
DRAM data input/output bit 8
0 V external pad power supply
DRAM data input/output bit 7
DRAM data input/output bit 6
DRAM data input/output bit 5
DRAM data input/output bit 4
DRAM data input/output bit 3
DRAM data input/output bit 2
DRAM data input/output bit 1
DRAM data input/output bit 0
0 V external pad power supply
DRAM column address strobe
5 V external pad power supply
DRAM row/column address pin A8
DRAM row/column address pin A7
DRAM row/column address pin A6
DRAM row/column address pin A5
DRAM row/column address pin A4
+3 V internal power supply
DR13
DR12
DR11
DR10
DR9
VDD5
DR8
VSS5
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
VSS5
CAS
VDD5
A8
A7
A6
A5
A4
VDD3
W
active low DRAM write strobe
0 V internal power supply
VSS
RAS
VDD5
A3
DRAM row address strobe
5 V internal power supply
DRAM row/column address pin A3
0 V external pad power supply
DRAM row/column address pin A2
5 V external pad power supply
DRAM row/column address pin A1
DRAM row/column address pin A0
VSS5
A2
VDD5
A1
A0
VDDO3
Sys_osc_0
VSS
3 V internal power supply for oscillator
oscillator input pin; 40 MHz oscillator
0 V internal power supply
Sys_osc_1
TP1
oscillator output pin; 40 MHz oscillator
factory test pin; connect to ground
1996 May 21
6
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
SYMBOL
TP2
PIN
DESCRIPTION
78
79
80
factory test pin; connect to ground
clock direction control pin; when high, CLK27 is an output
CDIR
CREF
clock qualifier output; 13.5 MHz timing signal used in 16-bit video output mode; can
also be used as 13.5 MHz video sample clock
VSS5
81
82
83
84
85
86
87
88
0 V external pad power supply
CLK27
VDD5
27 MHz clock input or output; direction controlled by CDIR pin
5 V external pad power supply
Vid_osc_0
VSS
oscillator pin; 27 MHz; input pin
0 V internal power supply
Vid_osc_1
VDDO3
Y7
oscillator pin; 27 MHz; output pin
3 V internal power supply for oscillator
video Y bus output bit 7
DMSD mode: the Y bus outputs luminance samples at 13.5 Mbytes/s
CCIR656 mode: this pin supplies multiplexed chrominance and luminance
(27 Mbytes/s)
Y6
89
90
91
92
93
94
95
96
97
video Y bus bit 6
Y5
video Y bus bit 5
Y4
video Y bus bit 4
Y3
video Y bus bit 3
Y2
video Y bus bit 2
Y1
video Y bus bit 1
Y0
video Y bus bit 0
VSS5
HREF
0 V external pad power supply
horizontal (line) timing reference signal; high during active video part of line, low
during line blanking
VDD5
98
99
5 V external pad power supply
VSYNC
vertical (field/frame) timing reference signal; high during vertical blanking interval of
field
UV7
100
video UV bus output bit 7
DMSD mode: the UV bus outputs alternating U and V chroma samples at
13.5 Mbytes/s
CCIR656 mode: this bus is not used (inactive)
1996 May 21
7
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
1
2
UV6
UV5
UV4
UV3
UV2
UV1
UV0
80 CREF
79 CDIR
78 TP2
3
4
TP1
76 Sys_osc_1
77
5
V
6
75
74
73
SS
7
Sys_osc_0
V
8
V
DDO3
DD5
9
CSYNC
72 A0
71 A1
V
10
11
12
13
SS5
TLSAND
EBUOUT
DAOUT
V
DD5
70
69
68
A2
V
SS5
WSOUT 14
67 A3
V
V
15
16
17
66
65
64
63
62
61
DD3
DD5
SAA2510
CLOUT
RAS
V
V
SS
SS
AUDIOCLK 18
W
V
V
19
20
DD3
DD5
EBUIN
A4
CLIN 21
WSIN 22
DAIN 23
60 A5
59 A6
A7
A8
V
58
57
56
V
24
EFIN 25
DD3
DD5
V
26
27
55 CAS
V
SS
RESET
54
53
52
SS5
DRAMON 28
INT
NDAV 30
DR0
DR1
29
51 DR2
MGE324
Fig.2 Pin configuration.
1996 May 21
8
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
The OSD is implemented as 48 vertical ‘slices’ of 8 pixels
(horizontally) and 32 (vertically). Each pixel is stored as
2 bits. This gives three programmable logical colours, plus
a transparent option. Each slice is identified by a slice code
(slice number).
FUNCTIONAL DESCRIPTION
Block decoder
The VCD chip receives MPEG A/V or CD digital audio data
from a CD decoder chipset using any one of four common
interface formats (Philips I2S, EIAJ, MEC or IEC 958). The
Philips I2S, EIAJ and Matsushita input modes use the bit
clock (CLIN), word select (WSIN), data (DAIN) and error
flag (EFIN) inputs. If IEC 958 (EBU) input mode is
selected, only the EBUIN pin needs to be connected. The
chip also requires a 16.9 MHz clock input (CLIN) which is
synchronous with the data input from the CD decoder
providing the serial data input.
The horizontal position of a slice is defined by its position
in a slice code sequence written to the VCD chip. This
arrangement reduces the need to completely update the
OSD bit map in many situations. It may be possible to
simply reorder the slices, e.g. if a track time display is
being updated and slices are prepared to represent digits.
At any time, up to 44 of the 48 slices can be displayed.
Video decoder
The VCD chip contains a block decoder and descrambler
which performs error correction on the Video CD data track
(form 1) sectors and error detection on real-time audio and
video tracks where an error correction code is present.
Video output data can be presented in one of two modes:
1. 16-bit wide data is output in YUV 4 : 2 : 2 format as
8 bits of luminance and 8 bits of alternating U and
V chrominance. The video output data rate in this
mode is 13.5 Mwords/s.
In most events, audio output can be in any of the three
(I2S, EIAJ or MEC) formats, independent of input type.
When playing CD digital audio discs, the input is copied to
the outputs.
2. 8-bit wide, CCIR656-like, data is output providing
4 : 2 : 2 format video as an 8-bit UYVY multiplex at
27 Mbytes/s.
The block decoder supports some special functions which
enable recovery of play control lists. The desired sectors
can be acquired by programming a sector address via the
I2C-bus microcontroller interface. The microcontroller then
instructs the CD servo/decoder subsystem to execute a
servo jump to the required disc location and then waits for
an interrupt indicating that the desired sector information
has been received and error-corrected.
In either case, the VCD chip can be programmed to output
525 line or 625 line format timing to match the type of
display (TV) connected to its output. Additional
programmability is provided to cope with the Video CD disc
source picture coding type (525/625 lines).
The VCD chip performs vertical and horizontal
interpolation to convert the MPEG SIF (352 pixels per line)
normal resolution pictures to CCIR601 resolution.
Vertically interpolated pixels are output on the odd fields
during display of normal resolution pictures.
System controller
Overall control of the chip and a number of its less
time-critical functions is carried out by a dedicated
RISC processor. The microcode for this processor is
executed from an on-chip RAM. This microcode must be
loaded into RAM after power-up by the host
microcontroller, using the I2C-bus interface. This enables
the functionality of the chip to be customized for specific
applications.
The Video CD disc being played may have been coded
with 525 lines/60 Hz or 625 lines/50 Hz pictures. When the
Video CD player is connected to a display with a different
timebase to the coded disc material, some adjustments
must be made to allow for the different number of lines on
the display and the reconstructed picture. Two examples
are shown in Figs. 3 and 4.
On-screen display
The VCD chip can be programmed to position the
reconstructed picture with respect to horizontal and
vertical syncs anywhere on the display screen with a
programmable ‘viewport’ position. Figure 3 shows an
MPEG SIF resolution picture (352 pixels by 288 lines)
being displayed on an NTSC display having only
240 active display lines per field. In this event, the top and
bottom 24 lines are not displayed.
The VCD chip provides a bit-mapped On-Screen-Display
(OSD), containing 32 display lines of 352 pixels per line.
There is a double-height mode which repeats OSD lines so
that the maximum height of OSD objects becomes
64 lines. This character-set-independent OSD permits
display of ideographic characters and simple graphic
displays anywhere on the screen.
1996 May 21
9
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
The second example, illustrated in Fig.4, is where a
240 active lines per field NTSC picture needs to be
displayed on a 288 line PAL format display. The ‘missing’
lines can be filled with a programmable border colour.
In this event, the horizontal and vertical resolution of the
reconstructed picture is double that of normal resolution
(moving) pictures. In order to fit the picture in the available
frame buffer DRAM, a data compression scheme is
applied to the stored picture.
High-resolution still pictures can be present on a Video CD
disc.
reconstructed picture
352
display window
handbook, halfpage
handbook, halfpage
24
352
not displayed
border = blank
reconstructed picture
window
viewport
240 288
240 288
not displayed
24
border = blank
MGE332
MGE333
Fig.3 One field of a 625-line picture on a 525-line
display.
Fig.4 525-line picture on a 625-line display.
1996 May 21
10
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
to read data stored in three play-control sector buffers,
which normally will be used to store Video CD data track
information. This interface features a two or three byte
sub-addressing scheme allowing access to any DRAM
location. However, in normal use, only two byte
sub-addressing is needed.
‘Trickmode’ implementation
Compared with CD digital audio players, it is likely that
Video CD players will need to offer additional functionality
similar to VCRs. These features are commonly called
‘trickmodes’. Typically, the player will offer features such
as still picture (freeze frame), scan forwards and
backwards as well as slow motion replay.
An interrupt pin is available to signal a number of events
so that the controlling processor does not need to poll VCD
status registers.
These features require a combination of CD servo control
and Video CD decoder functions for effective
Input pin NDAV is used to signal that data on the block
decoder input is not valid, e.g. during CD servo jumps.
implementation. The VCD chip provides high level
command features to support these modes in order to
minimize microcontroller time-critical software.
A complete memory map and list of registers will be
included in a later version of this data sheet.
STILL PICTURE DISPLAY
I2C-bus slave address selection
This is implemented directly using a Pause command,
causing the VCD chip to hold the displayed picture at the
next frame update.
A6
0
A5
0
A4
1
A3
1
A2
0
A1
1
A0
A0(1)
R/W
SCAN FORWARD AND SCAN BACKWARDS
Note
There is no difference as far as the VCD chip is concerned.
The controlling microcomputer must command the CD
servo to execute a servo jump and re-synchronize. The
VCD chip is then commanded to display the next I
(Intra-coded) picture following re-acquisition of sector
sync.
1. ASEL.
The data transfer protocol is as follows:
Two and three byte sub-addressing: first the device
sub-address is transmitted, preceded by a START
condition and the slave address:
SLOW-MOTION REPLAY
Two and three byte sub-addressing
A command is provided by the VCD chip, allowing a
slow-motion ‘factor’ in the range 2 to 8 to be selected. This
is the factor by which replay will be slowed down. Because
the rate of decoding of video sectors has been reduced,
the video FIFO fills up. The block decoder is designed to
automatically disable acquisition when the video FIFO fills
in this way and an interrupt is generated. At this point, the
next wanted sector (address) has been loaded into a
register in the VCD chip. The controlling microcomputer
then commands a CD servo jump to position on the disc
just before the next desired sector, making allowance for
re-synchronization by the servo and VCD chip.
S
SLA
S = START
W
SUB_A
SLA = Slave address
W = Write
SUB_A = Sub-address
The sub-address can be either 2 or 3 bytes. The 3-byte
sub-address is used for DRAM random access. This is not
used for normal operation. It exists only as a test mode.
Since the Video CD IC is internally fully word (16 bits)
oriented, the sub-address must always be an even
address. If an odd-numbered address is given, the Video
CD IC will not acknowledge this byte. For the sub-address,
the least significant byte is sent first. The second
sub-address byte contains 2 control bits.
I2C-bus interface
The VCD chip is programmed via the I2C-bus interface.
The chip is a slave transceiver capable of operating at the
maximum specified bus clock frequency of 400 kHz. It
does not support the general call feature. One of two slave
addresses can be used. The address is selected by the
ASEL input pin.
This bus provides access to the internal registers of the
device. The bus is also used to write OSD slice data and
1996 May 21
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Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
Sub-address byte format
MSB
LSB MSB
A0 C1
LSB
A7
A6
A5
A4
A3
A2
A1
C0
A13
A12
A11
A10
A9
A8
I2C-bus transaction summary
When A0 is a ‘1’, the address byte is not acknowledged
(odd address).
The following notation is used to describe bus
transactions:
Explanation of control bits
S: START condition generated by bus master
P: STOP condition generated by bus master
C0 = 0; 2-byte sub-address.
C0 = 1; 3-byte sub-address. The next byte transmitted is
also an address byte:
A: Acknowledge bit generated by master or slave
according to transaction type and stage
N: Negative acknowledge; acknowledge bit is not set by
bus master during last byte of a read
3-byte sub-address - most significant byte format
MSB
0
LSB
SLA: 7-bit slave address generated by bus master
W: R/W bit after slave address is set to write
R: R/W bit after slave address is set to read
0
0
A18 A17 A16 A15 A14
C1 = 0; sub-address post increment enabled. After each
transfer of 2 bytes, the address is automatically
incremented by 2.
SUB_N: Sub-address byte N (N = 0, 1 or 2); least
significant address byte is SUB_0
D(M): A data byte transmitted by master or slave on the
bus; D(0) is the first byte sent; as all transfers must be
an even number of bytes, it follows that M must be odd.
C1 = 1; sub-address post increment disabled.
The master will terminate a read action by NOT
acknowledging the last read byte followed by a STOP
condition.
Set 2-byte sub-address and write (M + 1) bytes
S
SLA
W
A
SUB_0
A
SUB_1
A
D(0)
R
A
D(0)
D(1)
A to D(M)
A
P
Set 2-byte sub-address and read (M + 1) bytes
SLA SUB_0 A SUB_1 A
S
W
A
S
SLA
A
D(1) A to D(M)
N
P
Set 3-byte sub-address and write (M + 1) bytes
SLA SUB_0 A SUB_1 A SUB_2
S
W
A
A
D(0) A
D(1)
A to D(M)
A
P
Set 3-byte sub-address and read (M + 1) bytes
S SLA SUB_0 A SUB_1 A SUB_2
W
A
A
S
SLA
R
A D(0)
A
D(1) A to D(M)
N
P
This addressing mode is valid only if sub-address auto incrementing is disabled. It is intended for fast polling of a status
register.
1996 May 21
12
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
Byte-order within words
LSB
MSB
Word
I2C-bus B7
B15 B14 B13 B12 B11 B10 B9
B8
B0
B7
B6
B5
B4
B3
B2
B1
B0
B8
B6
B5
B4
B3
B2
B1
B15 B14 B13 B12 B11 B10 B9
For each transmitted word (read or written) the least significant byte is transmitted first.
CHARACTERISTICS
Tamb = −20 to +70 °C; VDD5 = 4.5 to 5.5 V; VDD3 = 3.0 to 3.6 V; unless otherwise specified.
SYMBOL
Supplies
VDD5
IDD5
VDD3
IDD3
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
supply voltage (5 V) range
VDD5 supply current
4.5
5
5.5
V
−
3
−
−
tbf
3.3
tbf
tbf
tbf
3.6
tbf
tbf
mA
V
supply voltage (3 V) range
VDD3 supply current
mA
mA
IDD(tot)
total supply current
Digital inputs
ALL INPUTS (EXCEPT RESET AND OSCILLATOR INPUTS)
VIL
VIH
ILI
LOW level input voltage
HIGH level input voltage
input leakage current
input capacitance
−0.3
2
−
−
−
−
+0.8
V
VDD + 0.5 V
Vi = 0 to VDD
−10
−
+10
10
µA
Ci
pF
RESET INPUT: (SCHMITT INPUT)
VIL
VIH
ILI
LOW level input voltage
−0.3
3.5
−10
1
+2
V
HIGH level input voltage
input leakage current
VDD + 0.5 V
Vi = 0 to VDD
+10
−
µA
Vhys
hysteresis voltage
−
V
(VIH − VIL)
Inputs/outputs
SDA AND SCL (I2C-BUS DATA AND CLOCK)
VIL
VIH
ILI
LOW level input voltage
HIGH level input voltage
input leakage current
input capacitance
−0.5
3
−
−
−
−
−
−
−
+1.5
V
VDD + 0.5 V
Vi = 0 to VDD
−10
−
+10
10
µA
pF
pF
V
Ci
CL
load capacitance
−
400
0.4
0.6
VOL
VOL
LOW level output voltage (IOL = 3.0 mA)
LOW level output voltage (IOL = 6.0 mA)
0
0
V
CLK27
VIL
LOW level input voltage
HIGH level input voltage
−0.3
−
−
+0.8
V
VIH
2.4
VDD + 0.5 V
1996 May 21
13
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
SYMBOL
PARAMETER
CONDITIONS
Vi = 0 to VDD
MIN.
−10
TYP.
MAX.
+10
UNIT
µA
ILI
Ci
input leakage current
input capacitance
−
−
−
−
−
−
−
10
0.4
VDD
4
pF
V
VOL
VOH
tr
LOW level output voltage (IOL = 1.6 mA)
0
HIGH level output voltage (IOH = −0.2 mA)
2.6
−
V
input rise time
input fall time
0.6 to 2.6 V
0.6 to 2.6 V
ns
ns
tf
−
4
DR15 TO DR0 (DRAM DATA I/O)
VIL
VIH
ILI
LOW level input voltage
−0.3
2
−
−
−
−
−
−
−
−
−
+0.8
V
HIGH level input voltage
input leakage current
input capacitance
VDD + 0.5 V
Vi = 0 to VDD
−10
−
+10
10
µA
pF
pF
V
Ci
CL
VOL
VOH
tr
load capacitance
−
30
LOW level output voltage (IOL = 1.6 mA)
0
0.4
VDD
10
HIGH level output voltage (IOH = −0.2 mA)
2.4
3
V
output rise time
output fall time
0.6 to 2.6 V; load = CL
0.6 to 2.6 V; load = CL
ns
ns
tf
3
10
Outputs
RAS, CAS, W, A0 TO A8 (DRAM CONTROL AND ADDRESS LINES)
VOL
VOH
CL
tr
LOW level output voltage (IOL = 1.6 mA)
HIGH level output voltage (IOH = −0.2 mA)
load capacitance
0
−
−
−
−
−
0.4
VDD
30
V
2.4
V
pF
ns
ns
output rise time
output fall time
0.6 to 2.2 V; load = CL
0.6 to 2.2 V; load = CL
3
3
10
tf
10
Y0 TO Y7 (VIDEO OUTPUT Y BUS)
VOL
VOH
CL
tr
LOW level output voltage (IOL = 1.6 mA)
HIGH level output voltage (IOH = −0.2 mA)
0
−
−
−
−
−
0.4
VDD
30
4
V
2.4
−
V
load capacitance
output rise time
output fall time
pF
ns
ns
0.6 to 2.6 V; load = CL
0.6 to 2.6 V; load = CL
−
tf
−
4
UV0 TO UV7 (VIDEO OUTPUT UV BUS)
VOL
VOH
CL
tr
LOW level output voltage (IOL = 1.6 mA)
HIGH level output voltage (IOH = -0.2 mA)
0
−
−
−
−
−
0.4
VDD
30
V
2.4
−
V
load capacitance
output rise time
output fall time
pF
ns
ns
0.6 to 2.2 V; load = CL
0.6 to 2.2 V; load = CL
−
10
tf
3
10
INT (OPEN DRAIN; INTERRUPT)
VOL
CL
tr
LOW level output voltage (IOL = 1.6 mA)
0
−
−
−
−
−
0.4
30
10
V
load capacitance
output rise time
pF
ns
0.6 to 2.2 V; load = CL
14
1996 May 21
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
SYMBOL
PARAMETER
output fall time
EBUOUT (IEC 958 OUT)
CONDITIONS
MIN.
TYP.
MAX.
10
UNIT
ns
tf
0.6 to 2.2 V; load = CL
−
−
VOL
VOH
CL
LOW level output voltage (IOL = 10 mA)
HIGH level output voltage (IOH = −10 mA)
load capacitance
0
V
−
−
−
−
−
−
1
V
DD5−1
VDD
50
10
V
pF
ns
tr
output rise time
0.8 V to (VDD5 − 0.8 V);
load = CL
tr
output fall time
0.8 V to (VDD5 − 0.8 V);
−
−
10
ns
load = CL
ALL OTHER INPUTS
VOL
VOH
CL
tr
LOW level output voltage (IOL = 1.6 mA)
HIGH level output voltage (IOH = −0.2 mA)
load capacitance
0
−
−
−
−
−
0.4
VDD
50
V
2.4
−
V
pF
ns
ns
output rise time
output fall time
0.6 to 2.6 V; load = CL
0.6 to 2.6 V; load = CL
−
30
tf
−
30
I2S input/output timing; (Fig.5)
INPUT TIMING
fclk
input clock frequency
−
2.118
−
−
−
−
MHz
ns
tclkH
tclkL
tsu
input clock HIGH period
input clock LOW period
166
166
95
−
−
−
ns
set-up time (DAIN, EFIN,
WSIN)
ns
th1
hold time DAIN, EFIN,
WSIN)
0
−
−
ns
OUTPUT TIMING
fclk
output clock frequency
−
2.118
−
−
−
MHz
ns
tclkH
th2
output clock HIGH period
166
195
−
−
hold time (DAOUT,
WSOUT)
ns
td
output delay time (DAOUT,
WSOUT)
−
−
147
ns
I2C-bus input/output timing (Fig.6)
100 kHz CLOCK FREQUENCY
fclk
clock frequency
clock LOW period
period
0
−
−
−
−
−
−
100
−
kHz
µs
µs
ns
tLOW
4.7
4
tHIGH
−
tSU;DAT
tHD;DAT
tSU;STO
data set-up time
data hold time
250
0
−
−
ns
set-up time clock HIGH to
STOP
4.7
−
µs
1996 May 21
15
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
SYMBOL
tBUF
PARAMETER
CONDITIONS
MIN.
4.7
TYP.
MAX.
UNIT
µs
set-up time STOP to
START
−
−
tHD;STA
tSU;STA
START hold time
4
−
−
−
−
µs
µs
set-up time clock rising
edge to START
4.7
tr
tf
rise time (SDA and SCL)
fall time (SDA and SCL)
VILmin to VIHmax
50
50
−
−
1000
300
ns
ns
VILmin to VIHmax
400 kHz CLOCK FREQUENCY
fclk
clock frequency
0
−
−
−
−
−
−
400
−
kHz
µs
µs
ns
tLOW
clock LOW period
period
1.3
0.6
100
0
tHIGH
−
tSU;DAT
tHD;DAT
tSU;STO
data set-up time
data hold time
−
−
ns
set-up time clock HIGH to
STOP
0.6
−
µs
tBUF
set-up time STOP to
START
1.3
−
−
µs
tHD;STA
tSU;STA
START hold time
0.6
0.6
−
−
−
−
µs
µs
set-up time clock rising
edge to START
tr
tf
rise time (SDA and SCL)
fall time (SDA and SCL)
VILmin to VIHmax
VILmin to VIHmax
50
50
−
−
300
300
ns
ns
Video Output Timing (Figs. 7 and 8)
16-BIT VIDEO OUTPUT MODE
tsu
th2
tsu
th1
set-up time (CREF, HREF,
UV and Y valid to CLK27)
10
3
−
−
−
−
−
−
−
−
ns
ns
ns
ns
hold time (CLK27 to CREF,
HREF, UV and Y invalid)
set-up time (UV and Y
valid to CREF rising edge)
6
hold time (CREF rising
10
edge to UV and Y invalid)
8-BIT VIDEO OUTPUT MODE
tsu
set-up time (HREF and Y
valid to CLK27)
7
5
−
−
−
−
ns
ns
th2
hold time (CLK27 to HREF
and Y invalid)
DRAM Timing (Fig.9)
tCYC cycle time
tRP
tCSH
tRCD
130
50
−
−
−
−
−
−
−
−
ns
ns
ns
ns
RAS pre-charge time
CAS hold time
70
RAS to CAS delay time
20
1996 May 21
16
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
SYMBOL
tCAS
PARAMETER
CONDITIONS
MIN.
20
TYP.
MAX.
UNIT
ns
CAS pulse width LOW
page mode cycle time
CAS pre-charge time
RAS hold time after CAS
−
−
−
−
−
−
−
−
−
−
tPC
50
10
20
15
ns
ns
ns
ns
tCP
tRSH
tCRP
CAS to RAS pre-charge
time
tASR
tRAH
tASC
row address set-up time
row address hold time
0
−
−
−
−
−
−
ns
ns
ns
10
0
column address set-up
time
tCAH
tRCS
tRCH
column address hold time
read command set-up time
15
0
−
−
−
−
−
−
ns
ns
ns
read command hold time
(CAS)
0
tRRH
tWCS
read command hold time
(RAN)
0
0
−
−
−
−
ns
ns
write command set-up
time
tWCH
tDS
write command hold time
data-in set-up time
15
0
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
tDH
data-in hold time
15
−
tCAC
tRAC
read access time (CAS)
read access time (RAS)
20
70
−
Crystal oscillators
40 MHz SYSTEM CLOCK OSCILLATOR
Vosc(p-p)
oscillation amplitude
(peak-to-peak)
−
tbf
−
V
Gv
Gm
Ci
small signal voltage gain
mutual conductance
input capacitance
−
tbf
−
−
tbf
−
−
mA/V
pF
−
tbf
−
Cfb
fOSC
∆f
feedback capacitance
oscillation frequency
frequency tolerance
−
tbf
40
−
pF
−
−
MHz
ppm
−
−
27 MHz SYSTEM CLOCK OSCILLATOR
Vosc(p-p)
oscillation amplitude
(peak-to-peak)
−
tbf
−
V
GV
Gm
Ci
small signal voltage gain
mutual conductance
input capacitance
−
tbf
−
−
tbf
−
−
mA/V
pF
−
tbf
1996 May 21
17
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
tbf
MAX.
UNIT
pF
Cfb
fosc
∆f
feedback capacitance
oscillation frequency
frequency tolerance
−
−
−
−
−
−
27
MHz
ppm
−
t
clkH
2
I S bit clock
CLKIN
or
t
clkL
CLKOUT
t
t
d
h
2
I S data
and
word select outputs
DAOUT, WSOUT
t
t
h
su
I2S data,
word select
and
error flags inputs
DAIN, WSIN, EFIN
MGE327
Fig.5 I2S input/output timing.
t
t
r
f
t
t
LOW
HIGH
SCL
t
SU; STA
t
t
t
HD; DAT
SU;STO
SU; DAT
t
HD; STA
SDA
MGE328
t
BUF
Fig.6 I2C-bus timing.
18
1996 May 21
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
27 MHz clock
(CLK27)
t
h1
t
su
CREF
HREF
t
su1
t
t
h1
t
h2
su2
t
h2
U0 (Cb0)
V718
V0 (Cr0)
Y1
Y719
Y0
pixel #0
pixel #719
CSYNC
MGE329
(1)
Timing applies to CLK27 when programmed as an input or an output of the SAA2510.
(1) CSYNC (HIGH-to-LOW) to first sample and HREF (LOW-to-HIGH) = 264.5/244.5 CLK27 periods (625 lines/525 lines mode).
Fig.7 16-bit video output mode timing.
27 MHz clock
(CLK27)
t
su
HREF
t
t
h2
h1
Y bus
output
Cb
Y
Cr
Y719
pixel #719
pixel #0
MGE330
Fig.8 8-bit video CCIR656 output mode timing.
19
1996 May 21
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
t
t
RAS
CYC
RP
t
RSH
t
t
CRP
CSH
t
PC
CAS
t
CP
t
t
CAS
RCD
t
ASC
t
t
RAH
t
ASR
CAH
ADDRESS
t
RRH
t
t
RCS
RCH
W
t
CAC
READ
CYCLE
DRAM
data out
t
RAC
t
WCH
t
WCS
W
t
DH
WRITE
CYCLE
t
DS
VCD
data to
DRAM
MGE331
Fig.9 DRAM timing.
1996 May 21
20
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
APPLICATION INFORMATION
40 MHz
crystal
0 V
EBU
INTERFACE
Sys_osc_0
EBUIN
Sys_osc_1
EBUOUT
EBU input
AUDIOCLK
CLIN
CLOUT
DAOUT
WSOUT
Audio L, R
DAIN
AUDIO DAC
WSIN
ESIN
COMPACT DISC
MECHANISM
AND
16
9
DR0 to DR15
A0 to A8
CASN
CVBS
Y, C
HREF
DIGITAL
VIDEO
ENCODER
DECODER
VSYNC
4 Mbit
DRAM
8
8
UV0 to 7
Y0 to 7
CREF
RASN
SAA2510
W
VP0 to 7
CREF
ASEL
LLC
CLK27
2
I C-bus
+5 V
e.g.: SAA7185
2
I C-bus
CDIR
SDA
SCL
Vid_osc_0
RESET
27 MHz
crystal
MICROCONTROLLER
AND
USER INTERFACE
0 V
NDAV
Vid_osc_1
INTN
DRAMON
TEST1, 2
2
MGE326
0 V
VCD power supply pins not shown.
Fig.10 Application diagram; 16-bit video output mode.
1996 May 21
21
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
PACKAGE OUTLINE
QFP100: plastic quad flat package;
SOT317-1
100 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
y
X
A
80
51
81
50
Z
E
e
A
2
H
A
E
(A )
3
E
A
1
θ
w M
p
pin 1 index
L
p
b
L
31
100
detail X
1
30
w M
Z
v
M
M
D
A
B
b
p
e
D
B
H
v
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.36 2.87
0.10 2.57
0.40 0.25 20.1 14.1
0.25 0.13 19.9 13.9
24.2 18.2
23.6 17.6
1.0
0.6
0.8
0.4
1.0
0.6
mm
3.3
0.25
0.65
1.95
0.2 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-08-01
SOT317-1
1996 May 21
22
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
SOLDERING
Introduction
Wave soldering
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Reflow soldering
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
Reflow soldering techniques are suitable for all QFP
packages.
QFP100 (SOT382-1) or QFP160 (SOT322-1).
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1996 May 21
23
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 May 21
24
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
NOTES
1996 May 21
25
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
NOTES
1996 May 21
26
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
NOTES
1996 May 21
27
Philips Semiconductors – a worldwide company
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Colombia: see South America
Sweden: Kottbygatan 7, Akalla. S-16485 STOCKHOLM,
Tel. (0) 8-632 2000, Fax. (0) 8-632 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. (01) 488 2211, Fax. (01) 481 77 30
Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,
Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. (886) 2 382 4443, Fax. (886) 2 382 4444
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. (66) 2 745-4090, Fax. (66) 2 398-0793
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. (0212) 279 2770, Fax. (0212) 282 6707
Ukraine: PHILIPS UKRAINE,
2A Akademika Koroleva str., Office 165, 252148 KIEV,
Tel. 380-44-4760297, Fax. 380-44-4766991
United Kingdom: Philips Semiconductors LTD.,
276 Bath Road, Hayes, MIDDLESEX UB3 5BX,
Tel. (0181) 730-5000, Fax. (0181) 754-8421
United States: 811 East Arques Avenue, SUNNYVALE,
CA 94088-3409, Tel. (800) 234-7381, Fax. (708) 296-8556
Uruguay: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300
COPENHAGEN S, Tel. (032) 88 2636, Fax. (031) 57 1949
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. (358) 0-615 800, Fax. (358) 0-61580 920
France: 4 Rue du Port-aux-Vins, BP317,
92156 SURESNES Cedex,
Tel. (01) 4099 6161, Fax. (01) 4099 6427
Germany: P.O. Box 10 51 40, 20035 HAMBURG,
Tel. (040) 23 53 60, Fax. (040) 23 53 63 00
Greece: No. 15, 25th March Street, GR 17778 TAVROS,
Tel. (01) 4894 339/4894 911, Fax. (01) 4814 240
Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block,
Dr. Annie Besant Rd. Worli, BOMBAY 400 018
Tel. (022) 4938 541, Fax. (022) 4938 722
Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. (01) 7640 000, Fax. (01) 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,
Tel. (03) 645 04 44, Fax. (03) 648 10 07
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. (381) 11 825 344, Fax. (359) 211 635 777
Italy: PHILIPS SEMICONDUCTORS,
Piazza IV Novembre 3, 20124 MILANO,
Tel. (0039) 2 6752 2531, Fax. (0039) 2 6752 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108, Tel. (03) 3740 5130, Fax. (03) 3740 5077
Korea: Philips House, 260-199 Itaewon-dong,
Yongsan-ku, SEOUL, Tel. (02) 709-1412, Fax. (02) 709-1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,
SELANGOR, Tel. (03) 750 5214, Fax. (03) 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO,
TEXAS 79905, Tel. 9-5(800) 234-7831, Fax. (708) 296-8556
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. (040) 2783749, Fax. (040) 2788399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. (09) 849-4160, Fax. (09) 849-7811
Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,
Marketing & Sales Communications, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Fax. +31-40-2724825
SCDS48
© Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Norway: Box 1, Manglerud 0612, OSLO,
Tel. (022) 74 8000, Fax. (022) 74 8341
Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC,
MAKATI, Metro MANILA,
Printed in The Netherlands
Tel. (63) 2 816 6380, Fax. (63) 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. (022) 612 2831, Fax. (022) 612 2327
537021/1200/01/pp28
Date of release: 1996 May 21
9397 750 00851
Document order number:
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