PHD24N03LT [NXP]
TrenchMOS transistor Logic level FET; 的TrenchMOS晶体管逻辑电平场效应管
| 型号： | PHD24N03LT |
| 厂家： | 
NXP |
| 描述： | TrenchMOS transistor Logic level FET |
| 文件： | 总8页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Preliminary specification
TrenchMOS transistor
Logic level FET
PHD24N03LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
d
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
VDSS = 30 V
ID = 24 A
R
DS(ON) ≤ 56 mΩ (VGS = 5 V)
g
RDS(ON) ≤ 50 mΩ (VGS = 10 V)
s
GENERAL DESCRIPTION
PINNING
SOT428 (DPAK)
N-channel enhancement mode,
logic level, field-effect power
transistor in a plastic envelope
using ’trench’ technology. The
device has very low on-state
resistance. It is intended for use in
dc to dc converters and general
purpose switching applications.
PIN
DESCRIPTION
tab
1
2
gate
drain 1
source
drain
3
2
tab
1
3
ThePHD24N03LTissuppliedinthe
SOT428 (DPAK) surface mounting
package.
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
-
-
-
-
-
-
-
30
30
± 13
24
20
96
60
175
V
V
V
A
A
A
W
˚C
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
IDM
PD
Tj, Tstg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
- 55
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-mb
Thermal resistance junction
to mounting base
-
2.5
K/W
Rth j-a
Thermal resistance junction pcb mounted, minimum footprint
to ambient
50
-
K/W
1 it is not possible to make connection to pin 2 of the SOT428 package.
December 1999
1
Rev 1.100
Philips Semiconductors
Preliminary specification
TrenchMOS transistor
Logic level FET
PHD24N03LT
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
V(BR)DSS Drain-source breakdown
CONDITIONS
MIN. TYP. MAX. UNIT
VGS = 0 V; ID = 0.25 mA;
VDS = VGS; ID = 1 mA
30
27
-
-
-
-
V
V
voltage
Gate threshold voltage
Tj = -55˚C
VGS(TO)
1.0
0.5
1.5
-
2.0
-
V
V
Tj = 175˚C
Tj = -55˚C
-
-
-
-
-
-
-
-
2.3
56
50
104
100
10
500
V
RDS(ON)
Drain-source on-state
resistance
VGS = 10 V; ID = 12 A
50
45
-
10
0.05
-
mΩ
mΩ
mΩ
nA
µA
µA
VGS = 5 V; ID = 12 A
Tj = 175˚C
Tj = 175˚C
IGSS
IDSS
Gate source leakage current VGS = ±5 V; VDS = 0 V
Zero gate voltage drain
current
VDS = 30 V; VGS = 0 V;
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 24 A; VDD = 15 V; VGS = 5 V
-
-
-
7
2.3
5
-
-
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 15 V; RD = 0.6 Ω;
VGS = 5 V; RG = 10 Ω
Resistive load
-
-
-
-
12
50
30
36
-
-
-
-
ns
ns
ns
ns
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from tab to centre of die
Measured from source lead to source
bond pad
-
-
3.5
7.5
-
-
nH
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
-
-
460
144
78
-
-
-
pF
pF
pF
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IS
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
-
-
-
-
24
A
A
V
ISM
-
96
VSD
IF = 24 A; VGS = 0 V
1.05
1.5
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 12 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 30 V
-
-
50
100
-
-
ns
nC
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
15
UNIT
WDSS
Drain-source non-repetitive ID = 12 A; VDD ≤ 15 V; VGS = 5 V;
unclamped inductive turn-off RGS = 50 Ω; Tmb = 25 ˚C
energy
-
mJ
December 1999
2
Rev 1.100
Philips Semiconductors
Preliminary specification
TrenchMOS transistor
Logic level FET
PHD24N03LT
Normalised Power Derating
PD%
Transient thermal impedance, Zth j-mb (K/W)
120
110
100
90
80
70
60
50
40
30
20
10
0
10
1
D =
0.5
0.2
0.1
0.05
0.02
0.1
0.01
p
t
t
p
P
D
D =
T
0
t
T
1us 10us 100us 1ms 10ms 0.1s
pulse width, tp (s)
1s
10s
0
20
40
60
80
Tmb /
100 120 140 160 180
C
Fig.1. Normalised power dissipation.
PD% = 100 PD/PD 25 ˚C = f(Tmb)
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
3.5 V
ID, Drain current (Amps)
120
110
100
90
80
70
60
50
40
30
20
10
0
20
15
10
5
5 V
15 V
3 V
VGS = 2.5 V
Tj = 25 C
0
0
20
40
60
80
100 120 140 160 180
0
5
10
15
20
25
30
Tmb /
C
VDS, Drain-Source voltage (Volts)
Fig.2. Normalised continuous drain current.
ID% = 100 ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
RDS(on), Drain-Source on resistance (Ohms)
ID, Drain current (Amps)
RDS(ON) = VDS/ID
0.12
0.1
100
10
1
3 V
VGS = 2.5 V
10 us
0.08
0.06
0.04
0.02
0
100 us
3.5 V
5 V
DC
1 ms
15 V
10 ms
Tmb = 25 C
Tj = 25 C
0
5
10
15
20
1
10
VDS, Drain-source voltage (Volts)
100
ID, Drain current (Amps)
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
December 1999
3
Rev 1.100
Philips Semiconductors
Preliminary specification
TrenchMOS transistor
Logic level FET
PHD24N03LT
VGS(TO) / V
max.
Drain current, ID (A)
20
2.5
2
VDS = 25 V
15
typ.
1.5
1
10
5
min.
Tj = 25 C
175 C
2
0.5
0
0
0
1
3
4
5
-100
-50
0
50
Tj / C
100
150
200
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
ID = f(VGS); parameter Tj
Fig.10. Gate threshold voltage.
GS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
V
Sub-Threshold Conduction
Transconductance, gfs (S)
15
1E-01
1E-02
1E-03
1E-04
1E-05
1E-05
VDS = 25 V
Tj = 25 C
175 C
10
5
2%
typ
98%
0
0
5
10
Drain current, ID (A)
15
20
0
0.5
1
1.5
2
2.5
3
Fig.8. Typical transconductance, Tj = 25 ˚C.
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
gfs = f(ID)
Capacitances Ciss, Coss, Crss (pF)
a
1000
2
Ciss
1.5
1
100
Coss
Crss
0.5
0
Tj = 25 C
10
-100
0
100
200
1
10
100
1000
-50
50
Tj / C
150
Drain-source voltage, VDS (V)
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 12 A; VGS = 5 V
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
December 1999
4
Rev 1.100
Philips Semiconductors
Preliminary specification
TrenchMOS transistor
Logic level FET
PHD24N03LT
VGS, Gate-Source voltage (Volts)
Source-Drain diode current, IF(A)
VGS = 0 V
15
20
15
10
5
VDD = 15 V
ID = 24 A
Tj = 25 C
10
5
175 C
Tj = 25 C
0
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0
5
10
15
20
25
Qg, Gate charge (nC)
Source-Drain voltage, VSDS (V)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
Fig.14. Typical reverse diode current.
IF = f(VSDS); parameter Tj
December 1999
5
Rev 1.100
Philips Semiconductors
Preliminary specification
TrenchMOS transistor
Logic level FET
PHD24N03LT
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
seating plane
A
y
A
2
E
A
A
1
b
D
1
2
mounting
base
E
1
D
H
E
L
2
2
L
1
L
1
3
b
1
b
w
M
A
c
e
e
1
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
b
E
H
E
max.
D
L
1
min.
A
max.
E
max.
y
D
max.
1
1
(1)
1
A
b
2
A
UNIT
mm
b
c
e
e
1
L
L
w
2
1
2
max.
max.
min.
max.
0.65 0.89
0.45 0.71
0.7
0.5
2.38
2.22
0.89 1.1
0.71 0.9
5.36
5.26
0.4 6.22
0.2 5.98
6.73
6.47
2.95
2.55
10.4
9.6
4.81
4.45
4.57
0.2
0.2
4.0 2.285
0.5
Note
1. Measured from heatsink back to lead.
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SOT428
98-04-07
Fig.15. SOT428 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
December 1999
6
Rev 1.100
Philips Semiconductors
Preliminary specification
TrenchMOS transistor
Logic level FET
PHD24N03LT
MOUNTING INSTRUCTIONS
Dimensions in mm
7.0
7.0
2.15
2.5
1.5
4.57
Fig.16. SOT428 : soldering pattern for surface mounting.
December 1999
7
Rev 1.100
Philips Semiconductors
Preliminary specification
TrenchMOS transistor
Logic level FET
PHD24N03LT
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
December 1999
8
Rev 1.100
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