PHD24N03LT/T3 [NXP]
TRANSISTOR 20 A, 30 V, 0.056 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-252AA, PLASTIC, SC-63, DPAK-3, FET General Purpose Power;
| 型号： | PHD24N03LT/T3 |
| 厂家： | 
NXP |
| 描述： | TRANSISTOR 20 A, 30 V, 0.056 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-252AA, PLASTIC, SC-63, DPAK-3, FET General Purpose Power 开关 脉冲 晶体管 |
| 文件： | 总15页 (文件大小：437K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PHD24N03LT
N-channel enhancement mode field-effect transistor
Rev. 02 — 27 July 2000
Product specification
1. Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™1 technology.
Product availability:
PHD24N03LT in SOT428 (D-PAK).
2. Features
■ TrenchMOS™ technology
■ Low on-state resistance
■ Avalanche ruggedness rated
■ Logic level compatible
■ Surface mount package.
3. Applications
■ DC to DC converter
c
c
■ High speed, low resistance switch
4. Pinning information
Table 1: Pinning - SOT428, simplified outline and symbol
Pin
1
Description
gate (g)
Simplified outline
Symbol
4
d
[1]
2
drain (d)
3
source (s)
g
4
mounting base,
connected to
drain (d)
2
1
3
03ab30
s
Top view
MBK091
SOT428 (D-PAK)
N-channel MOSFET
[1] It is not possible to make connection to pin 2 of the SOT428 package.
1. TrenchMOS is a trademark of Royal Philips Electronics.
PHD24N03LT
N-channel enhancement mode field-effect transistor
Philips Semiconductors
5. Quick reference data
Table 2: Quick reference data
Symbol Parameter
Conditions
Typ
−
Max
30
Unit
V
VDS
ID
drain-source voltage (DC)
drain current (DC)
Tj = 25 to 175 °C
Tmb = 25 °C; VGS = 10 V
Tmb = 25 °C
−
20
A
Ptot
Tj
total power dissipation
junction temperature
−
37.5
175
50
W
−
°C
mΩ
mΩ
RDSon
drain-source on-state resistance
VGS = 10 V; ID = 10 A
VGS = 5 V; ID = 10 A
28
38
56
6. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
−
Max
30
Unit
V
VDS
VDGR
VGS
VGSM
ID
drain-source voltage (DC)
Tj = 25 to 175 °C
drain-gate voltage (DC)
gate-source voltage (DC)
peak gate-source voltage
drain current (DC)
Tj = 25 to 175 °C; RGS = 20 kΩ
−
30
V
−
±15
±20
20
V
tp ≤ 50 µs; pulsed; duty cycle = 25%
−
V
Tmb = 25 °C; VGS = 10 V;
−
A
Figure 2 and 3
T
mb = 100 °C; VGS = 10 V; Figure 2
−
−
14
80
A
A
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs;
Figure 3
Ptot
Tstg
Tj
total power dissipation
storage temperature
Tmb = 25 °C; Figure 1
−
37.5
W
−55
−55
+175
+175
°C
°C
operating junction temperature
Source-drain diode
IS
source (diode forward) current (DC)
peak source (diode forward) current
Tmb = 25 °C
−
−
20
80
A
A
ISM
Tmb = 25 °C; pulsed; tp ≤ 10 µs
Avalanche ruggedness limiting values
EAS
non-repetitive avalanche energy
unclamped inductive load; ID = 19 A;
tp = 0.2 ms; VDD ≤ 15 V; RGS = 50 Ω;
VGS = 5 V; starting Tj = 25 °C; Figure 4
−
−
74
20
mJ
A
IAS
non-repetitive avalanche current
unclamped inductive load; VDD ≤ 15 V;
RGS = 50 Ω; VGS = 5 V; Figure 4
9397 750 07311
© Philips Electronics N.V. 2000. All rights reserved.
Product specification
Rev. 02 — 27 July 2000
2 of 13
PHD24N03LT
N-channel enhancement mode field-effect transistor
Philips Semiconductors
03aa24
03aa16
120
120
I
P
der
der
(%)
100
(%)
100
80
60
40
20
0
80
60
40
20
0
0
25
50
75 100 125 150 175 200
o
0
25
50
75 100 125 150 175 200
o
T
( C)
T
( C)
mb
mb
V
GS ≥ 5 V
Ptot
Pder
=
× 100%
----------------------
P
ID
°
tot(25 C)
Ider
=
× 100%
------------------
I
°
D(25 C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
03ab07
03aa99
µ
µ
t
p
P
δ =
T
t
t
p
T
Tmb = 25 °C; IDM is single pulse.
Unclamped inductive load; VDD ≤ 15 V; RGS = 50 Ω;
VGS = 5 V; starting Tj = 25°C and 150°C.
Fig 3. Safe operating area; continuous and peak drain
currents as a function of drain-source voltage.
Fig 4. Non-repetitive avalanche ruggedness current
as a function of pulse duration.
9397 750 07311
© Philips Electronics N.V. 2000. All rights reserved.
Product specification
Rev. 02 — 27 July 2000
3 of 13
PHD24N03LT
N-channel enhancement mode field-effect transistor
Philips Semiconductors
7. Thermal characteristics
Table 4: Thermal characteristics
Symbol
Parameter
Conditions
Value
Unit
Rth(j-mb)
thermal resistance from junction to mounting mounted on a metal clad substrate;
4
K/W
base
Figure 5
Rth(j-a)
thermal resistance from junction to ambient
mounted on a printed circuit board;
minimum footprint
50
K/W
7.1 Transient thermal impedance
03aa98
δ
t
p
P
δ =
T
t
t
p
T
Mounted on a metal clad substrate.
Fig 5. Transient thermal impedance from junction to mounting base as a function of
pulse duration.
9397 750 07311
© Philips Electronics N.V. 2000. All rights reserved.
Product specification
Rev. 02 — 27 July 2000
4 of 13
PHD24N03LT
N-channel enhancement mode field-effect transistor
Philips Semiconductors
8. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified
Symbol
Static characteristics
V(BR)DSS drain-source breakdown
voltage
Parameter
Conditions
Min
Typ
Max
Unit
ID = 250 µA; VGS = 0 V
Tj = 25 °C
30
27
40
−
−
V
V
Tj = −55 °C
−
VGS(th)
gate-source threshold voltage ID = 1 mA; VDS = VGS;
Figure 10
Tj = 25 °C
Tj = 175 °C
Tj = −55 °C
1
1.5
−
2
V
V
V
0.5
−
−
−
2.3
IDSS
drain-source leakage current VDS = 30 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
−
−
−
0.05
5.0
10
10
µA
µA
nA
500
100
IGSS
gate-source leakage current VGS = ±10 V; VDS = 0 V
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 10 A;
Figure 8 and 9
Tj = 25 °C
−
28
50
mΩ
VGS = 5 V; ID = 10 A;
Figure 8 and 9
Tj = 25 °C
−
−
38
70
56
mΩ
mΩ
Tj = 175 °C
104
Dynamic characteristics
gfs
forward transconductance
VDS = 10 V; ID = 10 A;
Figure 12
−
13
−
S
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
total gate charge
ID = 20 A; VDS = 15 V;
VGS = 5 V; Figure 15
−
−
−
−
−
−
−
−
−
−
10
−
−
−
−
−
−
−
−
−
−
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
gate-source charge
gate-drain (Miller) charge
input capacitance
2.7
5.7
460
143
107
18
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Figure 13
output capacitance
reverse transfer capacitance
turn-on delay time
turn-off rise time
VDD = 15 V; RD = 0.75 Ω;
VGS = 5 V; RG = 10 Ω
130
22
td(off)
tf
turn-off delay time
turn-off fall time
45
Source-drain diode
VSD
source-drain (diode forward) IS = 10 A; VGS = 0 V;
−
0.95
1.5
V
voltage
Figure 14
trr
reverse recovery time
recovered charge
IS = 10 A;
dIS/dt = −100 A/µs;
VGS = 0 V; VDS = 25 V
−
−
65
75
−
−
ns
Qr
nC
9397 750 07311
© Philips Electronics N.V. 2000. All rights reserved.
Product specification
Rev. 02 — 27 July 2000
5 of 13
PHD24N03LT
N-channel enhancement mode field-effect transistor
Philips Semiconductors
03ab00
03ab02
50
o
C
V
= 10V
I
D
T = 25
GS
j
45
40
35
30
25
20
15
10
5
(A)
5 V
4.5 V
4 V
3 V
2.8 V
2.6 V
2.4 V
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
(V)
2
V
DS
Tj = 25 °C
Tj = 25 °C and 175 °C; VDS > ID × RDSon
Fig 6. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 7. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
03ab01
03aa27
2.0
a
1.8
1.6
1.4
1.2
1.0
Ω
0.8
0.6
0.4
0.2
0
-60
-20
20
60
100
140
180
o
T ( C)
j
Tj = 25 °C
RDSon
a =
---------------------------
RDSon(25 C)
°
Fig 8. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 9. Normalized drain-source on-state resistance
factor as a function of junction temperature.
9397 750 07311
© Philips Electronics N.V. 2000. All rights reserved.
Product specification
Rev. 02 — 27 July 2000
6 of 13
PHD24N03LT
N-channel enhancement mode field-effect transistor
Philips Semiconductors
03aa33
03aa36
-1
2.5
10
V
GS(th)
I
D
(V)
max
typ
-2
2
(A)
10
10
10
-3
-4
-5
-6
1.5
1
min
typ
max
min
10
10
0.5
0
0
0.5
1
1.5
2
2.5
(V)
3
-60
-20
20
60
100
140
180
o
T ( C)
V
j
GS
ID = 1 mA; VDS = VGS
Tj = 25 °C; VDS = 5 V
Fig 10. Gate-source threshold voltage as a function of
junction temperature.
Fig 11. Sub-threshold drain current as a function of
gate-source voltage.
03ab03
03ab05
Tj = 25 °C and 175 °C; VDS > ID × RDSon
VGS = 0 V; f = 1 MHz
Fig 12. Forward transconductance as a function of
drain current; typical values.
Fig 13. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
9397 750 07311
© Philips Electronics N.V. 2000. All rights reserved.
Product specification
Rev. 02 — 27 July 2000
7 of 13
PHD24N03LT
N-channel enhancement mode field-effect transistor
Philips Semiconductors
03ab06
03ab04
Tj = 25 °C and 175 °C; VGS = 0 V
ID = 20 A; VDS = 15 V
Fig 14. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
Fig 15. Gate-source voltage as a function of gate
charge; typical values.
9397 750 07311
© Philips Electronics N.V. 2000. All rights reserved.
Product specification
Rev. 02 — 27 July 2000
8 of 13
PHD24N03LT
N-channel enhancement mode field-effect transistor
Philips Semiconductors
9. Package outline
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
seating plane
y
A
A
E
A
2
A
b
D
1
1
2
mounting
base
E
1
D
H
E
L
2
2
L
1
L
1
3
b
b
w
M
A
c
1
e
e
1
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
b
E
H
E
max.
D
L
1
min.
A
max.
E
max.
y
D
max.
1
1
(1)
1
A
A
b
2
UNIT
mm
b
c
e
e
1
L
L
w
2
1
2
max.
max.
min.
max.
0.65 0.89
0.45 0.71
0.7
0.5
2.38
2.22
0.89 1.1
0.71 0.9
5.36
5.26
0.4 6.22
0.2 5.98
6.73
6.47
10.4 2.95
9.6
2.55
4.81
4.45
4.57
0.2
0.2
4.0 2.285
0.5
Note
1. Measured from heatsink back to lead.
REFERENCES
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
JEDEC
EIAJ
98-04-07
99-09-13
SOT428
TO-252
SC-63
Fig 16. SOT428 (D-PAK).
9397 750 07311
© Philips Electronics N.V. 2000. All rights reserved.
Product specification
Rev. 02 — 27 July 2000
9 of 13
PHD24N03LT
N-channel enhancement mode field-effect transistor
Philips Semiconductors
10. Revision history
Table 6: Revision history
Rev Date
CPCN
Description
02 20000727
01 19991201
-
-
Product specification; second version; supersedes PHD24N03LT_1 of 991201.
Product specification; initial version.
9397 750 07311
© Philips Electronics N.V. 2000. All rights reserved.
Product specification
Rev. 02 — 27 July 2000
10 of 13
PHD24N03LT
N-channel enhancement mode field-effect transistor
Philips Semiconductors
11. Data sheet status
[1]
Datasheet status
Product status Definition
Development
Objective specification
This data sheet contains the design target or goal specifications for product development. Specification may
change in any manner without notice.
Preliminary specification Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any
time without notice in order to improve design and supply the best possible product.
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
12. Definitions
13. Disclaimers
Short-form specification — The data in
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
a
short-form specification is
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products
are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
9397 750 07311
© Philips Electronics N.V. 2000 All rights reserved.
Product specification
Rev. 02 — 27 July 2000
11 of 13
PHD24N03LT
N-channel enhancement mode field-effect transistor
Philips Semiconductors
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Building BE, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. +31 40 272 4825
(SCA70)
9397 750 07311
© Philips Electronics N.V. 2000. All rights reserved.
Product specification
Rev. 02 — 27 July 2000
12 of 13
PHD24N03LT
N-channel enhancement mode field-effect transistor
Philips Semiconductors
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
3
4
5
6
7
7.1
8
9
10
11
12
13
© Philips Electronics N.V. 2000.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 27 July 2000
Document order number: 9397 750 07311
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PHD24N03LT; N-
channel
enhancement mode
field-effect
download datasheet
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N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS
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Product availability:
PHD24N03LT in SOT428 (D-PAK).
Models
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Features
●
●
●
●
●
TrenchMOS technology
Low on-state resistance
Avalanche ruggedness rated
Logic level compatible
Surface mount package.
Applications
●
●
DC to DC converter
High speed, low resistance switch
Datasheet
Type number Title
Publication
release date
Datasheet status
Page
count
File
size
(kB)
Datasheet
PHD24N03LT N-channel
7/27/2000
Product
specification
13
382
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enhancement mode
field-effect
transistor
Parametrics
Type number Package
V
(V) Configuration
I DC(A) R
(mOhm) Q
DS
D
DS(on) gd
(typ)(nC)
50@10V
56@5V
SOT428 (SC-63, D-PAK)
PHD24N03LT
30
Single N-channel 20
5.7
Products, packages, availability and ordering
Type number North
American
Ordering code Marking/Packing Package Device status Buy online
Discretes
(12NC)
packing info
type number
Standard Marking
9340 556 36118 * Reel Pack,
SMD, 13"
SOT428
PHD24N03LT
/T3
PHD24N03LT
Full production
(SC-63; D-
PAK)
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