PHD2N50 [NXP]

1.9A, 500V, 5ohm, N-CHANNEL, Si, POWER, MOSFET;


型号：	PHD2N50
厂家：	NXP
描述：	1.9A, 500V, 5ohm, N-CHANNEL, Si, POWER, MOSFET
文件：	总7页 (文件大小：60K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Philips Semiconductors

Product specification

PowerMOS transistor

PHD2N50

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel enhancement mode

field-effect power transistor in a

plastic envelope suitable for surface

mounting featuring high avalanche

energy capability, stable off-state

characteristics, fast switching and

high thermal cycling performance

withlowthermalresistance. Intended

for use in Switched Mode Power

Supplies (SMPS), motor control

circuits and general purpose

switching applications.

SYMBOL

PARAMETER

MAX.

UNIT

V_DS

I_D

Drain-source voltage

Drain current (DC)

Total power dissipation

Drain-source on-state resistance

500

1.9

Ω

P_tot

R_DS(ON)

PINNING - SOT428

PIN CONFIGURATION

SYMBOL

DESCRIPTION

tab

gate

drain

source

tab drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

I_D

Continuous drain current

T_mb= 25 ˚C; V_GS= 10 V

T_mb= 100 ˚C; V_GS= 10 V

T_mb= 25 ˚C

1.9

1.2

I_DM

P_D

Pulsed drain current

Total dissipation

7.5

T_mb= 25 ˚C

∆P_D/∆T_mbLinear derating factor

T_mb> 25 ˚C

0.33

± 30

100

W/K

V_GS

E_AS

Gate-source voltage

Single pulse avalanche

energy

_DD≤ 50 V; starting T_j= 25˚C; R_GS= 50 Ω;

V_GS= 10 V

_DD≤ 50 V; starting T_j= 25˚C; R_GS= 50 Ω;

V_GS= 10 V

I_AS

Peak avalanche current

T_j, T_stg

Operating junction and

storage temperature range

- 55

150

˚C

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R_{th j-mb}

Thermal resistance junction to

K/W

mounting base

R_{th j-a}

Thermal resistance junction to

ambient

pcb mounted, minimum

footprint

K/W

July 1997

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

PHD2N50

ELECTRICAL CHARACTERISTICS

T_j= 25 ˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

V_(BR)DSS

Drain-source breakdown

voltage

V_GS= 0 V; I_D= 0.25 mA

500

∆V_(BR)DSS

∆T_j

Drain-source breakdown

voltage temperature coefficient

Drain-source on resistance

Gate threshold voltage

Forward transconductance

Drain-source leakage current

V_DS= V_GS; I_D= 0.25 mA

0.6

V/K

R_DS(ON)

V_GS(TO)

g_fs

V_GS= 10 V; I_D= 1 A

V_DS= V_GS; I_D= 0.25 mA

V_DS= 30 V; I_D= 1 A

V_DS= 500 V; V_GS= 0 V

V_DS= 400 V; V_GS= 0 V; T_j= 125 ˚C

V_GS= ±30 V; V_DS= 0 V

2.0

0.5

3.1

3.0

1.3

4.0

250

200

Ω

µA

I_DSS

I_GSS

Gate-source leakage current

Q_g(tot)

Q_gs

Q_gd

Total gate charge

Gate-source charge

Gate-drain (Miller) charge

I_D= 2 A; V_DD= 400 V; V_GS= 10 V

t_d(on)

t_r

t_d(off)

t_f

Turn-on delay time

Turn-on rise time

Turn-off delay time

Turn-off fall time

V_DD= 250 V; I_D= 2 A;

R_G= 24 Ω; R_D= 120 Ω

L_d

L_s

Internal drain inductance

Internal source inductance

Measured from tab to centre of die

Measured from source lead solder

point to source bond pad

3.5

7.5

C_iss

C_oss

C_rss

Input capacitance

Output capacitance

Feedback capacitance

V_GS= 0 V; V_DS= 25 V; f = 1 MHz

236

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS

T_j= 25 ˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

I_S

Continuous source current

T_mb= 25˚C

1.9

7.5

1.2

(body diode)

I_SM

V_SD

Pulsed source current (body

diode)

Diode forward voltage

T_mb= 25˚C

I_S= 2 A; V_GS= 0 V

t_rr

Q_rr

Reverse recovery time

Reverse recovery charge

I_S= 2 A; V_GS= 0 V; dI/dt = 100 A/µs

350

2.5

µC

July 1997

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

PHD2N50

Normalised Power Derating

PD%

120

Zth j-mb / (K/W)

1E+01

1E+00

1E-01

1E-02

110

100

0.5

0.2

0.1

0.05

0.02

D =

Tmb /

100

120

140

1E-07

1E-05

1E-03

t / s

1E-01

1E+01

Fig.1. Normalised power dissipation.

PD% = 100 P_D/P_{D 25 ˚C}= f(T_mb)

Fig.4. Transient thermal impedance.

Z_{th j-mb}= f(t); parameter D = t_p/T

Normalised Current Derating

ID%

PHP2N50

ID, Drain current (Amps)

Tj = 25 C

120

110

100

20 V

10 V

7 V

6.5 V

6 V

5.5 V

VGS = 5 V

Tmb /

100

120

140

VDS, Drain-Source voltage (Volts)

Fig.2. Normalised continuous drain current.

ID% = 100 I_D/I_{D 25 ˚C}= f(T_mb); conditions: V_GS≥ 10 V

Fig.5. Typical output characteristics.

I_D= f(V_DS); parameter V_GS

PHP2N50

Drain current, ID (Amps)

Tmb = 25 C

Drain-Source on resistance, RDS(ON) (Ohms)

PHP2N50

5V 5.5 V

6 V

Tj = 25 C

tp =

10 us

6.5 V

7 V

100us

1 ms

10 V

10 ms

100ms

VGS = 20 V

0.1

0.01

100

Drain-source voltage, VDS (Volts)

1000

Drain current, ID (Amps)

Fig.3. Safe operating area. T_mb= 25 ˚C

I_D& I_DM= f(V_DS); I_DMsingle pulse; parameter t_p

Fig.6. Typical on-state resistance.

R_DS(ON)= f(I_D); parameter V_GS

July 1997

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

PHD2N50

VGS(TO) / V

PHP2N50

Drain current, ID (A)

max.

VDD = 30 V

Tj = 25 C

typ.

150 C

min.

-60 -40 -20

Tj /

80 100 120 140

Gate-source voltage, VGS (V)

Fig.7. Typical transfer characteristics.

I_D= f(V_GS); parameter T_j

Fig.10. Gate threshold voltage.

V_GS(TO)= f(T_j); conditions: I_D= 0.25 mA; V_DS= V_GS

SUB-THRESHOLD CONDUCTION

ID / A

Transconductance, gfs (S)

VDD = 30 V

PHP2N50

1E-01

1E-02

1E-03

1E-04

1E-05

1E-06

2.5

Tj = 25 C

2 %

typ

98 %

1.5

150 C

0.5

Drain current, ID (A)

VGS / V

Fig.8. Typical transconductance.

g_fs= f(I_D); parameter T_j

Fig.11. Sub-threshold drain current.

I_D= f(V_GS); conditions: T_j= 25 ˚C; V_DS= V_GS

Normalised RDS(ON) = f(Tj)

PHP2N50

Capacitances, Ciss, Coss, Crss (pF)

1000

100

Ciss

Coss

Crss

-60 -40 -20

20 40 60 80 100 120 140

Tj /

100

1000

Drain-source voltage, VDS (V)

Fig.9. Normalised drain-source on-state resistance.

a = R_DS(ON)/R_{DS(ON)25 ˚C}= f(T_j); I_D= 1 A; V_GS= 10 V

Fig.12. Typical capacitances, C_iss, C_oss, C_rss.

C = f(V_DS); conditions: V_GS= 0 V; f = 1 MHz

July 1997

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

PHD2N50

Gate-Source voltage, VGS (Volts)

PHP2N50

Source-drain diode current, IF(A)

VGS = 0 V

ID = 2 A

300 V

200 V

VDD = 400 V

150 C

Tj = 25 C

Gate charge, Qg (nC)

0.5

1.5

Source-Drain voltage, VSDS (V)

Fig.13. Typical turn-on gate-charge characteristics.

V_GS= f(Q_G); parameter V_DS

Fig.16. Source-Drain diode characteristic.

I_F= f(V_SDS); parameter T_j

Switching times, td(on), tr, td(off), tf (ns)

PHP2N50

EAS, Normalised unclamped inductive energy (%)

120

1000

100

VDD = 250V

RD = 120 Ohms

Tj = 25 C

110

100

td(off)

td(on)

100

120

140

Gate resistance, RG (Ohms)

Starting Tj ( C)

Fig.14. Typical switching times.

t_d(on), t_r, t_d(off), t_f= f(R_G)

Fig.17. Normalised unclamped inductive energy.

E_AS% = f(T_j)

Normalised Drain-source breakdown voltage

V(BR)DSS @ Tj

1.15

1.1

VDD

V(BR)DSS @ 25 C

1.05

VDS

VGS

-ID/100

T.U.T.

0.95

0.9

R 01

RGS

shunt

0.85

-100

-50

100

150

Tj, Junction temperature (C)

Fig.18. Unclamped inductive test circuit.

Fig.15. Normalised drain-source breakdown voltage.

V_(BR)DSS/V_{(BR)DSS 25 ˚C}= f(T_j)

E_AS= 0.5 LI_D²V_(BR)DSS/(V_(BR)DSS− V_DD

)

July 1997

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

PHD2N50

MECHANICAL DATA

Dimensions in mm : Net Mass: 1.4 g

seating plane

1.1

2.38 max

0.93 max

5.4

6.73 max

tab

4 min

4.6

6.22 max

0.5 min

10.4 max

0.5

0.3

0.5

0.8 max

(x2)

2.285 (x2)

Fig.19. SOT428 : centre pin connected to mounting base.

MOUNTING INSTRUCTIONS

Dimensions in mm

7.0

2.15

2.5

1.5

4.57

Fig.20. SOT428 : soldering pattern for surface mounting.

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent

damage to MOS gate oxide.

2. Epoxy meets UL94 V0 at 1/8".

July 1997

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

PHD2N50

DEFINITIONS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Electronics N.V. 1997

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury. Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

July 1997

Rev 1.000

PHD2N50 [NXP]

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