PCK2510SPW-T [NXP]
暂无描述;
NXP 
INTEGRATED CIRCUITS
PCK2510S
50–150 MHz 1:10 SDRAM clock driver
Product specification
1999 Dec 13
Philips
Semiconductors
Philips Semiconductors
Product specification
50–150 MHz 1:10 SDRAM clock driver
PCK2510S
independent of the duty cycle at CLK. All outputs can be enabled or
disabled via a single output enable input. When the G input is high,
the outputs switch in phase and frequency with CLK; when the G
input is low, the outputs are disabled to the logic-low state.
FEATURES
• Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM
applications
• Spread Spectrum clock compatible
• Operating frequency 50 to 150 MHz
Unlike many products containing PLLs, the PCK2510S does not
require external RC networks. The loop filter for the PLL is included
on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the PCK2510S requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power
up and application of a fixed-frequency, fixed-phase signal at CLK,
and following any changes to the PLL reference. The PLL can be
• (t
– jitter) at 100 to133 MHz = ±50 ps
phase error
• Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps
• Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps
• Pin-to-pin skew < 200 ps
bypassed for test purposes by strapping AV to ground.
CC
The PCK2510S is characterized for operation from 0°C to +70°C.
• Available in plastic 24-Pin TSSOP
• Distributes one clock input to one bank of ten outputs
PIN CONFIGURATION
• External Feedback (FBIN) terminal Is used to synchronize the
outputs to the clock input
CLK
1
2
24
23
22
21
20
19
18
17
16
15
14
13
AGND
• On-Chip series damping resistors
• No external RC network required
• Operates at 3.3 V
V
AV
CC
CC
3
1Y0
1Y1
V
CC
4
1Y9
1Y8
GND
GND
1Y7
5
1Y2
6
GND
GND
1Y3
DESCRIPTION
7
The PCK2510S is a high-performance, low-skew, low-jitter,
phase-locked loop (PLL) clock driver. It uses a PLL to precisely
align, in both frequency and phase, the feedback (FBOUT) output to
the clock (CLK) input signal. It is specifically designed for use with
8
9
1Y4
1Y6
1Y5
10
11
V
CC
synchronous DRAMs. The PCK2510S operates at 3.3 V V and is
CC
G
V
CC
input compatible with both 2.5 V and 3.3 V input voltage ranges. It
also provides integrated series damping resistors that make it ideal
for driving point-to-point loads.
FBOUT 12
FBIN
SW00382
One bank of ten outputs provides ten low-skew, low-jitter copies of
CLK. Output signal duty cycles are adjusted to 50 percent,
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
PCK2510S PW
DRAWING NUMBER
24-Pin Plastic TSSOP
0°C to +70°C
SOT355-1
2
1999 Dec 13
853–2184 22832
Philips Semiconductors
Product specification
50–150 MHz 1:10 SDRAM clock driver
PCK2510S
PIN DESCRIPTIONS
PIN NUMBER
1
SYMBOL
TYPE
GND
PWR
NAME, FUNCTION, and DIRECTION
AGND
Analog ground. AGND provides the ground reference for the analog circuitry.
Power supply
2, 10, 14, 22
V
CC
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y (0–9) is enabled
via the G input. These outputs can be disabled to a logic-low state by de-asserting the G control
input. Each output has an integrated 25 Ω series-damping resistor.
3, 4, 5, 8, 9,
15, 16, 17, 20, 21
1Y (0–9)
GND
G
OUT
GND
IN
6, 7, 18, 19
11
Ground
Output bank enable. G is the output enable for outputs 1Y (0–9). When G is LOW, outputs 1Y
(0–9) are disabled to a logic LOW state. When G is HIGH, all outputs 1Y (0–9) are enabled and
switch at the same frequency as CLK.
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency
as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL.
FBOUT has an integrated 25 Ω series-damping resistor.
12
13
23
FBOUT
FBIN
OUT
IN
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be
hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so
that there is nominally zero phase error between CLK and FBIN.
Analog power supply. AV provides the power reference for the analog circuitry. In addition,
CC
AV can be used to bypass the PLL for test purposes. When AV is strapped to ground, PLL
AV
PWR
CC
CC
CC
is bypassed and CLK is buffered directly to the device outputs.
Clock input. CLK provides the clock signal to be distributed by the PCK2510S clock driver. CLK
is used to provide the reference signal to the integrated PLL that generates the clock output
signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock.
Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required
for the PLL to phase lock the feedback signal to its reference signal.
24
CLK
IN
FUNCTION TABLE
INPUTS
OUTPUTS
G
X
L
CLK
1Y (0–9)
FBOUT
L
H
H
L
L
L
H
H
H
H
3
1999 Dec 13
Philips Semiconductors
Product specification
50–150 MHz 1:10 SDRAM clock driver
PCK2510S
FUNCTIONAL BLOCK DIAGRAM
11
G
3
4
1Y0
1Y1
1Y2
5
8
9
1Y3
1Y4
15
16
1Y5
1Y6
17
1Y7
24
CLK
20
21
12
PLL
1Y8
13
FBIN
1Y9
23
AV
CC
FBOUT
SW00383
1, 3
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER
AV Supply voltage range
LIMITS
CONDITION
UNIT
MIN
–0.5
–0.5
–0.5
–65
MAX
Note 2
< V + 0.7
V
V
CC
CC
V
Supply voltage range
+4.6
–50
6.5
CC
IK
I
Input clamp current
V < 0
I
mA
V
V
I
Input voltage range
Note 3
I
Output clamp current
V
O
> V or V < 0
±50
mA
V
OK
CC
O
V
O
Output voltage range
Notes 3, 4
= 0 to V
CC
V
CC
+ 0.5
I
DC output source or sink current
Storage temperature range
Power dissipation per package
V
O
±50
mA
°C
mW
O
T
+150
700
STG
P
TOT
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. AV must not exceed V
CC
CC
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
4. This value is limited to 4.6 V maximum.
4
1999 Dec 13
Philips Semiconductors
Product specification
50–150 MHz 1:10 SDRAM clock driver
PCK2510S
1
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MAX
MIN
3
V
CC
, AV
Supply voltage
3.6
V
V
CC
V
IH
HIGH level input voltage
2
V
IL
LOW level input voltage
0
0.8
V
V
I
Input voltage
0
V
CC
V
T
amb
Operating ambient temperature range in free air
0
+70
°C
NOTE:
1. Unused inputs must be held high or low to prevent them from floating.
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
LIMITS
TYP
SYMBOL
PARAMETER
UNIT
AV , V (V)
OTHER
I = –18 mA
MIN
MAX
CC
CC
V
IK
Input clamp voltage
3
–1.2
V
V
I
MIN to MAX
I
= – 100 µA
V
– 0.2
OH
CC
3
I
= – 12 mA
2.1
V
OH
HIGH level output voltage
LOW level output voltage
OH
3
I
= – 6 mA
= 100 µA
= 12 mA
2.4
–
OH
MIN to MAX
I
0.2
0.8
0.55
±5
OL
3
3
I
–
V
OL
V
OL
I
OL
= 6 mA
–
I
I
Input current
3.6
V = V or GND
µA
µA
µA
µA
I
CC
V = V or GND;
= 0, outputs: LOW or HIGH
I
CC
I
Quiescent supply current
3.6
10
50
CC
I
O
I
AV power supply current
AV = 3.3
30
CCA
CC
CC
Additional supply current per
input pin
One input at V – 0.6 V;
CC
other inputs at V or GND
∆I
CC
3.3 to 3.6
500
CC
C
Input capacitance
Output capacitance
3.3
3.3
V = V or GND
2.8
5.4
pF
pF
I
I
CC
C
V = V or GND
O CC
O
TIMING REQUIREMENTS
Over recommended ranges of supply voltage and operating free-air temperature
SYMBOL PARAMETER
MIN
MAX
UNIT
MHz
%
f
Clock frequency
50
40
150
60
1
CLK
Input clock duty cycle
1
Stabilization time
ms
NOTE:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation
delay, skew, and jitter parameters given in the switching characteristics table are not applicable.
5
1999 Dec 13
Philips Semiconductors
Product specification
50–150 MHz 1:10 SDRAM clock driver
PCK2510S
SWITCHING CHARACTERISTICS
1
Over recommended ranges of supply voltage and operating free-air temperature; C = 30 pF
L
V
, AV = 3.3 V ±0.3 V
CC
CC
FROM
(INPUT)/CONDITION
TO
(OUTPUT)
PARAMETER
UNIT
MIN
–100
–125
–50
TYP
MAX
100
125
50
CLKIN↑ = 100 MHz to 133 MHz
CLKIN↑ = 66 MHz
FBIN↑
FBIN↑
ps
ps
ps
ps
2
t
phase error
3
t
– jitter
CLKIN↑ = 100 MHz to 133 MHz
Any Y or FBOUT
FBIN↑
phase error
t
Any Y or FBOUT
200
80
SK(0)
jitter
jitter
–80
(peak-peak)
(cycle-cycle)
CLKIN = 100 MHz to 133 MHz
Any Y or FBOUT
ps
|65|
Duty cycle reference
F(CLKIN > 60 MHz)
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
47
2.5
2.5
53
1
%
t
r
V
O
V
O
= 0.4 V to 2 V
= 0.4 V to 2 V
V/ns
V/ns
t
f
1
NOTES:
1. These parameters are not production tested.
2. This is considered as static phase error.
3. Phase error does not include jitter. (t
= static phase error – jitter
)
(cycle-cycle)
phase error
4. The t
specification is only valid for equal loading of all outputs.
SK(0)
PARAMETER MEASUREMENT INFORMATION
3V
0V
50% V
2V
INPUT
CC
t
pe
FROM OUTPUT
UNDER TEST
V
V
OH
OL
2V
50% V
CC
OUTPUT
500Ω
0.4V
0.4V
t
30pF
t
r
f
LOAD CIRCUIT FOR OUTPUTS
VOLTAGE WAVEFORMS & PHASE ERROR TIMES
NOTES:
1.
C includes probe and jig capacitance.
L
2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100MHz, Z = 50Ω , t ≤ 1.2ns, t ≤ 1.2ns.
O
r
f
3. The outputs are measured one at a time with one transition per measurement.
SW00384
Figure 1. Load Circuit and Voltage Waveforms
6
1999 Dec 13
Philips Semiconductors
Product specification
50–150 MHz 1:10 SDRAM clock driver
PCK2510S
CLKIN
FBIN
t
phase error
FBOUT
ANY Y
t
SK(0)
ANY Y
ANY Y
t
SK(0)
SW00385
Figure 2. Phase Error and Skew Calculations
7
1999 Dec 13
Philips Semiconductors
Product specification
50–100 MHz 1:10 SDRAM clock driver
PCK2510S
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
8
1999 Dec 13
Philips Semiconductors
Product specification
50–100 MHz 1:10 SDRAM clock driver
PCK2510S
NOTES
9
1999 Dec 13
Philips Semiconductors
Product specification
50–100 MHz 1:10 SDRAM clock driver
PCK2510S
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 12-99
Document order number:
9397 750 06707
Philips
Semiconductors
相关型号：
PCK2510SPWDH
IC PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, 4.40 MM, PLASTIC, MO-153, SOT-355-1, TSSOP-24, Clock Driver
NXP
©2020 ICPDF网 联系我们和版权申明