PCK12439D-T [NXP]
IC 800 MHz, OTHER CLOCK GENERATOR, PDSO28, SO-28, Clock Generator;型号: | PCK12439D-T |
厂家: | NXP |
描述: | IC 800 MHz, OTHER CLOCK GENERATOR, PDSO28, SO-28, Clock Generator 时钟 光电二极管 外围集成电路 晶体 |
文件: | 总2页 (文件大小:71K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
25-800 MHz Differential PECL
Clock Generator Family
PCK12429
The PCK12429 provides a fully integrated crystal oscillator,
PLL with integrated loop filter, and programmable frequency
divider ratios to generate a high-quality, low-jitter differential
PECL output clock from an external quartz crystal reference.
S e m i c o n d u c t o r s
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
S_CLOCK
S_DATA
NC
N[1]
N[0]
M[8]
M[7]
M[6]
M[5]
M[4]
S_LOAD
Description
PLL-V
PLL-V
CC
CC
PCK12429BD
The PCK12429 uses an external quartz crystal reference frequency with
an input range of 10-20 MHz to generate one output with a frequency
between 25 and 400 MHz, programmable through either serial or parallel
interface. In the typical case of a 16 MHz crystal, the PCK12429 derives an
internal reference frequency of 1 MHz, which drives an internal PLL. The
loop divider ratio, M, is programmable between 200 and 400 to create a
VCO output frequency between 200 MHz and 400 MHz. TheVCO output
frequency can then be further divided by the output divider ratio N, which
can be programmed to values of 1, 2, 4 or 8, for an overall output frequency
range of 25 MHz (M=200, N=8) up to 400 MHz (M=400, N=1).
NC
NC
XTAL1
Features
•
•
•
•
One 25-400 MHz differential PECL clock output
25 pꢀ peak-to-peak output ꢁitter
Fully integrated PLL and loop filter - no external componentꢀ needed
Integrated ꢀerieꢀ-reꢀonant cryꢀtal oꢀcillator - no external componentꢀ
needed beꢀideꢀ cryꢀtal
The PCK12429 has a fully integrated PLL loop filter and uses a pure
series-resonant crystal oscillator, eliminating the need for external components.
It uses separate voltage supplies to minimize noise-induced jitter. The resulting
output is a high-quality differential PECL output clock signal with extremely
low jitter of 25 ps peak-to-peak. Frequency lock is achieved in less than
10 ms with minimal frequency overshoot.
•
•
•
•
•
Frequency programmable to 1 MHz or finer reꢀolution
Parallel or 3-wire ꢀerial programming interface
Synchronouꢀ output enable
Synchronouꢀ frequency ramp-down on power-down (PCK12439)
Offered in 28-pin PLCC, 32-pin LQFP and 28-pin SO packageꢀ
Pin Configuration
M [0]
The basic function in this family is PCK12429, programmable from 25 MHz to
400 MHz. PCK12429S adds spread spectrum capability. For operation from 50
MHz to 800 MHz, PCK12430 can be used, or PCK12439 which adds a gradual
frequency step-down function supporting system power-down modes.
1
2
28 P_LOAD
M [1]
M [2]
M [3]
27
26
25
V
CC
3
XTAL2
XTAL1
4
M [4]
M [5]
5
24 NC
23
22 PLL-V
6
NC
25
V
CC
5
6
XTAL2
OE
Applications
24 FOUT
23 FOUT
22 GND
M [6]
M [7]
M [8]
N [0]
7
CC
7
P_LOAD
M [0]
8
21 S_LOAD
20 S_DATA
19 S_CLOCK
•
•
•
High-performance UNIX computing platforms
8
PCK12429A
9
™
IA-64 Itanium 2 architecture ꢀerver motherboardꢀ
21
V
CC
9
M [1]
10
20 TEST
19 GND
10
11
M [2]
High-performance PECL reference clock generation
N [1] 11
GND 12
TEST 13
18
V
CC
M [3]
17 FOUT
16 FOUT
15 GND
Operating Characteristics
V
14
CC
•
•
•
•
Operates from a 3.3V power supply
0°C to +70°C operating temperature range
Input crystal frequency range between 10 MHz and 20 MHz
Serial programming interface operates at up to 10 MHz
Order Information
Package
SO
Container
Tube
T & R
T & R
Tray, single
PCK12429
PCK12429S
PCK12430
PCK12439
PCK12429D
PCK12429D-T
PCK12429BD-T
PCK12429BD
PCK12429BD
PCK12429A
PCK12429SD
PCK12429SD-T
PCK12429SBD-T
PCK12429SBD
PCK12429SBD
PCK12429SA
PCK12430D
PCK12430D-T
PCK12430BD-T
PCK12430BD
PCK12430BD
PCK12430A
PCK12439D
PCK12439D-T
PCK12439BD-T
PCK12439BD
PCK12439BD
PCK12439A
LQFP
PLCC
Tray, multiple
Tube
T & R
PCK12429A-T
PCK12429SA-T
PCK12430A-T
PCK12439A-T
PCK12429
25-800 MHz Differential PECL Clock Generator Family
w w w . s e m i c o n d u c t o r s . p h i l i p s . c o m
F
F
Functional Block Diagram
Example of a PECL Clock Tree
Using PCK12429 with Several
Clock Distribution ICs
OUT 1-1
OUT 1-2
PCK111
1:10
PCK12429/29S/30/39
16 MHz
F
OUT 1-10
Crystal
Oscillator
DIV
16
DIV
N
PLL
FOUT
F
F
OUT 2-1
OUT 2-2
F
F
F
F
F
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
PCK111
1:10
F
OUT
PCK12429
25..400MHz
PCKEP14
1:5
synchronous
output enable
F
OUT 2-10
DIV
M
F
OUT 4-1
Serial Data
Programming Interface
PCK210
2x1:5
F
F
OUT 4-5
OUT 5-1
F
OUT 5-5
M (9 bits)
N (2 bits)
Divider ratios and output frequency ranges*
Jitter Performance as a Function of Output Frequency
25
20
15
10
5
Output
Division
Ratio
PLL
Division
Ratio
Frequency
Step
Increment
N
M
Output
Frequency
1 1001 0000
…
0 1100 1000
1 1001 0000
…
0 1100 1000
1 1001 0000
…
0 1100 1000
1 1001 0000
…
400
…
200
400
…
200
400
…
200
400
…
400
…
200
200
…
RMS jitter [ps]
00
1
2
4
8
1 MHz
500 kHz
250 kHz
125 kHz
6.25 ps reference (1-sigma)
01
10
11
100
100
6.25
50
50
0
0 1100 1000
200
25
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
Output Frequency [MHz]
* using a 16 MHz crystal as an example reference frequency
Philips Semiconductors
Family Overview
Part Number Function
PCK12429
PCK12429S
Philips Semiconductors is a worldwide company with over 100 sales offices
in more than 50 countries. For a complete up-to-date list of our sales offices
please e-mail sales.addresses@www.semiconductors.philips.com.
A complete list will be sent to you automatically. You can also visit our
website http://www.semiconductors.philips.com/sales
25-400 MHz differential PECL clock generator
25-400 MHz differential PECL clock generator
with spread spectrum
50-800 MHz differential PECL clock generator
50-800 MHz differential PECL clock generator
with frequency ramp-down mode
PCK12430
PCK12439
© Koninklijke Philips Electronics N.V. 2002
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent
of the copyright owner.The information presented in this document does not form part of any quo-
tation or contract, is believed to be accurate and reliable and may be changed without notice. No lia-
bility will be accepted by the publisher for any consequence of its use. Publication thereof does not
convey nor imply any license under patent- or other industrial or intellectual property rights.
Date of release: August 2002
document order number: 9397 750 10201
Published in U.S.A.
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