PCK2000 [NXP]
CK97 66/100MHz System Clock Generator; CK97 66 / 100MHz的系统时钟发生器
| 型号： | PCK2000 |
| 厂家： | 
NXP |
| 描述： | CK97 66/100MHz System Clock Generator |
| 文件： | 总14页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
PCK2000
CK97 (66/100MHz) System Clock
Generator
Product specification
1998 Sep 29
Philips
Semiconductors
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
FEATURES
PIN CONFIGURATION
• Mixed 2.5V and 3.3V operation
• Four CPU clocks at 2.5V
1
2
3
48
47
REF0
REF1
V
DDREF
REF2
• Eight synchronous PCI clocks at 3.3V, one free-running
• Two 2.5V IOAPIC clocks @ 14.318 MHz
• Two 3.3V 48MHz USB clock outputs
• Three 3.3V reference clocks @ 14.318 MHz
• Reference 14.31818 MHz Xtal oscillator input
• 100 MHz or 66 MHz operation
46
45
V
V
DDAPIC
SSREF
4
5
XTAL_IN
IOAPIC0
XTAL_OUT
44 IOAPIC1
6
7
43
42
41
V
V
SSAPIC
SSPCI0
PCICLK_F
PCICLK1
RESERVED
8
V
DDCPU0
• Part provides frequencies for Pentium Pro and
9
40
39
V
CPUCLK0
CPUCLK1
DDPCI0
Pentium II motherboards
PCICLK2
PCICLK3
10
11
12
• Power management control input pins
• 175 ps CPU clock jitter
V
38
37
36
35
34
33
32
31
30
29
28
SSCPU0
V
V
DDCPU1
SSPCI1
• 175 ps skew on outputs
PCICLK4 13
PCICLK5 14
CPUCLK2
CPUCLK3
• 1.5 – 4 ns CPU–PCI delay
V
V
DDPCI1
SSCPU1
• Power down if PWRDWN is held LOW
• Available in 48-pin SSOP package
• See PCK2000M for 28-pin mobile version
15
16
17
18
19
20
21
PCICLK6
PCICLK7
V
V
DDCORE1
SSCORE1
V
SSPCI2
PCISTOP
V
CPUSTOP
DESCRIPTION
The PCK2000 is a clock synthesizer/driver chip for a Pentium Pro or
other similar processors.
DDCORE0
V
PWRDWN
SSCORE0
48MHz
V
RESERVED
DD
The PCK2000 has four CPU clock outputs at 2.5V. There are eight
PCI clock outputs running at 33MHz. One of the PCI clock outputs is
free-running. Additionally, the part has two 3.3V USB clock outputs
at 48MHz, two 2.5V IOAPIC clock outputs at 14.318MHz, and three
3.3V reference clock outputs at 14.318MHz. All clock outputs meet
Intel’s drive strength, rise/fall time, jitter, accuracy, and skew
requirements.
22
27
26
25
48MHz0
48MHz1
48MHz
SEL0
SEL1
23
24
V
SEL100/66
SS
SW00237
The part possesses dedicated powerdown, CPUSTOP, and
PCISTOP input pins for power management control. These inputs
are synchronized on-chip and ensure glitch-free output transitions.
When the CPUSTOP input is asserted, the CPU clock outputs are
driven LOW. When the PCISTOP input is asserted, the PCI clock
outputs are driven LOW, except for free running PCICLK_F clock
output..
Finally, when the PWRDWN input pin is asserted, the internal
reference oscillator and PLLs are shut down, and all outputs are
driven LOW.
The PCK2000 is available in a 48–pin SSOP package.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA NORTH AMERICA
PCK2000 DL PCK2000 DL
DRAWING NUMBER
48-Pin Plastic SSOP
0°C to +70°C
SOT370-1
Intel and Pentium are registered trademarks of Intel Corporation.
2
1998 Sep 29
853-2129 20102
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1, 2, 47
REF [0–2]
14.318 MHz clock outputs
GROUND for REF outputs
POWER for REF outputs
14.318 MHz crystal input
14.318 MHz crystal output
GROUND for PCI outputs
Free-running PCI output
POWER for PCI outputs
PCI clock outputs.
3
V
SSREF
V
DDREF
48
4
XTAL_IN
5
XTAL_OUT
6, 12, 18
V
SSPCI
[0–2]
7
PCICLK_F
V [0–1]
DDPCI
9, 15
8, 10, 11, 13, 14, 16, 17
PCICLK [1–7]
19, 33
20, 32
21
V
[0–1]
[0–1]
Isolated POWER for core
Isolated GROUND for core
POWER for 48MHz outputs
DDCORE
V
SSCORE
V
DD
48MHz
24
V
48MHz
GROUND for 48MHz outputs
48MHz outputs
SS
22, 23
26, 27
48MHz [0–1]
SEL0,1
Logic select pins.
Select pin for enabling 66 MHz or 100MHz. L = 66 MHz
H = 100MHz
25
SEL100/66
29
30
PWRDWN
CPUSTOP
PCISTOP
Control pin to put device in powerdown state, active low
Control pin to disable CPU clocks, active low
Control pin to disable PCI clocks, active low
POWER for CPU outputs
31
37, 41
34, 38
35, 36, 39, 40
43
V
[0–1]
[0–1]
DDCPU
V
GROUND for CPU outputs
SSCPU
CPUCLK [0–3]
CPU clock outputs @2.5V
V
GROUND for IOAPIC outputs
POWER for IOAPIC outputs
SSAPIC
V
DDAPIC
46
44, 45
28, 42
IOAPIC [0–1]
RESERVED
IOAPIC output @ 2.5V
Reserved for future use
NOTES:
1. V and V names in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on
DD
SS
the performance of the device. In reality, the platform will be configured with the V
and V
pins tied to a 2.5V supply, all
DDAPIC
DDCPU
remaining V pins tied to a common 3.3V supply and all V pins being common.
DD
SS
3
1998 Sep 29
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
BLOCK DIAGRAM
REFCLK [0–2](14.318 MHz)
IOAPIC [0–1](14.318 MHz)
X
X
PWRDWN
LOGIC
XTAL_IN
X
X
14.318
MHZ
OSC
PWRDWN
LOGIC
XTAL_OUT
X
X
PLL2
PLL1
48MHz [0–1](48MHz)
STOP
LOGIC
CPUCLK [0–3] (100MHz/66MHz)
PCICLK_F (33MHz)
PWRDWN
LOGIC
X
X
SEL0 X
SEL1 X
LOGIC
X
SEL100/66
STOP
LOGIC
PCICLK [1–7](33MHz)
CPUSTOP
X
PCISTOPX
X
PWRDWN
SW00236
SELECT FUNCTIONS
SEL100/66
SEL1
SEL0
FUNCTION
TRI-State
NOTES
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
Reserved
Reserved
Active 66MHz
Test mode
Reserved
1
Reserved
Active 100MHz
NOTE:
1. Internal decode logic for all three select inputs implemented.
OUTPUTS
FUNCTION
DESCRIPTION
CPU
HI-Z
PCI, PCI_F
HI-Z
48MHz
HI-Z
REF
IOAPIC
HI-Z
NOTES
3-STATE
HI-Z
TEST MODE
TCLK/2
TCLK/6
TCLK/2
TCLK
TCLK
NOTE:
1. TCLK is a test clock driven in on the XTAL_IN input in Test Mode.
4
1998 Sep 29
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
FUNCTION TABLE
CPICLK (1–7)
PCICLK_F
(MHz)
REF (0–2)
IOAPIC (0–1)
(MHz)
CPUCLK (0–3)
(MHz)
SEL 100/66
CPU/PCI RATIO
48MHz (0–1)
0
1
2
3
66.66
100
33.33
33.33
14.318
14.318
48
48
CLOCK ENABLE CONFIGURATION
OTHER
CPUSTOP
PCISTOP
PWRDWN
CPUCLK
PCICLK
PCICLK_F
PLLs
OSCILLATOR
CLOCKS
Stopped
Running
Running
Running
Running
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
LOW
LOW
LOW
LOW
LOW
OFF
OFF
33MHz
33MHz
33MHz
33MHz
Running
Running
Running
Running
Running
Running
Running
Running
LOW
33MHz
LOW
100/66MHz
100/66MHz
33MHz
POWER MANAGEMENT REQUIREMENTS
LATENCY
SIGNAL
SIGNAL STATE
NO. OF RISING EDGES OF FREE RUNNING
PCICLK
CPUSTOP
PCISTOP
0 (DISABLED)
1 (ENABLED)
0 (DISABLED)
1 (ENABLED)
1
1
1
1
PWRDWN
1 (NORMAL OPERATION)
0 (POWER DOWN)
3ms
2 MAX
NOTES:
1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the
first valid clock that comes out of the device.
2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.
5
1998 Sep 29
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
1, 2
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to V (V = 0V)
SS
SS
LIMITS
SYMBOL
PARAMETER
CONDITION
UNIT
MIN
–0.5
–0.5
–0.5
MAX
+4.6
+4.6
+3.6
–50
V
DC 3.3V core supply voltage
DC 3.3V I/O supply voltage
DC 2.5V I/O supply voltage
DC input diode current
V
V
DD3
V
DDQ3
V
DDQ2
V
I
V < 0
mA
V
IK
I
V
I
DC input voltage
Note 2
–0.5
–0.5
–65
5.5
I
DC output diode current
DC output voltage
V
> V or V < 0
±50
mA
V
OK
O
CC
O
V
Note 2
V
+ 0.5
O
CC
I
O
DC output source or sink current
Storage temperature range
V
>= 0 to V
CC
±50
mA
°C
O
T
STG
+150
Power dissipation per package
plastic medium-shrink (SSOP)
For temperature range: –40 to +125°C
above +55°C derate linearly with 11.3mW/K
P
TOT
850
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
3.135
3.135
2.135
0
MAX
3.465
3.465
2.625
V
DC 3.3V core supply voltage
DC 3.3V I/O supply voltage
DC 2.5V I/O supply voltage
DC input voltage range
Note 1
Note 2
Note 3
V
V
V
V
DD3
V
DDQ3
DDQ2
V
V
I
V
DD3
V
V
DDQ2
DDQ3
V
DC output voltage range
0
0
V
O
T
amb
Operating ambient temperature range in free air
+70
°C
NOTES:
1. V
2. V
3. V
= V
= V
= 3.3V
DD3
DDCORE1
DDCORE2
= V
= V
= V
= V
= V
= 2.5V
= 3.3V
DDQ3
DDQ2
DDREF
DDAPIC
DDPCI0
DDPCI1
DD48MHz
= V
= V
DDCPU0
DDCPU1
6
1998 Sep 29
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
DC CHARACTERISTICS
LIMITS
= 0°C to +70°C
TEST CONDITIONS
T
amb
UNIT
SYMBOL
PARAMETER
V
(V)
DD
OTHER
MIN
TYP
MAX
+ 0.3
V
DDQ2
V
DDQ3
V
DDQ3
= 2.5V
±5%
V
HIGH level input voltage
LOW level input voltage
3.135 to 3.465
2.0
V
DD
V
V
V
V
V
V
IH
= 3.3V
±5%
V
3.135 to 3.465
2.375 to 2.625
2.375 to 2.625
3.135 to 3.465
3.135 to 3.465
V
– 0.3
0.8
IL
SS
2.5V output HIGH voltage
CPUCLK, IOAPIC
= 3.3V
±5%
V
OH2
I
I
= –1mA
= 1mA
2.0
–
–
OH
2.5V output LOW voltage
CPUCLK, IOAPIC
V
I
OL
0.4
–
OL2
OH3
3.3V output HIGH voltage
REF, 48MHz
V
= –1mA
2.0
–
OH
3.3V output LOW voltage
REF, 48MHz
V
OL3
I
OL
= 1mA
0.4
V
PCI output HIGH voltage
PCI output LOW voltage
3.135 to 3.465
3.135 to 3.465
2.375
I
= –1mA
2.4
–
–
0.55
–
V
V
POH
OH
V
I
= 1mA
POL
OL
V
= 1.0V
= 2.375V
= 1.4V
–27
–
OUT
CPUCLK
output HIGH current
I
mA
mA
mA
mA
mA
mA
mA
mA
OH
2.625
V
–27
–
OUT
2.375
V
V
V
–36
–
OUT
OUT
OUT
IOAPIC
output HIGH current
I
I
I
OH
OH
OH
2.625
= 2.5V
–21
–
3.135
= 1.0V
–29
–
48MHz, REF
output HIGH current
3.465
V
= 3.135V
= 1.0V
–23
–
OUT
3.135
V
–33
–
OUT
PCI
output HIGH current
3.465
V
= 3.135V
= 1.2V
–33
–
OUT
2.375
V
V
V
V
27
–
OUT
OUT
OUT
OUT
CPUCLK
output LOW current
I
I
I
I
OL
OL
OL
OL
2.625
= 0.3V
30
–
2.375
= 1.0V
36
–
IOAPIC
output LOW current
2.625
= 0.2V
31
–
3.135
V
OUT
= 1.95V
= 0.4V
29
–
48MHz, REF
output LOW current
3.465
V
27
–
OUT
3.135
V
OUT
= 1.95V
= 0.4V
30
–
PCI
output LOW current
3.465
V
38
5
OUT
±I
I
Input leakage current
3.465
–
µA
µA
pF
pF
3-State output OFF-State
current
V
dd
=
OUT
±I
3.465
I
= 0
–
10
5
OZ
O
V
or GND
Cin
Input pin capacitance
Xtal pin capacitance, as
seen by external crystal
Cxtal
Cout
18
Output pin capacitance
Operating supply current
Powerdown supply current
Operating supply current
Powerdown supply current
6
pF
mA
mA
µA
1
1
66MHz mode
100MHz mode
Outputs loaded
Outputs loaded
170
170
500
72
I
I
3.465
2.625
dd3
All static inputs to V
or GND
DD
1
66MHz mode
100MHz mode
Output loaded
Output loaded
mA
mA
µA
1
100
100
dd2
All static inputs to V
or GND
DD
NOTE:
1. All clock outputs loaded with maximum lump capacitance test load specified in AC characteristics section.
7
1998 Sep 29
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
AC CHARACTERISTICS
VDDREF = VDDPCI (0–1) = VDD48MHz = 3.3V ± 5%; VDDAPIC = VDDCPU (0–1) = 2.5V ± 5%; f
= 14.31818 MHz
LIMITS
crystal
CPU CLOCK OUTPUTS, CPU(0–3) (LUMP CAPACITANCE TEST LOAD = 20pF)
TEST CONDITIONS
T
amb
= 0°C to +70°C
SYMBOL
PARAMETER
UNIT
NOTES
MIN
15.0
5.2
MAX
T
(t )
CPUCLK period
CPUCLK HIGH time
CPUCLK LOW time
CPUCLK period
2
1, 5
1, 5
2
15.5
HKP
P
T
HKH
(t )
H
66MHz
ns
T
(t )
L
5.0
HKL
HKP
HKH
T
(t )
P
10.0
3.0
10.5
T
(t )
H
CPUCLK HIGH time
CPUCLK LOW time
CPUCLK rise time
100MHz
1, 5
1, 5
9
ns
T
(t )
L
2.8
HKL
T
(t )
R
0.4
1.6
1.6
175
55
ns
ns
ps
%
HRISE
T
(t )
CPUCLK fall time
9
0.4
HFALL
F
T
(t
)
CPUCLK jitter
JITTER JC
DUTY CYCLE (t )
Output Duty Cycle
1
2
7
45
D
T
(t
)
CPU Bus CLK skew
CPUCLK stabilization from Power-up
175
3
ps
ms
HSKW SK
T
(f
)
HSTB ST
PCI CLOCK OUTPUTS, PCI(0–7) (LUMP CAPACITANCE TEST LOAD = 30pF)
LIMITS
= 0°C to +70°C
TEST CONDITIONS
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
MIN
MAX
T
(t )
PCICLK period
PCICLK period stability
PCICLK HIGH time
3
8
30.0
ns
ps
ns
ns
ns
ns
ps
ns
ms
PKP
P
T
500
PKPS
T
PKH
(t )
H
1
12.0
12.0
0.5
T
(t )
L
PCICLK LOW time
1
PKL
T
(t )
R
PCICLK rise time
10
10
2
2.0
2.0
500
4.0
3
HRISE
T
(t )
F
PCICLK fall time
0.5
HFALL
T
(t
)
PCI Bus CLK skew
PSKW SK
T
(t )
CPUCLK to PCICLK Offset
PCICLK stabilization from Power-up
2, 4
7
1.5
HPOFFSET
O
T
(f
)
PSTB ST
APIC(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)
LIMITS
= 0°C to +70°C
TEST CONDITIONS
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
MIN
MAX
Frequency generated
by Crystal
f
Frequency, Actual
14.31818
MHz
T
(t )
Output rise edge rate
Output fall edge rate
1
1
4
4
ns
ns
%
HRISE
R
T
(t )
F
HFALL
DUTY CYCLE (t )
Duty Cycle
45
55
3
D
T
(f
)
Frequency stabilization from Power-up (cold start)
ms
HSTB ST
8
1998 Sep 29
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
REF(0–2) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)
LIMITS
= 0°C to +70°C
TEST CONDITIONS
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
MIN
MAX
Frequency generated
by Crystal
f
Frequency, Actual
14.31818
MHz
T
(t )
Output rise edge rate
Output fall edge rate
1
1
4
4
ns
ns
%
HRISE
R
T
(t )
F
HFALL
DUTY CYCLE (t )
Duty Cycle
45
55
3
D
T
(f
)
Frequency stabilization from Power-up (cold start)
ms
HSTB ST
48MHZ(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)
LIMITS
= 0°C to +70°C
TEST CONDITIONS
T
amb
SYMBOL
PARAMETER
UNIT
NOTES
MIN
MAX
Determined by PLL
divider ratio
f
Frequency, Actual
48.008
+167
MHz
f
Devation from 48MHz
Output rise edge rate
(48.008 – 48)/48
ppm
ns
D
T
(t )
1
1
4
4
HRISE
R
T
(t )
F
Output fall edge rate
ns
HFALL
DUTY CYCLE (t )
Duty Cycle
45
55
3
%
D
T
(f
)
Frequency stabilization from Power-up (cold start)
ms
HSTB ST
ALL CLOCK OUTPUTS
LIMITS
= 0°C to +70°C
TEST CONDITIONS
NOTES
T
SYMBOL
PARAMETER
amb
UNIT
MIN
1.0
MAX
8.0
T
T
, T
Output enable time
Output disable time
ns
ns
PZL PZH
, T
PLZ PHZ
1.0
8.0
NOTES:
1. See Figure 3 for measure points.
2. Period, jitter, offset, and skew are measured on the rising edge @ 1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks.
3. The PCICLK is the CPUCLK divided by two at CPUCLK = 66.6MHz. PCICLK is the CPUCLK divided by three at CPUCLK = 100MHz.
4. The CPUCLK must always lead the PCICLK as shown in Figure 2.
5. T
6. T
is measured @ 2.0V as shown in Figure 4.
is measured @ 0.4V as shown in Figure 4.
HKH
HKL
7. The time is specified from when V
achieves its nominal operating level (typical condition is V
= 3.3V) until the frequency output is
DDQ
DDQ
stable and operating within specification.
8. Defined as once the clock is at its nominal operating frequency, the adjacent period changes cannot exceed the time specified.
9. T
10.T
and T
and T
are measured as a transition through the threshold region V = 0.4V and V = 2.0V (1mA) JEDEC specification.
OL OH
HRISE
HRISE
HFALL
HFALL
(48MHz, REF, PC) are measured as a transition through the threshold region V = 0.4V and V = 2.4V
OL
OH
9
1998 Sep 29
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
AC WAVEFORMS
V
V
V
V
= 1.25V @ V
and 1.5V @ V
M
X
Y
DDQ2 DDQ3
= V + 0.3V
V
OL
I
= V –0.3V
OH
and V are the typical output voltage drop that occur with the
OL
OH
V
SEL 100, 66,
SEL1, SEL0
M
output load.
GND
V
DDQ2
t
t
PZL
PLZ
1.25V
V
DD
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
V
CPUCLK
SS
V
M
V
X
V
OL
DDQ2
1.25V
t
t
PZH
PHZ
CPUCLK
V
SS
V
OH
OUTPUT
V
Y
HIGH-to-OFF
OFF-to-HIGH
V
M
T
HSKW
V
SS
SW00240
outputs
enabled
outputs
enabled
outputs
disabled
Figure 1. CPUCLK to CPUCLK skew
SW00239
Figure 4. 3-State enable and disable times.
V
DDQ2
1.25V
COMPONENT
MEASUREMENT
POINTS
V
V
CPUCLK
PCICLK
SS
2.5VOLT MEASURE POINTS
V
DDQ2
DDQ3
V
= 2.0V
OH
V
= 1.7V
IH
1.25V
1.5V
V
= 0.7V
IL
V
= 0.4V
OL
V
SS
V
SS
SYSTEM
MEASUREMENT
POINTS
T
HPOFFSET
COMPONENT
MEASUREMENT
POINTS
SW00241
3.3VOLT MEASURE POINTS
Figure 2. CPUCLK to PCICLK offset
V
DDQ3
V
= 2.4V
OH
V
= 2.0V
IH
1.5V
= 0.7V
V
IL
V
= 0.4V
OL
T
HKP
V
SS
SYSTEM
MEASUREMENT
POINTS
DUTY CYCLE
T
HKH
2.0
1.25
0.4
SW00243
2.5V CLOCKING
INTERFACE
Figure 5. Component versus system measure points
T
HKL
T
T
FALL
RISE
T
PKP
T
PKH
2.4
3.3V CLOCKING
INTERFACE
(TTL)
1.5
0.4
T
PKL
T
T
FALL
RISE
SW00242
Figure 3. 2.5V/3.3V Clock waveforms
10
1998 Sep 29
Philips Semiconductors
Product specification
PCK2000
CK97 (66/100MHz) System Clock Generator
CPUSTOP
CPUCLK
(INTERNAL)
PCICLK
(INTERNAL)
PCICLK
(FREE-RUNNING)
CPUSTOP
CPUCLK
(EXTERNAL)
PCISTOP
CPUCLK
(INTERNAL)
PCICLK
(INTERNAL)
PCICLK
(FREE-RUNNING)
PCISTOP
PCICLK
(EXTERNAL)
PWRDWN
CPUCLK
(INTERNAL)
PCICLK
(INTERNAL)
PWRDWN
CPUCLK
(EXTERNAL)
PCICLK
(EXTERNAL)
VCO
CRYSTAL
SW00244
Figure 6. Power Management
11
1998 Sep 29
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
12
1998 Sep 29
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
NOTES
13
1998 Sep 29
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397–750-04605
Document order number:
Philips
Semiconductors
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