PCK2001DL,112 [NXP]
PCK2001 - 14.318-150 MHz I2C 1:18 clock buffer SSOP 48-Pin;
| 型号： | PCK2001DL,112 |
| 厂家： | 
NXP |
| 描述： | PCK2001 - 14.318-150 MHz I2C 1:18 clock buffer SSOP 48-Pin PC 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总14页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
PCK2001
14.318–150 MHz I2C 1:18 clock buffer
Product data
2002 Jun 03
Supersedes data of 1999 Jul 06
Philips
Semiconductors
Philips Semiconductors
Product data
14.318–150 MHz I2C 1:18 clock buffer
PCK2001
FEATURES
• HIGH speed, LOW noise non-inverting 1–18 buffer
• Typically used to support four SDRAM DIMMs
• Multiple V , V pins for noise reduction
DD
SS
• 3.3 V operation
• Separate 3-State pin for testing
• ESD protection exceeds 2000 V per Standard 801.2
• Optimized for 66 MHz, 100 MHz and 133 MHz operation
• 175 ps skew outputs
DESCRIPTION
The PCK2001 is a 1–18 fanout buffer used for 133/100 MHz CPU,
66/33 MHz PCI, 14.318 MHz REF, or 133/100/66 MHz SDRAM clock
distribution. 18 outputs are typically used to support up to four
SDRAM DIMMS commonly found in desktop, workstation or server
applications.
• Available in 48-pin SSOP package
• See PCK2001M for mobile (reduced pincount) 28-pin 1-10 buffer
version
All clock outputs meet Intel’s drive, rise/fall time, accuracy, and skew
2
requirements. An I C interface is included to allow each output to be
2
enabled/disabled individually. An output disabled via the I C
interface will be held in the LOW state. In addition, there is an OE
input which 3-States all outputs.
2
• Individual clock output enable/disable via I C
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
= 3.3 V; C = 30 pF
TYPICAL
UNIT
t
t
Propagation delay
2.5
2.5
PLH
PHL
V
ns
CC
L
BUF_IN to BUF_OUT
Rise time
n
t
r
V
CC
V
CC
V
CC
= 3.3 V, C = 30 pF
1.0
700
50
ns
ps
µA
L
t
f
Fall time
= 3.3 V, C = 20 pF
L
I
Total supply current
= 3.465 V
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
48-Pin Plastic SSOP
0 °C to +70 °C
PCK2001DL
SOT370-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN
NUMBER
I/O
TYPE
SYMBOL
FUNCTION
RESERVED
RESERVED
1
2
3
4
5
6
7
8
9
48
47
46
RESERVED
RESERVED
4, 5, 8, 9
Output BUF_OUT (0–3) Buffered clock outputs
V
V
DD9
DD0
13, 14, 17, 18 Output BUF_OUT (4–7) Buffered clock outputs
45
BUF_OUT0
BUF_OUT1
BUF_OUT15
31, 32, 35,
36
BUF_OUT
(8–11)
44 BUF_OUT14
V
Output
Output
Buffered clock outputs
Buffered clock outputs
V
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
SS0
SS9
DD8
V
V
40, 41, 44,
45
BUF_OUT
(12–15)
DD1
BUF_OUT2
BUF_OUT13
BUF_OUT12
BUF_OUT3
V
BUF_OUT
(16–17)
21, 28
11
Output
Input
Buffered clock outputs
Buffered clock input
V
SS1 10
SS8
OE
BUF_IN 11
BUF_IN
V
V
DD2 12
DD7
Active-HIGH output
enable
BUF_OUT4 13
BUF_OUT11
BUF_OUT10
38
Input
OE
BUF_OUT5 14
V
2
24
25
I/O
SDA
SCL
I C serial data
V
SS2
DD3
15
16
17
18
19
20
21
22
23
24
SS7
V
V
2
DD6
Input
I C serial clock
BUF_OUT6
BUF_OUT7
BUF_OUT9
BUF_OUT8
3, 7, 12, 16,
20, 29, 33,
37, 42, 46
Input
V
3.3 V power supply
Ground
DD (0–9)
V
V
SS3
SS6
V
V
DD4
DD5
6, 10, 15, 19,
22, 27, 30,
34, 39, 43
BUF_OUT17
BUF_OUT16
Input
Input
V
SS (0–9)
V
V
27
SS4
SS5
V
V
DDI2C
SDA
26 SSI2C
2
3.3 V I C power
25
23
V
DDI2C
SCL
supply
SW00567
2
26
Input
n/a
V
I C ground
SSI2C
2
I C is a trademark of Koninklijke Philips Electronics N.V.
1, 2, 47, 48
RESERVED
Undefined
2
2002 Jun 03
853-2072 28362
Philips Semiconductors
Product data
14.318–150 MHz I2C 1:18 clock buffer
PCK2001
FUNCTION TABLE
2
OE
L
BUF_IN
I CEN
BUF_OUTn
X
L
X
X
H
L
Z
L
H
H
H
H
H
L
H
1, 2
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to V (V = 0 V).
SS
SS
LIMITS
SYMBOL
PARAMETER
CONDITION
UNIT
MIN
MAX
+4.6
–50
5.5
V
I
DC 3.3 V supply voltage
DC input diode current
DC input voltage
–0.5
V
mA
V
DD
V < 0 V
I
IK
V
I
Note 2
–0.5
–0.5
–65
I
DC output diode current
DC output voltage
V
> V or V < 0 V
±50
mA
V
OK
O
DD
O
V
O
Note 2
>= 0 V to V
DD
V
CC
+ 0.5
I
O
DC output source or sink current
Storage temperature range
V
±50
mA
°C
O
T
stg
+150
Power dissipation per package
plastic medium-shrink SO (SSOP)
For temperature range: 0 to +70 °C
above +55 °C derate linearly with 11.3 mW/K
P
TOT
850
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
3.135
20
MAX
3.465
30
V
DD
DC 3.3 V supply voltage
V
pF
V
C
Capacitive load
L
V
I
DC input voltage range
0
V
DD
V
DD
V
O
DC output voltage range
0
V
T
amb
Operating ambient temperature range in free air
0
+70
°C
3
2002 Jun 03
Philips Semiconductors
Product data
14.318–150 MHz I2C 1:18 clock buffer
PCK2001
DC CHARACTERISTICS
LIMITS
= 0 °C to +70 °C
TEST CONDITIONS
OTHER
T
UNIT
SYMBOL
PARAMETER
amb
V
DD
(V)
MIN
2.0
– 0.3
MAX
+ 0.3
DD
V
IH
HIGH level input voltage
LOW level input voltage
3.3 V output HIGH voltage
3.3 V output LOW voltage
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
3.465
V
V
V
V
IL
V
SS
0.8
–
V
OH
I
= –1 mA
2.4
–
V
OH
V
OL
I
= 1 mA
0.4
–
V
OL
V
= 2.0 V
= 3.135 V
= 1.0 V
–54
–
mA
mA
mA
mA
µA
µA
µA
OUT
I
Output HIGH current
Output LOW current
OH
V
–46
–
OUT
V
V
54
–
OUT
OUT
I
OL
= 0.4 V
53
5
±I
I
Input leakage current
–
±I
3-State output OFF-State current
Quiescent supply current
3.465
V
OUT
= V or GND
I
I
= 0
= 0
–
10
100
OZ
CC
DD
O
I
3.465
V = V or GND
–
I
DD
O
Additional quiescent supply current
given per control pin
∆I
CC
3.135 to 3.465
V = V – 0.6 V
I
O
= 0
–
500
µA
I
DD
4
2002 Jun 03
Philips Semiconductors
Product data
14.318–150 MHz I2C 1:18 clock buffer
PCK2001
SDRAM CLOCK OUTPUT BUFFER PULL-UP CHARACTERISTICS
PULL-UP
I
VOLTAGE
(mA)
(V)
MIN
TYP
–116
–116
–110
–107
–103
–98
–90
–69
–56
–15
0
MAX
–198
–198
–188
–184
–177
–170
–157
–126
–107
–46
0
–72
–72
–68
–67
–64
–60
–54
–39
–30
0
1
1.40
1.50
1.65
1.80
2.00
2.40
2.60
3.135
3.30
3.465
–23
0
SDRAM PULL-UP
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5 2.75
3
3.25 3.5
0
–20
–40
–60
–80
MIN
TYP
MAX
–100
–120
–140
–160
–180
–200
I
(mA)
OH
V
(V)
OUT
SW00249
5
2002 Jun 03
Philips Semiconductors
Product data
14.318–150 MHz I2C 1:18 clock buffer
PCK2001
SDRAM CLOCK OUTPUT BUFFER PULL-DOWN CHARACTERISTICS
PULL-UP
I
VOLTAGE
(V)
(mA)
TYP
0
MIN
0
MAX
0
0
0.4
23
35
43
49
61
64
67
70
72
72
34
53
0.65
0.85
1.00
1.4
52
83
65
104
118
152
159
168
177
184
204
204
74
93
1.5
98
1.65
1.8
103
108
112
112
112
1.95
3.135
3.6
SDRAM PULL-DOWN
225
200
175
150
125
100
75
MIN
TYP
MAX
I
OL
(mA)
50
25
0
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
V
(V)
OUT
SW00250
6
2002 Jun 03
Philips Semiconductors
Product data
14.318–150 MHz I2C 1:18 clock buffer
PCK2001
AC CHARACTERISTICS
LIMITS
= 0 °C to +70 °C
TEST CONDITIONS
NOTES
T
amb
SYMBOL
PARAMETER
UNIT
9
MIN
15.0
5.6
5.3
10.0
3.3
3.1
7.4
2.6
2.1
1.5
1.5
1.0
1.0
1.0
1.0
45
TYP
MAX
T
T
SDRAM CLK period
1, 6
2, 6, 8
3, 6, 8
1, 6
15.2
7.8
7.4
10.01
5.1
4.9
7.5
3.2
2.8
2.0
2.9
2.5
2.5
2.6
2.7
52
15.5
8.4
8.0
10.5
5.7
5.5
7.7
3.8
3.5
4.0
4.0
3.5
3.5
5.0
5.0
55
SDKP
SDRAM CLK HIGH time
SDRAM CLK LOW time
SDRAM CLK period
66 MHz
100 MHz
133 MHz
ns
ns
ns
SDKH
T
SDKL
SDKP
SDKH
T
T
SDRAM CLK HIGH time
SDRAM CLK LOW time
SDRAM clock period
2, 6, 8
3, 6, 8
1, 6
T
SDKL
SDKP
SDKH
T
T
SDRAM CLK HIGH time
SDRAM CLK LOW time
SDRAM rise time
2, 6, 8
3, 6, 8
4, 6, 10
4, 6, 11
6, 7
T
SDKL
T
V/ns
V/ns
ns
SDRISE
SDFALL
T
SDRAM fall time
T
T
SDRAM buffer LH propagation delay
SDRAM buffer HL propagation delay
SDRAM buffer enable time
SDRAM buffer disable time
PLH
PHL
6, 7
ns
T
T
, T
6, 7
ns
PZL PZH
, T
6, 7
ns
PLZ PHZ
DUTY CYCLE Output Duty Cycle
Measured at 1.5 V
5, 6, 7
1, 6
%
T
T
SDRAM Bus CLK skew
Device to device skew
150
250
250
ps
SDSKW
ps
DDSKW
NOTES:
1. Clock period and skew are measured on the rising edge at 1.5 V.
2. T
3. T
4. T
is measured at 2.4 V as shown in Figure 4.
is measured at 0.4 V as shown in Figure 4.
SDKH
SDKL
and T
are measured as a transition through the threshold region V = 0.4 V and V = 2.4 V (1 mA) JEDEC specification.
SDRISE
SDFALL
OL OH
5. Duty cycle should be tested with a 50/50% input.
6. Over MIN (20 pF) to MAX (30 pF) discrete load, process, voltage, and temperature.
7. Input edge rate for these tests must be faster than 1 V/ns.
8. Calculated at minimum edge rate (1.5 ns) to guarantee 45/55% duty cycle at 1.5 V. Pulse width is required to be wider at the faster edge to
ensure duty cycle specification is met.
9. All typical values are at V = 3.3 V and T
= 25 °C.
CC
amb
10.Typical is measured with MAX (30 pF) discrete load.
11. Typical is measured with MIN (20 pF) discrete load.
7
2002 Jun 03
Philips Semiconductors
Product data
14.318–150 MHz I2C 1:18 clock buffer
PCK2001
2
I C CONSIDERATIONS
2
2
I C has been chosen as the serial bus interface to control the PCK2001. I C was chosen to support the JEDEC proposal JC-42.5 168 Pin
2
Unbuffered SDRAM DIMM. All vendors are required to determine the legal issues associated with the manufacture of I C devices.
1. Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if
2
only one master clock driver is used in a design. The address can be re-used for the CKBF device if no other conflicting I C clock driver is
used in the system.
The following address was confirmed by Philips on 09/04/96.
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W#
0
2
NOTE: The R/W# bit is used by the I C controller as a data direction bit. A ‘zero’ indicates a transmission (WRITE) to the clock device. A
‘one’ indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller to WRITE
data; the R/W# bit of the address will always be seen as ‘zero’. Optimal address decoding of this bit is left to the vendor.
2. Options: It is our understanding that metal mask options and other pinouts of this type of clock driver will be allowed to use the same
2
address as the original CKBF device. I C addresses are defined in terms of function (master clock driver) rather than form (pinout, and
option).
3. Slave/Receiver: The clock driver is assumed to require only slave/receiver functionality. Slave/transmitter functionality is optional.
4. Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality required. Fast mode (400 kbits/s) functionality is optional.
2
5. Logic Levels: I C logic levels are based on a percentage of V for the controller and other devices on the bus. Assume all devices are
DD
based on a 3.3 Volt supply.
6. Data Byte Format: Byte format is 8 Bits as described in the following appendices.
2
7. Data Protocol: To simplify the clock I C interface, the clock driver serial protocol was specified to use only block writes from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
2
transferred. Indexed bytes are not allowed. However, the SMBus controller has a more specific format than the generic I C protocol.
2
The clock driver must meet this protocol which is more rigorous than previously stated I C protocol. Treat the description from the viewpoint
of controller. The controller “writes” to the clock driver and if possible would “read” from the clock driver (the clock driver is a slave/receiver
only and is incapable of this transaction.)
“The block write begins with a slave address and a write condition. After the command code the host (controller) issues a byte count which
describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be the number 20 (14h),
followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to transfer a maximum of 32 data bytes.”
1 bit
7 bits
1
1
8 bits
1
Start bit
Slave Address
R/W
Ack
Command Code Ack
Byte Count = N
...
Ack
1 bit
Data Byte 1
8 bits
Ack
1
Data Byte 2
8 bits
Ack
1
Data Byte 2
8 bits
Ack
1
Stop
1
SW00279
NOTE: The acknowledgement bit is returned by the slave/receiver (the clock driver).
8
2002 Jun 03
Philips Semiconductors
Product data
14.318–150 MHz I2C 1:18 clock buffer
PCK2001
Consider the command code and the byte count bytes required as the first two bytes of any transfer. The command code is software
programmable via the controller, but will be specified as 0000 0000 in the clock specification. The byte count byte is the number of
additional bytes required to transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is required to
be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement.
For example:
Byte count byte
Notes:
MSB
0000
0000
0000
0000
0000
0000
0000
0000
0010
LSB
0000 Not allowed. Must have at least one byte.
0001 Data for functional and frequency select register (currently byte 0 in spec)
0010 Reads first two bytes of data. (byte 0 then byte 1)
0011 Reads first three bytes (byte 0, 1, 2 in order)
0100 Reads first four bytes (byte 0, 1, 2, 3 in order)
0101 Reads first five bytes (byte 0, 1, 2, 3, 4 in order)
0110 Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)
0111 Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)
0000 Max byte count supported = 32
A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The serial controller
interface can be simplified by discarding the information in both the command code and the byte count bytes and simply reading all the bytes
that are sent to the clock driver after being addressed by the controller. It is expected that the controller will not provide more bytes than the
clock driver can handle. A clock vendor may choose to discard any number of bytes that exceed the defined byte count.
8. Clock stretching: The clock device must not hold/stretch the SCLOCK or SDATA lines low for more than 10 mS. Clock stretching is
discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than this time puts the device in an
error/time-out mode and may not be supported in all platforms. It is assumed that all data transfers can be completed as specified without
the use of clock/data stretching.
9. General Call: It is assumed that the clock driver will not have to respond to the “general call.”
2
10.Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in section 15 of the I C
specification.
a. Pull-Up Resistors: Any internal resistors pull-ups on the SDATA and SCLOCK inputs must be stated in the individual data sheet. The use of
internal pull-ups on these pins of below 100 kΩ is discouraged. Assume that the board designer will use a single external pull-up resistor for
2
2
each line and that these values are in the 5 to 6 kΩ range. Assume one I C device per DIMM (serial presence detect), one I C controller,
2
one clock driver plus one/two more I C devices on the platform for capacitive loading purposes.
2
b. Input Glitch Filters: Only fast mode I C devices require input glitch filters to suppress bus noise. The clock driver is specified as a standard
mode device and is not required to support this feature.
11. PWR DWN#: If a clock driver is placed in PWR DWN# mode, the SDATA and SCLK inputs must be 3-Stated and the device must retain all
2
programming information. I current due to the I C circuitry must be characterized and in the data sheet.
DD
2
2
For specific I C information consult the Philips I C Peripherals Data Handbook IC12 (1997).
9
2002 Jun 03
Philips Semiconductors
Product data
14.318–150 MHz I2C 1:18 clock buffer
PCK2001
SERIAL CONFIGURATION MAP
The serial bits will be read by the clock buffer in the following order:
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 2 – Bits 7, 6, 5, 4, 3, 2, 1, 0
All unused register bits (Reserved and N/A) should be defined as “Don’t Care”. It is expected that the controller will force all of these bits to a “0”
level.
All register bits labeled “Initialize to 0” must be written to zero during initialization. Failure to do so may result in a higher than normal operating
current. The controller will read back the last written value.
Byte 0: Output active/inactive register
1 = enable; 0 = disable
BIT
7
PIN#
18
17
14
13
9
NAME
DESCRIPTION
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
BUF_OUT7
BUF_OUT6
BUF_OUT5
BUF_OUT4
BUF_OUT3
BUF_OUT2
BUF_OUT1
BUF_OUT0
6
5
4
3
2
8
1
5
0
4
NOTE:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
not expected to be configured during the normal modes of operation.
Byte 1: Output active/inactive register
1 = enable; 0 = disable
BIT
7
PIN#
45
NAME
DESCRIPTION
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
Active/Inactive
BUF_OUT15
BUF_OUT14
BUF_OUT13
BUF_OUT12
BUF_OUT11
BUF_OUT10
BUF_OUT9
BUF_OUT8
6
44
5
41
4
40
3
36
2
35
1
32
0
31
NOTE:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
not expected to be configured during the normal modes of operation.
Byte 2: Optional register for possible future requirements
BIT
7
PIN#
28
21
—
NAME
DESCRIPTION
Active/Inactive
Active/Inactive
(reserved)
BUF_OUT17
BUF_OUT16
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
(reserved)
6
5
4
—
(reserved)
3
—
(reserved)
2
—
(reserved)
1
—
(reserved)
0
—
(reserved)
NOTE:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are
not expected to be configured during the normal modes of operation.
10
2002 Jun 03
Philips Semiconductors
Product data
14.318–150 MHz I2C 1:18 clock buffer
PCK2001
AC WAVEFORMS
V
V
V
V
= 1.5 V
M
X
Y
= V + 0.3 V
OL
t
kp
= V – 0.3 V
OH
t
kh
DUTY CYCLE
and V are the typical output voltage drop that occur with the
OL
OH
output load.
2.4
1.5
0.4
V
DD
t
kl
BUF_IN
INPUT
V
V
M
t
M
t
r
t
f
t
PLH
PHL
SW00479
Figure 4. SDRAM Output clock
V
V
M
M
BUF_OUT
TEST CIRCUIT
SW00246
S
Figure 1. Load circuitry for switching times.
1
V
2<V
DD
DD
Open
V
SS
V
I
500Ω
500Ω
V
DD
V
V
I
O
PULSE
GENERATOR
V
nOE INPUT
GND
M
D.U.T.
R
C
L
T
t
t
PZL
PLZ
V
DD
OUTPUT
LOW-to-OFF
OFF-to-LOW
TEST
S
1
V
M
t
t
/t
Open
V
PLH PHL
X
V
OL
t
/t
2<V
PLZ PZL
DD
/t
V
SS
t
t
PZH
PHZ PZH
PHZ
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
V
Y
SW00251
V
M
Figure 5. Load circuitry for switching times
V
SS
outputs
enabled
outputs
enabled
outputs
disabled
SW00245
Figure 2. 3-State enable and disable times
T
SDKP
T
SDKH
DUTY CYCLE
2.4
1.5
0.4
T
SDKL
T
T
SDFALL
SDRISE
SW00247
Figure 3. Buffer Output clock
11
2002 Jun 03
Philips Semiconductors
Product data
14.318–150 MHz I2C 1:18 clock buffer
PCK2001
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
12
2002 Jun 03
Philips Semiconductors
Product data
14.318–150 MHz I2C 1:18 clock buffer
PCK2001
NOTES
13
2002 Jun 03
Philips Semiconductors
Product data
14.318–150 MHz I2C 1:18 clock buffer
PCK2001
2
2
Purchase of Philips I C components conveys a license under the Philips’ I C patent
2
to use the components in the I C system provided the system conforms to the
I C specifications defined by Philips. This specification can be ordered using the
2
code 9398 393 40011.
Data sheet status
Product
status
Definitions
[1]
Data sheet status
[2]
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
Preliminary data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
Product data
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Koninklijke Philips Electronics N.V. 2002
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 06-02
9397 750 09944
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
Philips
Semiconductors
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