PCK2001RDB,112_技术文档

Philips Semiconductors

Product data

533 MHz I²C 1:6 clock buffer

PCK2001R

2

FEATURES

• Individual SDRAM clock output enable/disable via I C

• Typically used to support four registered SDRAM DIMMs

• 16-pin SSOP package

• Multiple V , V pins for noise reduction

DD

SS

• 3.3 V operation

• See PCK2001 for 48-pin 1:18 buffer part

• See PCK2001M for 28-pin 1:10 buffer part

• Operating frequency: 0 - 533 MHz

• Optimized for 33 MHz, 66 MHz, 100 MHz and 133 MHz operation

• Part-to-part skew < 500 ps

• ESD protection exceeds 2000 V per Standard 801.2

DESCRIPTION

The PCK2001R is a 1- 6 fanout buffer used for 133/100 MHz CPU,

66/33 MHz PCI, 14.318 MHz REF, or 133/100/66 MHz SDRAM clock

distribution. 6 outputs are typically used to support up to 4 registered

SDRAM DIMMs commonly found in server applications.

• 175 ps skew outputs typical

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

= 3.3 V, CL = 30 pF

TYPICAL

UNIT

t

Propagation delay

2.5

PLH

PHL

V

ns

CC

BUF_IN to BUF_OUT

Rise time

n

t

r

V

CC

V

CC

V

CC

= 3.3 V, CL = 30 pF

= 3.3 V, CL = 20 pF

= 3.465 V

1.0

700

50

ns

ps

µA

t

f

Fall time

I

Total supply current

CC

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

DRAWING NUMBER

16-Pin Plastic SSOP

0 to +70 °C

PCK2001RDB

SOT369-1

PIN CONFIGURATION

PIN DESCRIPTION

NUMBER

I/O

TYPE

SYMBOL

FUNCTION

V

16

1

2

3

4

5

6

7

8

DD9

BUF_OUT0

BUF_OUT

(0, 2)

V

15 BUF_OUT14

SS0

1, 3

13, 15

6, 11

Output

Buffered clock outputs

V

SS9

BUF_OUT2

BUF_IN

14

13

12

BUF_OUT

(11, 14)

BUF_OUT11

V

SS

DD5

BUF_OUT

(7, 17)

Buffered clock outputs

Buffered clock input

11 BUF_OUT17

2

BUF_OUT7

2

4

8

9

Input

I/O

BUF_IN

SDA

10

9

V

SSI

V

C

DDI

C

2

I C serial data

SDA

SCL

2

Input

SCL

I C serial clock

TOP VIEW

V

(5, 9)

DD

SA00542

12, 16

2, 14

Input

3.3 V power supply

Ground

V

(0, 9)

SS

Intel and Pentium are registered trademarks of Intel Corporation.

I C is a trademark of Philips Semiconductors Corporation.

2

7

Input

V

3.3 V I C power supply

DDI C

2

10

V

I C ground

SSI C

2

2002 Dec 13

Philips Semiconductors

Product data

533 MHz I²C 1:6 clock buffer

PCK2001R

FUNCTION TABLE

2

BUF_IN

I CEN

BUF_OUTn

L

H

X

H

L

H

L

1, 2

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134).

Voltages are referenced to V (V = 0V).

SS

LIMITS

SYMBOL

PARAMETER

CONDITION

UNIT

MIN

MAX

V

I

DC 3.3 V supply voltage

DC input diode current

DC input voltage

-0.5

+4.6

-50

5.5

50

V

mA

V

DD

V < 0

IK

I

V

Note 2

-0.5

-65

I

DC output diode current

DC output voltage

V

O

> V or V < 0

mA

V

OK

DD

O

V

Note 2

V

+ 0.5

O

CC

I

DC output source or sink current

Storage temperature range

V

O

≥ 0 to V

50

mA

°C

O

DD

T

stg

+150

Power dissipation per package

plastic medium-shrink SO (SSOP)

For temperature range: 0 to +70 °C

above +55 °C derate linearly with 11.3mW/K

P

TOT

850

mW

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL

PARAMETER

CONDITIONS

UNIT

MIN

3.135

20

MAX

3.465

30

V

DD

DC 3.3 V supply voltage

Capacitive load

V

pF

V

C

L

V

I

DC input voltage range

0

V

DD

V

DD

V

O

DC output voltage range

0

V

T

amb

Operating ambient temperature range in free air

0

+70

°C

3

2002 Dec 13

Philips Semiconductors

Product data

533 MHz I²C 1:6 clock buffer

PCK2001R

DC CHARACTERISTICS

LIMITS

TEST CONDITIONS

OTHER

T

= 0°C to +70°C

UNIT

SYMBOL

PARAMETER

amb

V

DD

(V)

MIN

MAX

V

HIGH level input voltage

LOW level input voltage

3.3V output HIGH voltage

3.3V output LOW voltage

Output HIGH current

3.135 to 3.465

3.465

2.0

V

DD

+ 0.3

V

IH

V

- 0.3

0.8

IL

SS

V

OH

I

= -1mA

3.1

-

V

OH

V

OL

I

OL

= 1mA

50

mV

mA

µA

I

V

= 1.5V

-70

65

-5

-

-185

160

5

OH

OUT

I

OL

Output LOW current

I

Input leakage current

Quiescent supply current

I

3.465

V = V or GND

I = 0

O

100

CC

I

DD

4

2002 Dec 13

Philips Semiconductors

Product data

533 MHz I²C 1:6 clock buffer

PCK2001R

AC CHARACTERISTICS

LIMITS

= 0°C to +70°C

TEST CONDITIONS

NOTES

T

amb

SYMBOL

PARAMETER

UNIT

MAX

9

MIN

29.9

12.3

12.1

14.9

5.6

5.3

9.9

3.3

3.2

7.4

2.6

2.2

1.5

1.0

45

TYP

t

CLK period

CLK HIGH time

CLK LOW time

CLK period

1, 6

2, 6, 8

3, 6, 8

1, 6

30.0

14.3

14.1

15.0

6.8

30.2

P

16.3

16.1

15.2

8.0

7.7

10.2

5.1

5.0

7.7

3.6

3.2

4.0

3.5

55

33 MHz

66 MHz

ns

H

t

L

t

P

CLK HIGH time

CLK LOW time

CLK period

2, 6, 8

3, 6, 8

1,6

H

t

6.5

L

t

10.01

4.2

P

CLK HIGH time

CLK LOW time

CLK period

2, 6, 8

3, 6, 8

1, 6

100 MHz

133 MHz

H

t

4.1

L

t

7.5

P

CLK HIGH time

CLK LOW time

Rise time

2, 6, 8

3, 6, 8

4, 6, 10

4, 6, 11

6, 7

3.1

H

t

2.7

L

t

2.0

V/ns

ns

SDRISE

SDFALL

Fall time

2.5

t

Buffer LH propagation delay

Buffer HL propagation delay

Output Duty Cycle

Bus CLK skew

2.4

PLH

6, 7

2.6

ns

PHL

DUTY CYCLE

Measured at 1.5 V

5, 6, 7

1, 6

50

%

t

150

250

500

ps

SKW

t

Device to device skew

ps

DDSKW

NOTES:

1. Clock period and skew are measured on the rising edge at 1.5V.

2. t is measured at 2.4V as shown in Figure 2.

H

3. t is measured at 0.4V as shown in Figure 2.

L

4. t

and t are measured as a transition through the threshold region V = 0.4V and V = 2.4V (1 mA) JEDEC specification.

SDFALL OL OH

SDRISE

5. Duty cycle should be tested with a 50/50% input.

6. Over MIN (20pF) to MAX (30pF) discrete load, process, voltage, and temperature.

7. Input edge rate for these tests must be faster than 1 V/ns.

8. Calculated at minimum edge rate (1.5ns) to guarantee 45/55% duty cycle at 1.5V. Pulsewidth is required to be wider at the faster edge to

ensure duty cycle specification is met.

9. All typical values are at V = 3.3V and T

10.Typical is measured with MAX (30pF) discrete load.

11. Typical is measured with MIN (20pF) discrete load.

= 25°C.

CC

amb

5

2002 Dec 13

Philips Semiconductors

Product data

533 MHz I²C 1:6 clock buffer

PCK2001R

2

I C CONSIDERATIONS

2

I C has been chosen as the serial bus interface to control the PCK2001R. I C was chosen to support the JEDEC proposal JC-42.5 168 Pin

2

Unbuffered SDRAM DIMM. All vendors are required to determine the legal issues associated with the manufacture of I C devices.

1) Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if only

2

one master clock driver is used in a design. The address can be re-used for the CKBF device if no other conflicting I C clock driver is used in

the system.

The following address was confirmed by Philips on 09/04/96.

A6

A5

A4

A3

A2

A1

A0

R/W

0

1

0

1

0

1

2

NOTE: The R/W bit is used by the I C controller as a data direction bit. A ‘zero’ indicates a transmission (WRITE) to the clock device. A ‘one’

indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller to WRITE data; the

R/W bit of the address will always be seen as ‘zero’. Optimal address decoding of this bit is left to the vendor.

2) Options: It is our understanding that metal mask options and other pinouts of this type of clock driver will be allowed to use the same address

2

as the original CKBF device. I C addresses are defined in terms of function (master clock driver) rather than form (pinout, and option).

3) Slave/Receiver: The clock driver is assumed to require only slave/receiver functionality. Slave/transmitter functionality is optional.

4) Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality required. Fast mode (400 kbits/s) functionality is optional.

2

5) Logic Levels: I C logic levels are based on a percentage of V for the controller and other devices on the bus. Assume all devices are

DD

based on a 3.3 Volt supply.

6) Data Byte Format: Byte format is 8 Bits as described in the following appendices.

2

7) Data Protocol: To simplify the clock I C interface, the clock driver serial protocol was specified to use only block writes from the controller.

The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been

2

transferred. Indexed bytes are not allowed. However, the SMBus controller has a more specific format than the generic I C protocol.

2

The clock driver must meet this protocol which is more rigorous than previously stated I C protocol. Treat the description from the viewpoint of

controller. The controller ‘‘writes” to the clock driver and if possible would ‘‘read” from the clock driver (the clock driver is a slave/receiver only

and is incapable of this transaction.)

‘‘The block write begins with a slave address and a write condition. After the command code the host (controller) issues a byte count which

describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be the number 20 (14h),

followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to transfer a maximum of 32 data bytes.”

1 bit

7 bits

1

8 bits

1

Start bit

Slave Address

R/W

Ack

Command Code Ack

Byte Count = N

...

Ack

1 bit

Data Byte 1

8 bits

Ack

1

Data Byte 2

8 bits

Ack

1

Data Byte 2

8 bits

Ack

1

Stop

1

SW00279

NOTE: The acknowledgement bit is returned by the slave/receiver (the clock driver).

Consider the command code and the byte count bytes required as the first two bytes of any transfer. The command code is software

programmable via the controller, but will be specified as 0000 0000 in the clock specification. The byte count byte is the number of additional

bytes required to transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is required to be a minimum of

1 byte and a maximum of 32 bytes to satisfy the above requirement.

6

2002 Dec 13

Philips Semiconductors

Product data

533 MHz I²C 1:6 clock buffer

PCK2001R

For example:

Byte count byte

Notes:

MSB

0000

0010

LSB

0000 Not allowed. Must have at least one byte.

0001 Data for functional and frequency select register (currently byte 0 in spec)

0010 Reads first two bytes of data. (byte 0 then byte 1)

0011 Reads first three bytes (byte 0, 1, 2 in order)

0100 Reads first four bytes (byte 0, 1, 2, 3 in order)

0101 Reads first five bytes (byte 0, 1, 2, 3, 4 in order)

0110 Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)

0111 Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)

0000 Max byte count supported = 32

A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The serial controller interface

can be simplified by discarding the information in both the command code and the byte count bytes and simply reading all the bytes that are

sent to the clock driver after being addressed by the controller. It is expected that the controller will not provide more bytes than the clock driver

can handle. A clock vendor may choose to discard any number of bytes that exceed the defined byte count.

8) Clock stretching: The clock device must not hold/stretch the SCLOCK or SDATA lines low for more than 10 ms. Clock stretching is

discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than this time puts the device in an error/time-out

mode and may not be supported in all platforms. It is assumed that all data transfers can be completed as specified without the use of

clock/data stretching.

9) General Call: It is assumed that the clock driver will not have to respond to the ‘‘general call.”

2

10) Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in section 15 of the I C

specification.

a) Pull-Up Resistors: Any internal resistors pull-ups on the SDATA and SCLOCK inputs must be stated in the individual datasheet. The use of

internal pull-ups on these pins of below 100 kΩ is discouraged. Assume that the board designer will use a single external pull-up resistor for

2

each line and that these values are in the 5-6 kΩ range. Assume one I C device per DIMM (serial presence detect), one I C controller, one

2

clock driver plus one/two more I C devices on the platform for capacitive loading purposes.

2

(b) Input Glitch Filters: Only fast mode I C devices require input glitch filters to suppress bus noise. The clock driver is specified as a standard

mode device and is not required to support this feature.

11) PWR DWN: If a clock driver is placed in PWR DWN mode, the SDATA and SCLK inputs must be 3-Stated and the device must retain all

2

programming information. I current due to the I C circuitry must be characterized and in the data sheet.

DD

2

For specific I C information consult the Philips I C Peripherals Data Handbook IC12 (1997).

7

2002 Dec 13

Philips Semiconductors

Product data

533 MHz I²C 1:6 clock buffer

PCK2001R

SERIAL CONFIGURATION MAP

The serial bits will be read by the clock buffer in the following order:

Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 2 - Bits 7, 6, 5, 4, 3, 2, 1, 0

All unused register bits (Reserved and N/A) should be desined as “Don’t Care”. It is expected that the controller will force all of these bits to a

“0” level.

All register bits labeled “Initialize to 0” must be written to zero during intialization. Failure to do so may result in a higher than normal operating

current. The controller will read back the last written value.

Byte 0: Active/inactive register

1 = enable; 0 = disable

BIT

7

PIN#

6

NAME

DESCRIPTION

BUF_OUT7

Active/Inactive

6

—

3

—

5

—

4

—

3

—

2

BUF_OUT2

—

Active/Inactive

—

1

—

1

0

BUF_OUT0

Active/Inactive

NOTE:

1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are

not expected to be configured during the normal modes of operation.

Byte 1: Active/inactive register

1 = enable; 0 = disable

BIT

7

PIN#

—

NAME

DESCRIPTION

—

6

15

—

BUF_OUT14

Active/Inactive

5

—

4

—

3

13

—

BUF_OUT11

Active/Inactive

2

—

1

—

0

—

NOTE:

1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are

not expected to be configured during the normal modes of operation.

Byte 2: Active/inactive register

BIT

7

PIN#

11

—

NAME

DESCRIPTION

BUF_OUT17

Active/Inactive

6

—

5

—

4

—

3

—

2

—

1

—

0

—

NOTE:

1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are

not expected to be configured during the normal modes of operation.

8

2002 Dec 13

Philips Semiconductors

Product data

533 MHz I²C 1:6 clock buffer

PCK2001R

AC WAVEFORMS

TEST CIRCUIT

V

= 1.5 V

M

X

Y

= V + 0.3 V

OL

V

DD

= V

-0.3 V

OH

and V are the typical output voltage drop that occur with the

OL

OH

output load.

V

I

O

V

DD

PULSE

GENERATOR

D.U.T.

BUF_IN

INPUT

V

M

t

M

500Ω

R

C

L

T

t

PLH

PHL

V

M

SW00719

BUF_OUT

Figure 3. Load circuitry for switching times

SW00246

Figure 1. Load circuitry for switching times.

t

p

t

h

DUTY CYCLE

2.4

1.5

0.4

t

l

t

r

t

f

SW00613

Figure 2. Buffer Output clock

9

2002 Dec 13

Philips Semiconductors

Product data

533 MHz I²C 1:6 clock buffer

PCK2001R

SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm

SOT369-1

10

2002 Dec 13

Philips Semiconductors

Product data

533 MHz I²C 1:6 clock buffer

PCK2001R

REVISION HISTORY

Rev

Date

Description

_2

20021213

Product data (9397 750 10864); ECN 853-2210 29225 of 22 November 2002.

Modifications:

• Increase F

to 533 MHz.

max

_1

20000725

Product data (9397 750 07352); ECN 853-2210 24202 of 25 July 2000.

11

2002 Dec 13

Philips Semiconductors

Product data

533 MHz I²C 1:6 clock buffer

PCK2001R

Data sheet status

Product

status

Definitions

[1]

Level

Data sheet status

[2] [3]

I

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

II

Preliminary data

Product data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in

order to improve the design and supply the best possible product.

III

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given

in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no

representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be

expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree

to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described

or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated

via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys

no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,

copyright, or mask work right infringement, unless otherwise specified.

 Koninklijke Philips Electronics N.V. 2002

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 12-02

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

9397 750 10864

Philips

Semiconductors

12

2002 Dec 13


型号：	PCK2001RDB,112
厂家：	NXP
描述：	PCK2001R - 533 MHz I2C 1:6 clock buffer SSOP1 16-Pin PC 驱动光电二极管逻辑集成电路
文件：	总12页 (文件大小：77K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCK2001RDB,112 [NXP]

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