PCF85133U [NXP]
Universal 36 Ã 4 LCD segment driver;型号: | PCF85133U |
厂家: | NXP |
描述: | Universal 36 Ã 4 LCD segment driver CD |
文件: | 总51页 (文件大小:652K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PCF8551
Universal 36 × 4 LCD segment driver
Rev. 3.1 — 3 May 2021
Product data sheet
1 General description
PCF8551 is an ultra low-power LCD segment driver with 4 backplane- and 36 segment-
driver outputs, with either an I2C- (PCF8551A) or an SPI-bus (PCF8551B) interface.
It comprises an internal oscillator, bias generation, instruction decoding, and display
controller.
For a selection of NXP LCD segment drivers, see Table 23.
2 Features and benefits
• Single chip LCD controller and driver with temperature range of -40 °C to 85 °C
• Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing
• Selectable display bias configuration: static, 1⁄2, or 1⁄3
• Internal LCD bias generation with buffers
• 36 segment drives:
– Up to 18 7-segment numeric characters
– Up to 9 14-segment alphanumeric characters
– Any graphics of up to 144 segments/elements
• Auto-incrementing display data and instruction loading
• Versatile blinking modes
• Independent supplies of VLCD and VDD
• Power supply ranges:
– 1.8 V to 5.5 V for VLCD
– 1.8 V to 5.5 V for VDD
• Ultra low-power consumption
• 400 kHz I2C-bus interface (PCF8551A)
• 5 MHz SPI-bus interface (PCF8551B)
• Internally generated or externally supplied clock signal
3 Applications
• Metering equipment
• Consumer healthcare devices
• Battery operated devices
• Measuring equipment
NXP Semiconductors
PCF8551
Universal 36 × 4 LCD segment driver
4 Ordering information
Table 1.ꢀOrdering Information
Product type Number Topside mark
Package
Name
Description
Version
PCF8551ATT/A
PCF8551BTT/A
PCF8551A
PCF8551B
TSSOP48
plastic thin shrink small outline
package; 48 leads; body width 6.1 mm
SOT362-1
TSSOP48
plastic thin shrink small outline
SOT362-1
package; 48 leads; body width 6.1 mm
4.1 Ordering options
Table 2.ꢀOrdering options
Product type
Number
Orderable part
number
PCF8551ATT/AJ [1]
Package
TSSOP48
TSSOP48
TSSOP48
TSSOP48
Packing method
Reel 13” Q1 NDP
Reel 13” Q1 DP
Reel 13” Q1 NDP
Reel 13” Q1 DP
Minimum order Temperature
quantity
PCF8551ATT/A
2000
2000
2000
2000
Tamb = -40 °C to
+85 °C
PCF8551ATT/AY [2]
PCF8551BTT/AJ [1]
PCF8551BTT/AY [2]
Tamb = -40 °C to
+85 °C
PCF8551BTT/A
Tamb = -40 °C to
+85 °C
Tamb = -40 °C to
+85 °C
[1] Not recommend for new design - will be discontinued in mid 2021 - use new version with improved package.
[2] Improved package - refer to PCN 202005038F01
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
5 Block diagram
COM0 to COM3
SEG0 to SEG35
36
COM0 to COM3
SEG0 to SEG35
36
VLCD
VLCD
Backplane
outputs
Backplane
outputs
Segment
outputs
V
V
high
low
Segment
outputs
V
V
high
low
LCD
voltage
selection
LCD
voltage
selection
Blink control
Blink control
LCD bias
generator
VSS
LCD bias
generator
Display controller
Display controller
VSS
Instruction
register
Display
register
IBIAS/
VREF
IBIAS/
VREF
Instruction
register
Display
register
Oscillator
Prescaler
Sync
Oscillator
Prescaler
Sync
Clock
select
CLK
Timer
Clock
select
Address
decoder
CLK
Timer
Address
decoder
PCF8551A
PCF8551B
Power-On
Reset
Reset
control
Power-On
Reset
Reset
control
PORE
Internal Bus
PORE
Internal Bus
Input
filters
Input
filters
2
I C-bus controller
SPI-bus controller
VDD
VDD
CE
aaa-013214
aaa-013215
SDA
SDIO
SCL
SCL
Figure 1.ꢀBlock diagram of PCF8551A
Figure 2.ꢀBlock diagram of PCF8551B
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
6 Pinning information
6.1 Pinning
SEG31
SEG32
SEG33
SEG34
SEG35
COM0
COM1
COM2
COM3
1
2
3
4
5
6
7
8
9
48 SEG30
47 SEG29
46 SEG28
45 SEG27
44 SEG26
43 SEG25
42 SEG24
41 SEG23
40 SEG22
39 SEG21
38 SEG20
37 SEG19
36 SEG18
35 SEG17
34 SEG16
33 SEG15
32 SEG14
31 SEG13
30 SEG12
29 SEG11
28 SEG10
27 SEG9
VLCD 10
VDD 11
VSS 12
PCF8551ATT
T1 13
CLK 14
SCL 15
SDA 16
PORE 17
SEG0 18
SEG1 19
SEG2 20
SEG3 21
SEG4 22
SEG5 23
SEG6 24
26 SEG8
25 SEG7
aaa-012401
For mechanical details, see Figure 29.
Figure 3.ꢀPin configuration of PCF8551ATT (TSSOP48)
PCF8551
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NXP Semiconductors
PCF8551
Universal 36 × 4 LCD segment driver
SEG31
SEG32
SEG33
SEG34
SEG35
COM0
COM1
COM2
COM3
1
2
3
4
5
6
7
8
9
48 SEG30
47 SEG29
46 SEG28
45 SEG27
44 SEG26
43 SEG25
42 SEG24
41 SEG23
40 SEG22
39 SEG21
38 SEG20
37 SEG19
36 SEG18
35 SEG17
34 SEG16
33 SEG15
32 SEG14
31 SEG13
30 SEG12
29 SEG11
28 SEG10
27 SEG9
VLCD 10
VDD 11
VSS 12
PCF8551BTT
SDIO 13
CLK 14
SCL 15
CE 16
PORE 17
SEG0 18
SEG1 19
SEG2 20
SEG3 21
SEG4 22
SEG5 23
SEG6 24
26 SEG8
25 SEG7
aaa-012402
For mechanical details, see Figure 29.
Figure 4.ꢀPin configuration of PCF8551BTT (TSSOP48)
6.2 Pin description
Table 3.ꢀPin description
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
Pin
Symbol
Type
Description
1 to 5,
SEG0 to SEG35
output
LCD segment outputs
18 to 48
6 to 9
10
COM0 to COM3
VLCD
output
supply
supply
supply
LCD backplane outputs
LCD supply voltage
supply voltage
11
VDD
12
VSS
ground supply
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
Table 3.ꢀPin description...continued
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
Pin
Symbol
Type
Description
14
CLK
input/output internal oscillator output, external oscillator input[1]
• must be left open if unused
15
17
SCL
PORE[2]
input
input
serial clock input
Power-On Reset (POR) enable
• connect to VDD for enabling POR
• connect to VSS (or leave open) for disabling POR
Pin layout depending on product and bus type
PCF8551ATT PCF8551BTT
(I2C-bus)
(SPI-bus)
13
16
T1
-
-
must be left open or connected to VSS
-
SDIO
-
input/output serial data input/output
input/output serial data line
SDA
-
CE
input
chip enable input, active LOW
[1] Can be configured by command, see Table 5.
[2] A series resistance between VDD and the pin must not exceed 1 kΩ to ensure proper functionality, see Section 15.3.
7 Functional description
7.1 Registers of the PCF8551
The registers of the PCF8551 are arranged in bytes with 8 bit, addressed by an address
pointer. Table 4 depicts the layout.
Table 4.ꢀRegisters of the PCF8551
Bits labeled as 0 must always be written with logic 0; bits labeled as - are ignored by the device.
Register name Address Bits
Reference
AP[4:0]
Command registers
Software_reset 00h
7
6
5
4
3
2
1
0
SR[7:0]
Table 8
Table 5
Table 6
Table 7
Device_ctrl
01h
02h
03h
0
0
0
0
0
0
0
0
0
0
FF[1:0]
OSC
B
COE
DE
Display_ctrl_1
Display_ctrl_2
BOOST MUX[1:0]
0
0
BL[1:0]
SEG2
INV
Display data registers
COM0
04h
05h
06h
07h
08h
SEG7
SEG6
SEG5
SEG4
SEG3
SEG1
SEG0
SEG8
Table 9
SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9
SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16
SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24
-
-
-
-
SEG35 SEG34 SEG33 SEG32
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
Table 4.ꢀRegisters of the PCF8551...continued
Bits labeled as 0 must always be written with logic 0; bits labeled as - are ignored by the device.
Register name Address Bits
Reference
AP[4:0]
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
7
6
5
4
3
2
1
0
COM1
COM2
COM3
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
SEG8
SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9
SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16
SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24
-
-
-
-
SEG35 SEG34 SEG33 SEG32
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
SEG8
SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9
SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16
SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24
12h
13h
14h
15h
16h
17h
-
-
-
-
SEG35 SEG34 SEG33 SEG32
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
SEG8
SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9
SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16
SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24
-
-
-
-
SEG35 SEG34 SEG33 SEG32
For writing to the registers, send the address byte first, then write the data to the register
(see Section 10.1.4 and Section 10.2.1). The address byte works as an address pointer.
For the succeeding registers, the address pointer is automatically incremented by 1 (see
Figure 5) and all following data are written into these register addresses. After register
18h, the auto-incrementing will stop and subsequent data are ignored.
address counter
00h
01h
auto-increment
02h
03h
...
15h
16h
17h
aaa-011661
Figure 5.ꢀAddress counter incrementing
7.2 Command registers of the PCF8551
7.2.1 Command: Device_ctrl
The Device_ctrl command sets the device into a defined state. It should be executed
before enabling the display (see bit DE in Table 6).
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
Table 5.ꢀDevice_ctrl - device control command register (address 01h) bit
description
Bit
Symbol
-
Value
Description
7 to 4
3 to 2
0000
default value
FF[1:0]
frame frequency selection
ffr = 32 Hz
00
01[1]
ffr = 64 Hz
10
ffr = 96 Hz
11
ffr = 128 Hz
1
0
OSC
COE
internal oscillator control
enabled
0[1]
1
disabled
clock output enable
0[1]
clock signal not available on pin CLK;
pin CLK is in 3-state
1
clock signal available on pin CLK
[1] Default value.
7.2.1.1 Internal oscillator and clock output
Bit OSC enables or disables the internal oscillator. When the internal oscillator is used,
bit COE allows making the clock signal available on pin CLK. If this is not intended, pin
CLK should be left open. The design ensures that the duty cycle of the clock output is
50 : 50 (% HIGH-level time : % LOW-level time).
In power-down mode (see Section 7.3.1)
• if pin CLK is configured as an output, there is no signal on CLK
• if pin CLK is configured as an input, the signal on CLK can be removed.
In applications where an external clock has to be applied to the PCF8551, bit OSC must
be set logic 1 and COE logic 0. In this case pin CLK becomes an input.
Remark: A clock signal must always be supplied to the device if the display is enabled
(see bit DE in Table 6). Removing the clock may freeze the LCD in a DC state, which is
not suitable for the liquid crystal.
7.2.2 Command: Display_ctrl_1
The Display_ctrl_1 command allows configuring the basic display set-up.
Table 6.ꢀDisplay_ctrl_1 - display control command 1 register (address 02h) bit
description
Bit
7 to 5
4
Symbol
-
Value
Description
000
default value
BOOST
large display mode support
standard power drive scheme
0[1]
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
Table 6.ꢀDisplay_ctrl_1 - display control command 1 register (address 02h) bit
description...continued
Bit
Symbol
Value
Description
enhanced power drive scheme for higher display
1
loads
3 to 2
MUX[1:0]
multiplex drive mode selection
00[1]
01
1:4 multiplex drive mode; COM0 to COM3 (nMUX
4)
=
=
1:3 multiplex drive mode; COM0 to COM2 (nMUX
3)
10
1:2 multiplex drive mode; COM0 and COM1 (nMUX
= 2)
11
static drive mode; COM0 (nMUX = 1)
bias mode selection
1
0
B[2]
DE
0[1]
1
1⁄3 bias (abias = 2)
1⁄2 bias (abias = 1)
display enable[3]
0[1]
1
display disabled; device is in power-down mode
display enabled; device is in power-on mode
[1] Default value.
[2] Not applicable for static drive mode.
[3] See Section 7.3.1.
7.2.2.1 Enhanced power drive mode
By setting the BOOST bit to logic 1, the driving capability of the display signals is
increased to cope with large displays with a higher effective capacitance. Setting this bit
increases the current consumption on VLCD
.
7.2.2.2 Multiplex drive mode
MUX[1:0] sets the multiplex driving scheme and the associated backplane drive signals,
which are active. For further details, see Section 8.2.
7.2.3 Command: Display_ctrl_2
Table 7.ꢀDisplay_ctrl_2 - display control command 2 register (address 03h) bit
description
Bit
Symbol
-
Value
Description
7 to 3
2 to 1
00000
default value
BL[1:0]
blink control
00[1]
01
blinking off
blinking on, fblink = 0.5 Hz
blinking on, fblink = 1 Hz
blinking on, fblink = 2 Hz
inversion mode selection
10
11
0
INV
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
Table 7.ꢀDisplay_ctrl_2 - display control command 2 register (address 03h) bit
description...continued
Bit
Symbol
Value
0[1]
1
Description
line inversion (driving scheme A)
frame inversion (driving scheme B)
[1] Default value.
7.2.3.1 Blinking
The whole display blinks at frequencies selected by the blink control bits BL[1:0], see
Table 7. The blink frequencies are derived from the clock frequency. During the blank-out
phase of the blinking period, the display is turned off.
If an external clock with frequency fclk(ext) is used, the blinking frequency is determined by
Equation 1. For notation, see Section 8.2.
(1)
7.2.3.2 Line inversion (driving scheme A) and frame inversion (driving scheme B)
The waveforms used to drive LCD inherently produce a DC voltage across the display
cell. The PCF8551 compensates for the DC voltage by inverting the waveforms on
alternate frames or alternate lines. The choice of compensation method is determined
with the INV bit.
7.3 Starting and resetting the PCF8551
If the internal Power-On Reset (POR) is enabled by connecting pin PORE to VDD, the
chip resets automatically when VDD rises above the minimum supply voltage. No further
action is required.
If the internal POR is disabled by connecting pin PORE to VSS, the chip must be reset by
a software reset (see Section 7.3.3).
Following a reset, the register 00h has to be rewritten with 0h by the next command byte
or the address pointer AP[4:0] has to be set to the required address after a new START
procedure. See also application information in Section 15.
7.3.1 Power-down mode
After a reset, the PCF8551 remains in power-down mode. In power-down mode the
oscillator is switched off and there is no output on pin CLK. The register settings remain
unchanged and the bus remains active. To enable the PCF8551, bit DE (command
Display_ctrl_1, see Table 6) must be set to logic 1.
7.3.2 Power-On Reset (POR)
If pin PORE is connected to VDD, the PCF8551 comprises an internal POR, which puts
the device into the following starting conditions:
• All backplane and segment outputs are set to VSS
• The selected drive mode is: 1:4 multiplex with 1⁄3 bias
• Blinking is switched off
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
• The address pointer is cleared (set to logic 0)
• The display and the internal oscillator are disabled
• The display registers are set to logic 0
• The bus interface is initialized
Remark: The internal POR can be disabled by connecting pin PORE to VSS. In this case,
the internal registers are not defined and require a software reset, see Section 7.3.3.
Remark: For power-on with a slowly starting power supply, see Section 15.1.
7.3.3 Command: Software_reset
The internal registers including the display registers and the address pointer (set to logic
0) of the device are reset by the Software_reset command.
Table 8.ꢀSoftware_reset - software reset command register (address 00h) bit
description
Bit
Symbol
SR[7:0][1]
Value
Description
software reset
no reset
7 to 0
0000ꢀ0000[2]
0010ꢀ1100
software reset
[1] Software_reset only generates a reset pulse, therefore this register always reads back as 00h.
[2] Default value.
7.4 Display data register mapping
Table 9.ꢀRegister to segment and backplane mapping
Backplanes[1] Segments
SEG0 to SEG7
SEG8 to SEG15
LSB MSB
SEG16 to SEG23
LSB MSB
SEG24 to SEG31
LSB MSB
SEG32 to SEG35
LSB MSB
LSB
MSB
1:4 multiplex drive mode
COM0
COM1
COM2
COM3
content of 04h
content of 09h
content of 05h
content of 0Ah
content of 0Fh
content of 14h
content of 06h
content of 0Bh
content of 10h
content of 15h
content of 07h
content of 0Ch
content of 11h
content of 16h
content of 08h
content of 0Dh
content of 12h
content of 17h
content of 0Eh
content of 13h
1:3 multiplex drive mode
COM0
COM1
COM2
content of 04h
content of 05h
content of 0Ah
content of 0Fh
content of 06h
content of 0Bh
content of 10h
content of 07h
content of 0Ch
content of 11h
content of 08h
content of 0Dh
content of 12h
content of 09h
content of 0Eh
1:2 multiplex drive mode
COM0
COM1
content of 04h
content of 09h
content of 05h
content of 0Ah
content of 06h
content of 0Bh
content of 07h
content of 0Ch
content of 08h
content of 0Dh
static drive mode
COM0
content of 04h
content of 05h
content of 06h
content of 07h
content of 08h
[1] See also Section 8.3.1
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
The example in Table 9 and Figure 6 illustrates the segment and backplane mapping of
the display in relation to the display RAM.
For example, in 1:4 multiplex drive mode, the backplanes are served by signals COM0 to
COM3 and the segments are driven by signals SEG0 to SEG35. Contents of addresses
04h to 08h are allocated to the first row (COM0) starting with the LSB driving the leftmost
element and moving forward to the right with increasing bit position. If a bit is logic 0, the
element is off, if it is logic 1 the element is turned on. All register content is LSB to MSB
left to right. Addresses 09h to 0Dh serve COM1 signals, addresses 0Eh to 12h serve
COM2 signals, and addresses 13h to 17h serve COM3 signals.
For displays with fewer segments/elements, the unused bits are ignored.
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
RAM
discarded
COM0
COM1
Display
COM2
COM3
aaa-014858
Figure 6.ꢀDisplay RAM organization bitmap for MUX 1:4
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
8 Possible display configurations
The possible display configurations of the PCF8551 depend on the number of active
backplane outputs required. A selection of display configurations is shown in Table 10. All
of these configurations can be implemented in the typical systems shown in Figure 8 or
Figure 9.
dot matrix
7-segment with dot
14-segment with dot and accent
013aaa312
Figure 7.ꢀExample of displays suitable for PCF8551
Table 10.ꢀSelection of possible display configurations
Number of
Backplanes
Icons
Digits/Characters
7-segment[1]
Dot matrix:
14-segment[2]
segments/
elements
4
3
2
1
144
108
72
18
13
9
9
6
4
2
144 dots (4 × 36)
108 dots (3 × 36)
72 dots (2 × 36)
36 dots (1 × 36)
36
4
[1] 7 segment display has 8 segments/elements including the decimal point.
[2] 14 segment display has 16 segments/elements including decimal point and accent dot.
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
V
DD
V
LCD
t
r
100 nF
100 nF
R ≤
2C
b
VDD
VLCD
36 segment drives
4 backplanes
SDA
LCD PANEL
(up to 144
elements)
HOST
MICRO-
CONTROLLER
PCF8551A
SCL
PORE
CLK
n.c.
VSS
V
SS
aaa-013223
The resistance of the power lines must be kept to a minimum. A decoupling capacitor of at least
100 nF is recommended for the supplies.
Figure 8.ꢀTypical system configuration using I2C-bus, internal power-on reset disabled
The host microcontroller manages the 2-line I2C-bus communication channel with
the PCF8551A. The internal oscillator is used and the internal POR is disabled in the
example. The appropriate biasing voltages for the multiplexed LCD waveforms are
generated internally. The only other connections required to complete the system are the
power supplies (VDD, VSS, and VLCD) and the LCD panel chosen for the application.
V
DD
V
LCD
100 nF
100 nF
VDD
VLCD
PORE
36 segment drives
4 backplanes
CE
LCD PANEL
(up to 144
elements)
HOST
MICRO-
CONTROLLER
PCF8551B
SDIO
SCL
CLK
n.c.
VSS
V
SS
aaa-013224
The resistance of the power lines must be kept to a minimum. A decoupling capacitor of at least
100 nF is recommended for the supplies.
Figure 9.ꢀTypical system configuration using SPI-bus, internal power-on reset enabled
The host microcontroller manages the 3-line SPI-bus communication channel with the
PCF8551B. The internal oscillator is enabled. The appropriate biasing voltages for
the multiplexed LCD waveforms are generated internally. The only other connections
required to complete the system are the power supplies (VDD, VSS, and VLCD) and the
LCD panel chosen for the application.
8.1 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of three
impedances connected between VLCD and VSS. These intermediate levels are tapped
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
off at positions of 1⁄3 and 2⁄3, or 1⁄2, depending on the bias mode chosen. To keep current
consumption to a minimum, on-chip low-power buffers provide these levels to the display.
8.2 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by
the Display_ctrl_1 command (see Table 6). The biasing configurations that apply to the
preferred modes of operation, together with the biasing characteristics as functions of
VLCD and the resulting discrimination ratios (D) are given in Table 11.
Table 11.ꢀBiasing characteristics
LCD drive
mode
Number of:
LCD bias
configuration
Backplanes Levels
static
1
2
2
3
4
2
3
4
4
4
static
0
1
∞
1
1:2 multiplex
1:2 multiplex
1:3 multiplex
1:4 multiplex
⁄
2
0.354
0.333
0.333
0.333
0.791
0.745
0.638
0.577
2.236
2.236
1.915
1.732
1
⁄
3
1
⁄
3
1
⁄
3
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast.
In the static drive mode, a suitable choice is VLCD > 3Vth(off)
.
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
Bias is calculated with Equation 2
(2)
The values for abias are:
abias = 1 for 1⁄2 bias
abias = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 3:
(3)
where the values for n are
nMUX = 1 for static drive mode
nMUX = 2 for 1:2 multiplex drive mode
nMUX = 3 for 1:3 multiplex drive mode
nMUX = 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 4:
(4)
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
Discrimination is a term which is defined as the ratio of the on and off RMS voltages
(Von(RMS) to Voff(RMS)) across a segment. It can be thought of as a measurement of
contrast. Discrimination is determined from Equation 5:
(5)
Using Equation 5, the discrimination for an LCD drive mode of 1:3 multiplex with 1⁄2 bias
is
and the discrimination for an LCD drive mode of 1:4 multiplex with 1⁄2 bias is
.
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage
VLCD as follows:
1:3 multiplex (1⁄2 bias):
•
•
1:4 multiplex (1⁄2 bias):
These compare with
when 1⁄3 bias is used.
VLCD is sometimes referred as the LCD operating voltage.
8.2.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel is switched on or off, determine the transmissibility of the
pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 10. For a good contrast performance, the following rules should be followed:
(6)
(7)
Von(RMS) (see Equation 3) and Voff(RMS) (see Equation 5) are properties of the display
driver and are affected by the selection of abias, nMUX, and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes named Vth. Vth(on) is sometimes named saturation
voltage Vsat
.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
100 %
90 %
10 %
V
[V]
RMS
V
V
th(on)
th(off)
OFF
SEGMENT
GREY
SEGMENT
ON
SEGMENT
013aaa494
Figure 10.ꢀElectro-optical characteristic: relative transmission curve of the liquid
8.2.2 LCD drive mode waveforms
8.2.2.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. The
backplane (COMn) and segment (SEGn) drive waveforms for this mode are shown in
Figure 11.
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
T
fr
LCD segments
V
LCD
COM0
SEGn
V
SS
state 1
(on)
state 2
(off)
V
LCD
V
SS
V
LCD
SEGn+1
V
SS
(a) Waveforms at driver.
V
LCD
0 V
state 1
- V
V
LCD
LCD
state 2
0 V
- V
LCD
(b) Resultant waveforms
at LCD segment.
aaa-011867
Vstate1(t) = VSEGn(t) - VCOM0(t).
Von(RMS) = VLCD
.
Vstate2(t) = V(SEGn + 1)(t) - VCOM0(t).
Voff(RMS) = 0 V.
Figure 11.ꢀStatic drive mode waveforms
8.2.2.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCF8551 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 12 and
Figure 13.
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
T
fr
V
LCD
LCD segments
V
V
/2
/2
COM0
COM1
SEGn
LCD
SS
state 1
state 2
V
LCD
V
V
LCD
SS
V
LCD
V
V
SS
LCD
SEGn+1
V
SS
(a) Waveforms at driver.
V
V
LCD
LCD
/2
0 V
- V
state 1
/2
LCD
- V
LCD
V
V
LCD
/2
LCD
0 V
state 2
- V
/2
LCD
LCD
- V
(b) Resultant waveforms
at LCD segment.
aaa-011868
Vstate1(t) = VSEGn(t) - VCOM0(t).
Von(RMS) = 0.791VLCD
Vstate2(t) = VSEGn(t) - VCOM1(t).
Voff(RMS) = 0.354VLCD
.
.
Figure 12.ꢀWaveforms for the 1:2 multiplex drive mode with 1⁄2 bias
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
T
fr
V
LCD
2V
LCD segments
/3
LCD
COM0
COM1
V
V
/3
LCD
SS
state 1
state 2
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
SEGn
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
SEGn+1
V
V
/3
LCD
SS
(a) Waveforms at driver.
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
- V
state 1
/3
LCD
-2V
/3
LCD
- V
LCD
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
- V
state 2
/3
LCD
-2V
/3
LCD
- V
LCD
(b) Resultant waveforms
at LCD segment.
aaa-011869
Vstate1(t) = VSEGn(t) - VCOM0(t).
Von(RMS) = 0.745VLCD
Vstate2(t) = VSEGn(t) - VCOM1(t).
Voff(RMS) = 0.333VLCD
Figure 13.ꢀWaveforms for the 1:2 multiplex drive mode with 1⁄3 bias
.
.
8.2.2.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as
shown in Figure 14.
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
T
fr
V
LCD
LCD segments
2V
/3
LCD
COM0
COM1
COM2
SEGn
V
V
/3
LCD
SS
state 1
state 2
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
SEGn+1
V
V
/3
LCD
SS
V
LCD
2V
/3
LCD
SEGn+2
V
V
/3
LCD
SS
(a) Waveforms at driver.
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
- V
state 1
/3
LCD
-2V
/3
LCD
- V
LCD
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
- V
state 2
/3
LCD
-2V
/3
LCD
- V
LCD
(b) Resultant waveforms
at LCD segment.
aaa-011870
Vstate1(t) = VSEGn(t) - VCOM0(t).
Von(RMS) = 0.638VLCD
Vstate2(t) = VSEGn(t) - VCOM1(t).
Voff(RMS) = 0.333VLCD
Figure 14.ꢀWaveforms for the 1:3 multiplex drive mode with 1⁄3 bias
.
.
8.2.2.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as
shown in Figure 15.
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
T
fr
V
LCD segments
LCD
2V
/3
LCD
/3
COM0
V
V
LCD
SS
state 1
state 2
V
2V
V
V
LCD
/3
LCD
/3
COM1
COM2
LCD
SS
V
2V
V
V
LCD
/3
LCD
/3
LCD
SS
V
LCD
2V
/3
LCD
/3
COM3
SEGn
V
V
LCD
SS
V
LCD
2V
/3
LCD
/3
V
V
LCD
SS
V
LCD
2V
/3
LCD
/3
SEGn+1
V
V
LCD
SS
V
LCD
2V
/3
LCD
/3
SEGn+2
SEGn+3
V
V
LCD
SS
V
LCD
2V
/3
LCD
/3
V
V
LCD
SS
(a) Waveforms at driver.
V
LCD
2V
/3
LCD
/3
V
LCD
0 V
- V
state 1
/3
LCD
-2V
/3
LCD
- V
LCD
V
LCD
2V
/3
LCD
V
/3
LCD
0 V
- V
state 2
/3
LCD
-2V
/3
LCD
- V
LCD
(b) Resultant waveforms
at LCD segment.
aaa-011871
Vstate1(t) = VSEGn(t) - VCOM0(t).
Von(RMS) = 0.577VLCD
Vstate2(t) = VSEGn(t) - VCOM1(t).
Voff(RMS) = 0.333VLCD
.
.
Figure 15.ꢀWaveforms for the 1:4 multiplex drive mode with 1⁄3 bias
8.3 Backplane and segment outputs
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
8.3.1 Backplane outputs
The LCD drive section includes four backplane outputs COM0 to COM3, which must
be directly connected to the LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than four backplane outputs are
required, the unused outputs can be left open-circuit.
• In 1:3 multiplex drive mode, COM3 carries the same signal as COM1, therefore these
two outputs can be tied together to give enhanced drive capabilities
• In 1:2 multiplex drive mode, COM0 and COM2, respectively, COM1 and COM3 all carry
the same signals and may also be paired to increase the drive capabilities
• In static drive mode, the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements
8.3.2 Segment outputs
The LCD drive section includes 36 segment outputs SEG0 to SEG35, which must be
directly connected to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display registers.
When less than 36 segment outputs are required, the unused segment outputs must be
left open-circuit.
9 Power Sequencing
9.1 Power-on
To avoid unwanted artifacts on the display, VLCD must never be asserted before VDD, it is
permitted to assert VDD and VLCD at the same time.
9.2 Power-off
Before turning the power to the device off, the display must be disabled by setting bit DE
to logic 0. To avoid unwanted artifacts on the display, VLCD must never be connected,
while VDD is switched off. It is permitted to switch off VDD and VLCD simultaneously.
9.3 Power sequences
Figure 16 depicts the recommended power-up and power-off sequence.
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
POWER-ON
(2)
POWER-OFF
Apply V
Disable display
DD
(1)
(1)
Remove V
LCD
Apply V
LCD
(2)
Reset
Remove V
DD
Write display data
Set device control
register
Set display control
register(s)
aaa-011937
Reset: internal power-on reset if PORE = 1, or software reset. If an external oscillator is used,
clock must be available after reset.
1. Can be simultaneous with VDD
2. Can be simultaneous with VLCD
Figure 16.ꢀRecommended power-up and power-off sequence
.
.
10 Bus interfaces
10.1 I2C-bus interface of the PCF8551A
The I2C-bus is for bidirectional, two-line communication between different ICs. The two
lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy. Both data and clock lines remain HIGH when the bus is not
busy. The PCF8551A acts as a slave receiver when being written to and as a slave
transmitter when being read from.
A
A
Write
Read
S
S
slave address + 0
A
write data
write data
write data
A
P
ACK from
slave
ACK from
slave
ACK from
slave
ACK from
slave
slave address + 1
A
read data
read data
A
A
P
read data
A
ACK from
master
ACK from
slave
ACK from
slave
ACK from
master
aaa-010487
Figure 17.ꢀI2C read and write protocol
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
2
I C write example
SCL
SDA
bit7
bit0 ACK bit7
bit0 ACK
P
S
1st byte, slave address with R/W = 0
write 2nd byte
START
STOP
ACK of 2nd byte
from slave
condition
condition
ACK of 1st byte
from slave
2
I C read example
SCL
SDA
bit7
read 2nd byte
0
bit
bit7
bit0 ACK
ACK
P
S
1st byte, slave address with R/W = 1
START
condition
STOP
condition
ACK of 1st byte
from slave
ACK of 2nd byte
from slave
aaa-010489
Figure 18.ꢀI2C read and write signaling
10.1.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must
remain stable during the HIGH period of the clock pulse, as changes in the data line at
this time are interpreted as STOP or START conditions.
10.1.2 START and STOP conditions
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the
START condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see Figure 18).
10.1.3 Acknowledge
Each byte of 8 bits is followed by an acknowledge cycle. An acknowledge is defined as
logic 0. A not-acknowledge is defined as logic 1.
When written to, the slave will generate an acknowledge after the reception of each byte.
After the acknowledge, another byte may be transmitted. It is also possible to send a
STOP or START condition.
When read from, the master receiver must generate an acknowledge after the reception
of each byte. When the master receiver no longer requires bytes to be transmitted, it
must generate a not-acknowledge. After the not-acknowledge, either a STOP or START
condition must be sent.
Remark: The PCF8551A omits the not-acknowledge. After the last byte read, the end of
transmission is indicated by a STOP or START condition from the master.
A detailed description of the I2C-bus specification is given in [5].
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
10.1.4 I2C interface protocol
The PCF8551A uses the I2C interface for data transfer. Interpretation of the data is
determined by the interface protocol.
10.1.4.1 Write protocol
After the I2C slave address is transmitted, the PCF8551A requires that the register
address pointer is defined. It can take the value 00h to 17h. Values outside of that
range will result in the transfer being ignored, however the slave will still respond with
acknowledge pulses.
After the register address has been transmitted, write data is transmitted. The minimum
number of data write bytes is 0 and the maximum number is unlimited. After each write,
the address pointer increments by one. After address 17h, the address pointer stops
incrementing at 18h.
• I2C START condition
• I2C slave address + write
• start register pointer
• write data
• write data
• :
• write data
• I2C STOP condition; an I2C RE-START condition is also possible.
10.1.4.2 Read protocol
When reading the PCF8551A, reading starts at the current position of the address
pointer. The address pointer for read data should first be defined by a write sequence.
• I2C START condition
• I2C slave address + write
• start address pointer
• I2C STOP condition; an I2C RE-START condition is also possible.
After setting the address pointer, a read can be executed. After the I2C slave address
is transmitted, the PCF8551A will immediately output read data. After each read, the
address pointer increments by one. After address 17h, the address pointer stops
incrementing at 18h.
• I2C START condition
• I2C slave address + read
• read data (master sends acknowledge bit)
• read data (master sends acknowledge bit)
• :
10.1.4.3 I2C-bus slave address
Device selection depends on the I2C-bus slave address (see Table 12).
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
Table 12.ꢀI2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
0
MSB
LSB
0
1
1
1
0
0
0
R/W
The least significant bit of the slave address byte is bit R/W (see Table 13).
Table 13.ꢀR/W-bit description
R/W
0
Description
write data
read data
1
10.2 SPI-bus interface of the PCF8551B
Data transfer to the device is made via a 3-line SPI-bus (see Table 14). There is no
dedicated output data line. The SPI-bus is initialized whenever the chip enable line pin
CE is pulled down.
Table 14.ꢀSerial interface
Symbol Function
Description
CE
chip enable input[1]; active LOW when HIGH, the interface is reset
SCL
SDIO
serial clock input
input may be higher than VDD
serial data input/output
input data are sampled on the rising edge of SCL,
output data are valid after the falling edge of SCL
[1] The chip enable must not be wired permanently LOW.
10.2.1 Data transmission
The chip enable signal is used to identify the transmitted data. Each data transfer is a
byte with the Most Significant Bit (MSB) sent first.
The transmission is controlled by the active LOW chip enable signal CE. The first byte
transmitted is the register address comprising of the address pointer and the R/W bit.
data bus
CE
REGISTER ADDRESS
DATA
DATA
DATA
aaa-011938
Figure 19.ꢀData transfer overview
Table 15.ꢀAddress byte definition
Bit
Symbol
Value
Description
7
R/W
data read or write selection
write data
0
1
read data
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PCF8551
Universal 36 × 4 LCD segment driver
Table 15.ꢀAddress byte definition...continued
Bit
Symbol
-
Value
Description
6 to 5
4 to 0
00
default value
AP[4:0]
pointer to register start address
valid range; other addresses are ignored
00h to 17h
After the register address byte, the register contents follows with the address pointer
being auto-incremented after every eighth bit sent (see Section 7.1).
10.2.1.1 Write protocol
After the CE is set LOW, the PCF8551B requires that R/W and the register address
pointer is defined. It can take the value 00h to 17h. Values outside of that range result in
the transfer being ignored.
After the register address has been transmitted, write data is transmitted. The minimum
number of data write bytes is 0 and the maximum number is unlimited. After each write,
the address pointer increments by one. After address 17h, the address pointer stops
incrementing at 18h.
• CE set LOW
• R/W = 0 and register address
• write data
• write data
• :
• write data
• CE set HIGH
R/W default
AP[4:0]
register data
register data
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
SCL
SDIO
CE
aaa-011951
Data transfers are terminated by de-asserting CE (set CE to logic 1).
Figure 20.ꢀSPI-bus write example: writing two data bytes to registers 00h and 01h
10.2.1.2 Read protocol
When reading the PCF8551B, reading starts at the defined position of the address
pointer. After setting the address pointer, the read can be executed. After each read,
the address pointer increments by one. After address 17h, the address pointer stops
incrementing at 18h.
• CE set LOW
• R/W = 1 and register address
• read data
• read data
• :
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
• CE set HIGH
R/W default
AP[4:0]
display data
display data
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
1
0
0
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
SCL
SDIO
CE
aaa-011954
Data transfers are terminated by de-asserting CE (set CE to logic 1).
Figure 21.ꢀSPI-bus read example: reading two data bytes from registers 04h and 05h
10.3 EMC detection
The PCF8551 is ruggedized against EMC susceptibility; however it is not possible to
cover all cases. To detect if a severe EMC event has occurred, it is possible to check the
responsiveness of the device by reading its registers.
11 Internal circuitry
V
DD
SCL, SDA/CE
PORE, SDIO, CLK
V
SS
V
V
SS
LCD
COM0 to
COM3
SEG0 to
SEG35
V
SS
aaa-013225
Figure 22.ꢀDevice protection diagram
12 Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe
precautions for handling electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5,
JESD625-A or equivalent standards.
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
CAUTION
Static voltages across the liquid crystal display can build up when the LCD
supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice
versa. This may cause unwanted display artifacts. To avoid such artifacts,
VLCD and VDD must be applied or removed together.
13 Limiting values
Table 16.ꢀLimiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
VLCD
VI
Parameter
Conditions
Min
-0.5
-0.5
-0.5
-0.5
-10
-10
-50
-50
-50
-
Max
+6.5
+6.5
+6.5
+6.5
+10
+10
+50
+50
+50
100
100
Unit
V
supply voltage
LCD supply voltage
input voltage
V
V
VO
output voltage
V
II
input current
mA
mA
mA
mA
mA
mW
mW
IO
output current
IDD
supply current
IDD(LCD)
ISS
LCD supply current
ground supply current
total power dissipation
output power
Ptot
Po
-
[1]
VESD
electrostatic discharge
voltage
HBM
on pins SCL, SDA, CE
on all other pins
CDM
-
±2ꢀ000
±5ꢀ000
±500
200
V
-
V
[2]
[3]
[4]
-
V
Ilu
latch-up current
-
mA
°C
°C
Tstg
Tamb
storage temperature
ambient temperature
-55
-40
+150
+85
operating device
[1] Pass level; Human Body Model (HBM), according to [1].
[2] Pass level; Charged-Device Model (CDM), according to [2].
[3] Pass level; latch-up testing according to [3] at maximum ambient temperature (Tamb(max)).
[4] According to the store and transport requirements (see [6]) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to
75 %.
14 Characteristics
Table 17.ꢀElectrical characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 5.5 V; Tamb = -40 °C to +85 °C; unless otherwise specified.
Symbol
Supplies
VDD
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
1.8
1.8
-
-
5.5
5.5
V
V
VLCD
LCD supply voltage
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PCF8551
Universal 36 × 4 LCD segment driver
Table 17.ꢀElectrical characteristics...continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 5.5 V; Tamb = -40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IDD
supply current
ffr = 64 Hz; no bus activity
VDD = 3.3 V; Tamb
25 °C
=
-
-
0.6
1.2
-
μA
μA
VDD = 5.5 V; Tamb
85 °C
=
2.7
[1]
IDD(LCD)
LCD supply current
ffr = 64 Hz; no bus activity
VLCD = 5.5 V; Tamb
85 °C; BOOST = 0;
=
-
3.2
4.5
μA
no display load
VLCD = 3.3 V; Tamb
25 °C
=
BOOST = 0;
no display load
-
-
2.5
4.5
-
-
μA
μA
BOOST = 0;
display enabled;
display load CL = 1.4 nF
BOOST = 1;
-
5.5
-
μA
display enabled;
display load CL = 1.4 nF
VIL
VIH
IOL
LOW-level input voltage
HIGH-level input voltage
LOW-level output current
VSS
-
-
0.3VDD
VDD
V
V
[2]
0.7VDD
output sink current; VOL
0.4 V; VDD = 5 V
=
on pin CLK
on pin SDIO
on pin SDA
2
2
3
2
-
-
-
-
-
-
-
-
mA
mA
mA
mA
IOH
HIGH-level output current output source current;
on pins SDIO, CLK; VOH
4.6 V; VDD = 5 V
=
IL
leakage current
any input pin except for RST
after ESD event
-
0
-
nA
nA
kΩ
-500
-
-
+500
-
Rpu(RST_n) pull-up resistance on pin
RST_N
100
LCD outputs (pins SEG0 to SEG17 and COM0 to COM3)
ΔVo
Ro
output voltage variation
output resistance
VLCD = 5 V
VLCD = 5 V
-100
-
-
+100
3
mV
kΩ
[3]
1.5
[1] For typical values, also see Figure 23 to Figure 25.
[2] I2C pins SCL and SDA have no diode to VDD and may be driven up to 5.5 V.
[3] Outputs measured one at a time.
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PCF8551
Universal 36 × 4 LCD segment driver
aaa-012359
3
2
3
10
10
I
I
DD
(nA)
DD(LCD)
(nA)
(1)
(2)
2
10
10
10
1
10
1
-50
-30
-10
10
30
50
70
amb
90
T
(°C)
VDD = 5.5 V, VLCD = 5.5 V; power-down mode.
1. IDD
2. IDD(LCD)
.
.
Figure 23.ꢀTypical IDD and IDD(LCD) in power-down mode as function of temperature
aaa-012153
12
I
(8)
(6)
DD(LCD)
(μA)
10
(4)
(7)
8
6
4
2
0
(5)
(2)
(3)
(1)
0
0.7
1.4
2
2.7
3.4
4.1
4.7
(nF)
5.4
C
L
Tamb = 25 °C; VLCD = 3.3 V; VDD = 3.3 V; ffr = 64 Hz, BOOST = 0.
1. Static, all segments/elements off.
2. Static, all segments/elements on.
3. MUX 1:2, bias level 1⁄2, all segments/elements off.
4. MUX 1:2, bias level 1⁄2, all segments/elements on.
5. MUX 1:3, bias level 1⁄3, all segments/elements off.
6. MUX 1:3, bias level 1⁄3, all segments/elements on.
7. MUX 1:4, bias level 1⁄3, all segments/elements off.
8. MUX 1:4, bias level 1⁄3, all segments/elements on.
Figure 24.ꢀTypical IDD(LCD) as function of display load
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
aaa-012360
8
I
DD(LCD)
(μA)
(8)
(6)
6
4
2
0
(7)
(4)
(5)
(3)
(2)
(1)
32
64
96
128
160
f
fr
(Hz)
Tamb = 25 °C; VLCD = 3.3 V; VDD = 3.3 V; ffr = 64 Hz, BOOST = 0, CL = 1.6 nF.
1. Static, all segments/elements off.
2. Static, all segments/elements on.
3. MUX 1:2, bias level 1⁄2, all segments/elements off.
4. MUX 1:2, bias level 1⁄2, all segments/elements on.
5. MUX 1:3, bias level 1⁄3, all segments/elements off.
6. MUX 1:3, bias level 1⁄3, all segments/elements on.
7. MUX 1:4, bias level 1⁄3, all segments/elements off.
8. MUX 1:4, bias level 1⁄3, all segments/elements on.
Figure 25.ꢀTypical IDD(LCD) as function of ffr
Table 18.ꢀFrequency characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 5.5 V; Tamb = -40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
-
Typ
32
64
96
128
1024
-
Max
Unit
Hz
Hz
Hz
Hz
Hz
Hz
μs
ffr
frame frequency
FF[1:0] = 00
-
FF[1:0] = 01
42
-
86
FF[1:0] = 10
-
FF[1:0] = 11
-
-
[1]
[1]
fclk(int)
fclk(ext)
tclk(H)
tclk(L)
internal clock frequency
external clock frequency
HIGH-level clock time
LOW-level clock time
reset pulse width
ffr = 64 Hz, nMUX = 4
-
-
-
4096
external clock
external clock
on pin RST
60
60
10
-
-
-
-
-
μs
tw(rst)
-
μs
[1]
or
respectively (see Table 5 and Table 6).
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
aaa-012364
1536
f
clk
(Hz)
1280
(4)
(3)
(2)
(1)
1024
768
512
256
0
32
64
96
128
160
f
fr
(Hz)
1. nMUX = 1.
2. nMUX = 2.
3. nMUX = 3.
4. nMUX = 4.
Figure 26.ꢀRelation of frame frequency (ffr), clock frequency (fclk) and multiplex-rate (nMUX
)
Table 19.ꢀI2C-bus characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; unless otherwise specified; all timing values are valid within the
[1]
operating supply voltage and Tamb range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD
.
Symbol
Pin SCL
fSCL
Parameter
Conditions
Min
Typ
Max
Unit
SCL clock frequency
-
-
-
400
-
kHz
μs
tLOW
LOW period of the SCL
clock
1.3
tHIGH
HIGH period of the SCL
clock
0.6
-
-
μs
Pin SDA
tSU;DAT
data set-up time
data hold time
100
0
-
-
-
-
ns
ns
tHD;DAT
Pins SCL and SDA
tBUF
bus free time between
1.3
-
-
μs
a STOP and START
condition
tSU;STO
tHD;STA
tSU;STA
set-up time for STOP
condition
0.6
0.6
0.6
-
-
-
-
-
-
μs
μs
μs
hold time (repeated)
START condition
set-up time for a repeated
START condition
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PCF8551
Universal 36 × 4 LCD segment driver
Table 19.ꢀI2C-bus characteristics...continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; unless otherwise specified; all timing values are valid within the
[1]
operating supply voltage and Tamb range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD
.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
μs
tr
rise time of both SDA and fSCL = 400 kHz
SCL signals
-
-
0.3
tf
fall time of both SDA and
SCL signals
-
-
-
-
-
-
0.3
400
50
μs
pF
ns
Cb
capacitive load for each
bus line
tw(spike)
spike pulse width
on the I2C-bus
[1] The I2C-bus interface of PCF8551A is 5 V tolerant.
SDA
t
t
t
f
BUF
LOW
SCL
SDA
t
HD;STA
t
r
t
t
SU;DAT
HD;DAT
t
HIGH
t
SU;STA
t
SU;STO
mga728
Figure 27.ꢀI2C-bus timing waveforms
Table 20.ꢀSPI-bus characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; unless otherwise specified; all timing values are valid within the
operating supply voltage and Tamb range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD
.
Symbol
Pin SCL
fSCL
Parameter
Conditions
Min
Typ
Max
Unit
SCL clock frequency
-
-
-
5
-
MHz
ns
tLOW
LOW period of the SCL
clock
150
tHIGH
HIGH period of the SCL
clock
80
-
-
ns
tr
rise time
fall time
-
-
-
-
100
100
ns
ns
tf
Pin CE
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
Table 20.ꢀSPI-bus characteristics...continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +85 °C; unless otherwise specified; all timing values are valid within the
operating supply voltage and Tamb range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD
.
Symbol
tsu(CE_N)
th(CE_N)
trec(CE_N)
Pin SDIO
tsu
Parameter
Conditions
Min
30
Typ
Max
Unit
ns
ns
ns
CE_N set-up time
CE_N hold time
CE_N recovery time
-
-
-
-
-
-
10
70
set-up time
write data
write data
CL = 50 pF
no load
5
50
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
th
hold time
-
td(R)SDIO
tdis(SDIO)
SDIO read delay time
SDIO disable time
150
50
-
-
tt(SDI-SDO) transition time from SDI to write to read mode
SDO
0
CE
t
t
t
su(CE_N)
rec(CE_N)
r
t
t
h(CE_N)
f
80 %
SCL
20 %
t
LOW
t
HIGH
t
su
WRITE
t
h
R/W
SDIO
SA2
RA0
b7
b6
b0
READ
SDI
b7
b6
b0
t
t(SDI-SDO)
SDIO
t
t
d(R)SDIO
dis(SDIO)
high-Z
b7
b6
b0
SDO
aaa-012166
Figure 28.ꢀSPI-bus timing waveforms
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
15 Application information
15.1 Power-on Reset
The built-in POR block acts on the rising edge of the VDD supply voltage. Depending
on the VDD rising edge in the application, the POR may not work properly. Therefore to
ensure proper device operation it is required to send nine clock pulses immediately after
power-on (see also UM10204).
15.2 I2C acknowledge after power-on
If the bus does not show an acknowledge at the first access, the command should be
sent a second time.
15.3 Resistors on I/O pins
The pin PORE comprises an internal, latching pull-down device, which keeps the input at
a low potential when left open. If the input is supposed to be at logic 0 potential, this pin
can be either connected to VSS or left open.
In case the pin is supposed to be at logic 1 potential, it must be connected to VDD to
avoid any cross-current during power-up. A series resistance between VDD and PORE
must not exceed 1 kΩ to ensure proper functionality.
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PCF8551
Universal 36 × 4 LCD segment driver
16 Package outline
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
D
E
A
X
c
v
A
H
E
y
Z
48
25
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
24
detail X
w
b
p
e
0
5 mm
2.5
scale
Dimensions (mm are the original dimensions)
Unit
max
(1)
(2)
A
A
A
A
b
c
D
E
e
H
L
1
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
°
8
0
0.15 1.05
0.05 0.85
0.28 0.2 12.6 6.2
0.17 0.1 12.4 6.0
8.3
7.9
0.8 0.50
0.4 0.35
0.8
0.4
mm nom 1.2
min
0.25
0.5
0.25 0.08 0.1
°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
sot362-1_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
03-02-19
13-08-05
SOT362-1
MO-153
Figure 29.ꢀPackage outline SOT362-1 (TSSOP48) of PCF8551
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
17 Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IECꢀꢀ61340-5 or equivalent
standards.
18 Packing information
18.1 Tape and reel information
For tape and reel packing information, see [4].
19 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
19.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
19.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
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PCF8551
Universal 36 × 4 LCD segment driver
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
19.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
19.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 30) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 21 and Table 22
Table 21.ꢀSnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
235
≥ 350
< 2.5
≥ 2.5
220
220
220
Table 22.ꢀLead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 30.
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 30.ꢀTemperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
20 Footprint information
Footprint information for reflow soldering of TSSOP48 package
SOT362-1
Hx
Gx
P2
(0.125)
(0.125)
Hy Gy
By Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.500 0.560 8.900 6.100 1.400 0.280 0.400 12.270 7.000 14.100 9.150
sot362-1_fr
Figure 31.ꢀFootprint information for reflow soldering of SOT362-1 (TSSOP48) of PCF8551
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
21 Appendix
21.1 LCD segment driver selection
Table 23.ꢀSelection of LCD segment drivers
Type name
Number of elements at MUX
VDD (V)
VLCD (V)
ffr (Hz)
VLCD (V) VLCD (V)
Tamb (°C)
Interface Package
AEC-
Q100
charge
pump
temperature
compensat.
1:1 1:2 1:3 1:4 1:6 1:8 1:9
PCA8553DTT
PCA8546ATT
PCA8546BTT
PCA8547AHT
PCA8547BHT
PCF85134HL
PCA85134H
PCA8543AHL
PCF8545ATT
PCF8545BTT
PCF8536AT
PCF8536BT
PCA8536AT
PCA8536BT
PCF8537AH
PCF8537BH
PCA8537AH
PCA8537BH
PCA9620H
40
-
80
-
120 160
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
2.5 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
2.5 to 5.5
2.5 to 5.5
1.8 to 5.5
1.8 to 5.5
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 6.5
2.5 to 8
2.5 to 9
2.5 to 5.5
2.5 to 5.5
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 6.5
32 to 256[1]
60 to 300[1]
60 to 300[1]
60 to 300[1]
60 to 300[1]
82
N
N
N
Y
Y
N
N
Y
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
N
N
N
N
Y
Y
N
N
Y
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
N
-40 to 105 I2C / SPI
TSSOP56
TSSOP56
TSSOP56
TQFP64
TQFP64
LQFP80
LQFP80
LQFP80
TSSOP56
TSSOP56
TSSOP56
TSSOP56
TSSOP56
TSSOP56
TQFP64
TQFP64
TQFP64
TQFP64
LQFP80
Bare die
Bare die
Y
Y
Y
Y
Y
N
Y
Y
N
N
N
N
Y
Y
N
N
Y
Y
Y
Y
N
-
-
-
-
176
176
176
176
-40 to 95
-40 to 95
-40 to 95
-40 to 95
-40 to 85
-40 to 95
I2C
SPI
I2C
SPI
I2C
I2C
-
-
44
44
60
60
60
-
88
88
120 180 240
120 180 240
82
120
-
-
-
-
-
-
-
-
-
-
-
-
-
-
240
60 to 300[1]
60 to 300[1]
60 to 300[1]
60 to 300[1]
60 to 300[1]
60 to 300[1]
60 to 300[1]
60 to 300[1]
60 to 300[1]
60 to 300[1]
60 to 300[1]
60 to 300[1]
60 to 300[1]
77
-40 to 105 I2C
176 252 320
176 252 320
176 252 320
176 252 320
176 252 320
176 252 320
176 276 352
176 276 352
176 276 352
176 276 352
240 320 480
240 320 480
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 95
-40 to 95
-40 to 85
-40 to 85
-40 to 95
-40 to 95
I2C
SPI
I2C
SPI
I2C
SPI
I2C
SPI
I2C
SPI
-
-
-
-
-
-
-
-
-
-
44
44
44
44
60
60
40
88
88
88
88
120
120
80
-40 to 105 I2C
-40 to 105 I2C
PCA9620U
PCF8576DU
120 160
-
-
-40 to 85
I2C
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
Table 23.ꢀSelection of LCD segment drivers...continued
Type name
Number of elements at MUX
VDD (V)
VLCD (V)
ffr (Hz)
VLCD (V) VLCD (V)
Tamb (°C)
Interface Package
AEC-
Q100
charge
pump
temperature
compensat.
1:1 1:2 1:3 1:4 1:6 1:8 1:9
PCF8576EUG
PCA8576FUG
PCF85133U
PCA85133U
PCA85233UG
PCF85132U
PCA8530DUG
PCA85132U
PCA85232U
PCF8538UG
PCA8538UG
40
40
80
80
80
80
80
120 160
120 160
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
2.5 to 5.5
1.8 to 5.5
1.8 to 5.5
2.5 to 6.5
2.5 to 8
2.5 to 6.5
2.5 to 8
2.5 to 8
1.8 to 8
4 to 12
77
N
N
N
N
N
N
Y
N
N
Y
Y
N
N
N
N
N
N
Y
N
N
Y
Y
-40 to 85
-40 to 105 I2C
I2C
Bare die
Bare die
Bare die
Bare die
Bare die
Bare die
Bare die
Bare die
Bare die
Bare die
Bare die
N
Y
N
Y
Y
N
Y
Y
Y
N
Y
200
160 240 320
160 240 320
160 240 320
82, 110[2]
82, 110[2]
150, 220[2]
60 to 90[1]
45 to 300[1]
60 to 90[1]
117 to 176[1]
45 to 300[1]
45 to 300[1]
-40 to 85
-40 to 95
-40 to 105 I2C
-40 to 85
I2C
-40 to 105 I2C / SPI
I2C
I2C
160 320 480 640
102 204 408
-
160 320 480 640
160 320 480 640
1.8 to 8
1.8 to 8
4 to 12
-40 to 95
-40 to 95
-40 to 85
I2C
I2C
I2C / SPI
102 204
102 204
-
-
408 612 816 918 2.5 to 5.5
408 612 816 918 2.5 to 5.5
4 to 12
-40 to 105 I2C / SPI
[1] Software programmable.
[2] Hardware selectable.
PCF8551
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Universal 36 × 4 LCD segment driver
22 Abbreviations
Table 24.ꢀAbbreviations
Acronym
CDM
DC
Description
Charged-Device Model
Direct Current
EMC
ESD
HBM
I2C
ElectroMagnetic Compatibility
ElectroStatic Discharge
Human Body Model
Inter-Integrated Circuit bus
Integrated Circuit
IC
LCD
LSB
MSB
MSL
MUX
PCB
POR
RC
Liquid Crystal Display
Least Significant Bit
Most Significant Bit
Moisture Sensitivity Level
Multiplexer
Printed-Circuit Board
Power-On Reset
Resistance-Capacitance
Root Mean Square
Serial CLock line
RMS
SCL
SDA
SMD
SPI
Serial DAta line
Surface-Mount Device
Serial Peripheral Interface
23 References
[1] JESD22-A114 Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model
(HBM)
[2] JESD22-C101 Field-Induced Charged-Device Model Test Method for Electrostatic-
Discharge-Withstand Thresholds of Microelectronic Components
[3] JESD78 IC Latch-Up Test
[4] SOT362-1_118 TSSOP48; Reel pack; SMD, 13", packing information
[5] UM10204 I2C-bus specification and user manual
[6] UM10569 Store and transport requirements
PCF8551
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Universal 36 × 4 LCD segment driver
24 Revision history
Table 25.ꢀRevision history
Document ID
PCF8551 v.3.1
Modifications:
PCF8551 v.3
Modifications:
Release date
20210503
Data sheet status
Change notice
Supersedes
Product data sheet
202005038F01
PCF8551 v.3
• Section 4: Added "Y" parts with improved package
20210421 Product data sheet 202104033I
• Updated ordering information to new format
PCF8551 v.2
• Section 7.3: Added "See also application information..."
• Section 7.3.2: Added "The bus interface is initialized"
• Updated Section 15.1
PCF8551 v.2
Modifications:
20150216
Product data sheet
-
PCF8551 v.1
• Adjusted IDD and IDD(LCD) values in Table 17
• Switched to Product data sheet
PCF8551 v.1
20141205
Objective data sheet
-
-
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
25 Legal information
25.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
25.2 Definitions
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
25.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
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PCF8551
Universal 36 × 4 LCD segment driver
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of non-
automotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
25.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
NXP — wordmark and logo are trademarks of NXP B.V.
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PCF8551
Universal 36 × 4 LCD segment driver
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Ordering Information ......................................... 2
Tab. 11. Biasing characteristics .....................................16
Tab. 12. I2C slave address byte ................................... 28
Tab. 13. R/W-bit description ..........................................28
Tab. 14. Serial interface ................................................ 28
Tab. 15. Address byte definition ....................................28
Tab. 16. Limiting values ................................................ 31
Tab. 17. Electrical characteristics ..................................31
Tab. 18. Frequency characteristics ............................... 34
Tab. 19. I2C-bus characteristics ....................................35
Tab. 20. SPI-bus characteristics ....................................36
Tab. 21. SnPb eutectic process (from J-STD-020D) ..... 41
Tab. 22. Lead-free process (from J-STD-020D) ............41
Tab. 23. Selection of LCD segment drivers ...................44
Tab. 24. Abbreviations ...................................................46
Tab. 25. Revision history ...............................................47
Ordering options ................................................2
Pin description ...................................................5
Registers of the PCF8551 .................................6
Device_ctrl - device control command
register (address 01h) bit description ................8
Display_ctrl_1 - display control command 1
register (address 02h) bit description ................8
Display_ctrl_2 - display control command 2
register (address 03h) bit description ................9
Software_reset - software reset command
register (address 00h) bit description ..............11
Register to segment and backplane
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
mapping ...........................................................11
Tab. 10. Selection of possible display configurations .... 14
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Block diagram of PCF8551A .............................3
Block diagram of PCF8551B .............................3
Pin configuration of PCF8551ATT
(TSSOP48) ........................................................4
Pin configuration of PCF8551BTT
(TSSOP48) ........................................................5
Address counter incrementing ...........................7
Display RAM organization bitmap for MUX
1:4 ................................................................... 13
Example of displays suitable for PCF8551 ......14
Typical system configuration using I2C-bus,
internal power-on reset disabled ..................... 15
Typical system configuration using SPI-
Fig. 16. Recommended power-up and power-off
sequence .........................................................25
Fig. 17. I2C read and write protocol .............................25
Fig. 18. I2C read and write signaling ........................... 26
Fig. 19. Data transfer overview .................................... 28
Fig. 20. SPI-bus write example: writing two data
bytes to registers 00h and 01h ........................29
Fig. 21. SPI-bus read example: reading two data
bytes from registers 04h and 05h ....................30
Fig. 22. Device protection diagram .............................. 30
Fig. 23. Typical IDD and IDD(LCD) in power-down
mode as function of temperature .................... 33
Fig. 24. Typical IDD(LCD) as function of display
load ..................................................................33
Fig. 25. Typical IDD(LCD) as function of ffr ..................34
Fig. 26. Relation of frame frequency (ffr), clock
frequency (fclk) and multiplex-rate (nMUX) ..... 35
Fig. 27. I2C-bus timing waveforms ...............................36
Fig. 28. SPI-bus timing waveforms .............................. 37
Fig. 29. Package outline SOT362-1 (TSSOP48) of
PCF8551 ......................................................... 39
Fig. 30. Temperature profiles for large and small
components .....................................................42
Fig. 31. Footprint information for reflow soldering of
SOT362-1 (TSSOP48) of PCF8551 ................ 43
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
bus, internal power-on reset enabled ..............15
Fig. 10. Electro-optical characteristic: relative
transmission curve of the liquid .......................18
Fig. 11.
Static drive mode waveforms ..........................19
Fig. 12. Waveforms for the 1:2 multiplex drive mode
with 1⁄2 bias .................................................... 20
Fig. 13. Waveforms for the 1:2 multiplex drive mode
with 1⁄3 bias .................................................... 21
Fig. 14. Waveforms for the 1:3 multiplex drive mode
with 1⁄3 bias .................................................... 22
Fig. 15. Waveforms for the 1:4 multiplex drive mode
with 1⁄3 bias .................................................... 23
PCF8551
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PCF8551
Universal 36 × 4 LCD segment driver
Contents
1
2
General description ............................................ 1
10.2.1.1 Write protocol ...................................................29
10.2.1.2 Read protocol .................................................. 29
Features and benefits .........................................1
Applications .........................................................1
Ordering information .......................................... 2
Ordering options ................................................ 2
Block diagram ..................................................... 3
Pinning information ............................................ 4
Pinning ...............................................................4
Pin description ...................................................5
Functional description ........................................6
Registers of the PCF8551 .................................6
Command registers of the PCF8551 ................. 7
Command: Device_ctrl ...................................... 7
Internal oscillator and clock output .................... 8
Command: Display_ctrl_1 ..................................8
Enhanced power drive mode .............................9
Multiplex drive mode ......................................... 9
Command: Display_ctrl_2 ..................................9
Blinking ............................................................ 10
Line inversion (driving scheme A) and
frame inversion (driving scheme B) ................. 10
Starting and resetting the PCF8551 ................ 10
Power-down mode ...........................................10
Power-On Reset (POR) ...................................10
Command: Software_reset .............................. 11
Display data register mapping .........................11
Possible display configurations ...................... 14
LCD bias generator ......................................... 15
LCD voltage selector ....................................... 16
Electro-optical performance .............................17
LCD drive mode waveforms ............................ 18
Static drive mode .............................................18
1:2 Multiplex drive mode ................................. 19
1:3 Multiplex drive mode ................................. 21
1:4 Multiplex drive mode ................................. 22
Backplane and segment outputs ..................... 23
Backplane outputs ........................................... 24
Segment outputs ............................................. 24
Power Sequencing ............................................24
Power-on ..........................................................24
Power-off ..........................................................24
Power sequences ............................................ 24
Bus interfaces ................................................... 25
I2C-bus interface of the PCF8551A .................25
Bit transfer ....................................................... 26
START and STOP conditions .......................... 26
Acknowledge ....................................................26
I2C interface protocol ...................................... 27
3
4
4.1
5
6
6.1
6.2
7
10.3
11
12
13
14
EMC detection .................................................30
Internal circuitry ................................................30
Safety notes .......................................................30
Limiting values ..................................................31
Characteristics .................................................. 31
Application information ....................................38
Power-on Reset ...............................................38
I2C acknowledge after power-on .....................38
Resistors on I/O pins .......................................38
Package outline .................................................39
Handling information ........................................40
Packing information ..........................................40
Tape and reel information ................................40
Soldering of SMD packages .............................40
Introduction to soldering .............................
Wave and reflow soldering .........................
Wave soldering ...........................................
Reflow soldering .........................................
Footprint information ........................................43
Appendix ............................................................44
LCD segment driver selection ......................... 44
Abbreviations .................................................... 46
References .........................................................46
Revision history ................................................ 47
Legal information ..............................................48
15
15.1
15.2
15.3
16
17
18
7.1
7.2
7.2.1
7.2.1.1
7.2.2
7.2.2.1
7.2.2.2
7.2.3
7.2.3.1
7.2.3.2
18.1
19
19.1
19.2
19.3
19.4
20
21
21.1
22
7.3
7.3.1
7.3.2
7.3.3
7.4
8
8.1
23
24
25
8.2
8.2.1
8.2.2
8.2.2.1
8.2.2.2
8.2.2.3
8.2.2.4
8.3
8.3.1
8.3.2
9
9.1
9.2
9.3
10
10.1
10.1.1
10.1.2
10.1.3
10.1.4
10.1.4.1 Write protocol ...................................................27
10.1.4.2 Read protocol .................................................. 27
10.1.4.3 I2C-bus slave address .....................................27
10.2
10.2.1
SPI-bus interface of the PCF8551B .................28
Data transmission ............................................28
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 May 2021
Document identifier: PCF8551
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