PCF85134HL-1_技术文档

PCF85134

Universal LCD driver for low multiplex rates

Rev. 01 — 17 December 2009

Product data sheet

1. General description

The PCF85134 is a peripheral device which interfaces to almost any LCD¹with low

multiplex rates. It generates the drive signals for any static or multiplexed LCD containing

up to four backplanes and up to 60 segments. In addition, the PCF85134 can be easily

cascaded for larger LCD applications. The PCF85134 is compatible with most

microprocessors or microcontrollers and communicates via a two-line bidirectional

I²C-bus. Communication overheads are minimized using display RAM with

auto-incremented addressing, hardware subaddressing, and display memory switching

(static and duplex drive modes).

2. Features

I Single-chip LCD controller and driver

I Selectable backplane drive conﬁgurations: static, 2, 3, or 4 backplane multiplexing

I 60 segment outputs allowing to drive:

N 30 7-segment alphanumeric characters

N 16 14-segment alphanumeric characters

N Any graphics of up to 240 elements

I Cascading supported for larger applications

I 60 × 4-bit display data storage RAM

I Wide LCD supply range: from 2.5 V for low threshold LCDs up to 6.5 V for guest-host

LCDs and high threshold twisted nematic LCDs

I Internal LCD bias generation with voltage follower buffers

I Selectable display bias conﬁgurations: static, ¹⁄₂, or ¹⁄₃

I Wide logic power supply range: from 1.8 V to 5.5 V

I LCD and logic supplies may be separated

I Low power consumption

I 400 kHz I²C-bus interface

I Compatible with any microprocessor or microcontroller

I No external components required

I Display memory bank switching in static and duplex drive mode

I Auto-incremented display data loading

I Versatile blink modes

I Silicon gate CMOS process

1. The deﬁnition of the abbreviations and acronyms used in this data sheet can be found in Section 17.

PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Delivery form

Version

PCF85134HL/1

LQFP80

plastic low proﬁle quad ﬂat package;

tape and reel

SOT315-1

80 leads; body 12 × 12 × 1.4 mm

4. Marking

Table 2.

Marking codes

Type number

Marking code

PCF85134HL

PCF85134HL/1

PCF85134_1

Product data sheet

Rev. 01 — 17 December 2009

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PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

5. Block diagram

BP0 BP1 BP2 BP3

S0 to S59

60

V

LCD

BACKPLANE

OUTPUTS

DISPLAY SEGMENT OUTPUTS

DISPLAY REGISTER

LCD

VOLTAGE

SELECTOR

OUTPUT BANK SELECT

AND BLINK CONTROL

DISPLAY

CONTROL

LCD BIAS

GENERATOR

V

SS

DISPLAY

RAM

PCF85134

CLK

BLINKER

CLOCK SELECT

TIMEBASE

AND TIMING

SYNC

COMMAND

DECODE

DATA POINTER AND

AUTO INCREMENT

WRITE DATA

CONTROL

POWER-ON

RESET

OSC

OSCILLATOR

SCL

SDA

2

SUBADDRESS

COUNTER

INPUT

FILTERS

I C-BUS

CONTROLLER

A0 A1 A2

SA0

V

DD

013aaa204

Fig 1. Block diagram of PCF85134

PCF85134_1

Product data sheet

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PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

6. Pinning information

6.1 Pinning

1

2

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

S31

S32

S33

S34

S35

S36

S37

S38

S39

S40

S41

S42

S43

S44

S45

S46

S47

S48

S49

S50

S10

S9

S8

S7

S6

S5

S4

S3

S2

S1

S0

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

PCF85134

V

LCD

V

SS

SA0

A2

A1

A0

OSC

SYNC

V

DD

013aaa205

Top view. For mechanical details, see Figure 22.

Fig 2. Pin conﬁguration for SOT315-1 (PCF85134)

PCF85134_1

Product data sheet

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PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

6.2 Pin description

Table 3.

Symbol

S31 to S59

BP0 to BP3

n.c.

Pin description

Description

1 to 29

30 to 33

34 to 37

38

LCD segment output 31 to 59

LCD backplane output 0 to 3

not connected

I²C-bus serial data input and output

I²C-bus serial clock input

SDA

SCL

39

CLK

40

external clock input and internal clock output

supply voltage

V_DD

41

SYNC

OSC

42

cascade synchronization input and output (active LOW)

enable input for internal oscillator

subaddress counter input 0 to 2

I²C-bus slave address input 0

ground supply voltage

43

A0 to A2

SA0

44 to 46

47

V_SS

48

V_LCD

49

input of LCD supply voltage

LCD segment output 0 to 30

S0 to S30

50 to 80

PCF85134_1

Product data sheet

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PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

7. Functional description

The PCF85134 is a versatile peripheral device designed to interface any microprocessor

or microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed

LCD containing up to four backplanes and up to 60 segments.

The display conﬁgurations possible with the PCF85134 depend on the number of active

backplane outputs required. A selection of display conﬁgurations is shown in Table 4. All

of these conﬁgurations can be implemented in the typical system shown in Figure 3.

Table 4.

Selection of display conﬁgurations

7-segment alphanumeric

Digits Indicator symbols

30 30

Number of

14-segment alphanumeric

Dot matrix

Backplanes Elements

Characters

Indicator symbols

4

3

2

1

240

180

120

60

16

12

8

16

12

8

240 (4 × 60)

180 (3 × 60)

120 (2 × 60)

60 (1 × 60)

22

15

7

26

15

11

4

V

DD

t

r

R

≤

2C

b

V

DD

V

LCD

60 segment drives

SDA

SCL

HOST

MICRO-

LCD PANEL

PROCESSOR/

MICRO-

CONTROLLER

PCF85134

(up to 240

elements)

4 backplanes

OSC

A0 A1 A2 SA0

V

SS

013aaa206

V

SS

Fig 3. Typical system conﬁguration

The host microprocessor or microcontroller maintains the 2-line I²C-bus communication

channel with the PCF85134.

Biasing voltages for the multiplexed LCD waveforms are generated internally, removing

the need for an external bias generator. The internal oscillator is selected by connecting

pin OSC to V_SS. The only other connections required to complete the system are the

power supplies (pins V_DD, V_SSand V_LCD) and the LCD panel selected for the application.

7.1 Power-On Reset (POR)

At power-on, the PCF85134 resets to the following default starting conditions:

• All backplane outputs are set to V_LCD

• All segment outputs are set to V_LCD

• The selected drive mode is: 1:4 multiplex with ¹⁄₃bias

• Blinking is switched off

• Input and output bank selectors are reset

PCF85134_1

Product data sheet

Rev. 01 — 17 December 2009

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PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

• The I²C-bus interface is initialized

• The data pointer and the subaddress counter are cleared (set to logic 0)

• The display is disabled

Remark: Do not transfer data on the I²C-bus for at least 1 ms after a power-on to allow the

reset action to complete.

7.2 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider of three

series resistors connected between pins V_LCDand V_SS. The center resistor is bypassed

by switch if the ¹⁄₂bias voltage level for the 1:2 multiplex drive mode conﬁguration is

selected.

7.3 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the

selected LCD drive conﬁguration. The operation of the voltage selector is controlled by the

mode-set command (see Table 10) from the command decoder. The biasing

conﬁgurations that apply to the preferred modes of operation, together with the biasing

characteristics as functions of V_LCDand the resulting discrimination ratios (D) are given in

Table 5.

Biasing characteristics

Number of:

LCD drive

mode

LCD bias

conﬁguration

V _{off (RMS)}

V _on(RMS)

--------------------------

V _LCD

D = --------------------------

V _{off (RMS)}

------------------------

V _LCD

Backplanes Levels

static

1

2

3

4

2

3

4

static

0

1

∞

1

⁄

1:2 multiplex

1:3 multiplex

1:4 multiplex

0.354

0.333

0.791

0.745

0.638

0.577

2.236

1.915

1.732

2

1

⁄

3

1

⁄

3

1

⁄

3

A practical value for V_LCDis determined by equating V_off(RMS)with a deﬁned LCD

threshold voltage (V_th), typically when the LCD exhibits approximately 10 % contrast. In

the static drive mode a suitable choice is V_LCD> 3V_th.

Multiplex drive modes of 1:3 and 1:4 with ¹⁄₂bias are possible but the discrimination and

hence the contrast ratios are smaller.

1

Bias is calculated by ------------ , where the values for a are

1 + a

a = 1 for ¹⁄₂bias

a = 2 for ¹⁄₃bias

The RMS on-state voltage (V_on(RMS)) for the LCD is calculated with Equation 1:

a²+ 2a + n

n × (1 + a)²

V_on(RMS)= V

-----------------------------

(1)

LCD

PCF85134_1

Product data sheet

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PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

where the values for n are

n = 1 for static drive mode

n = 2 for 1:2 multiplex drive mode

n = 3 for 1:3 multiplex drive mode

n = 4 for 1:4 multiplex drive mode

The RMS off-state voltage (V_off(RMS)) for the LCD is calculated with Equation 2:

a²– 2a + n

n × (1 + a)²

V_{off (RMS)}= V

-----------------------------

(2)

(3)

LCD

Discrimination is the ratio of V_on(RMS)to V_off(RMS)and is determined from Equation 3:

(a + 1)²+ (n – 1)

V _on(RMS)

D =

=

-------------------------------------------

------------------------

(a – 1)²+ (n – 1)

V _{off (RMS)}

Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with

¹⁄₂bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with

21

¹⁄₂bias is ---------- = 1.528 .

3

The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V_LCD

as follows:

• 1:3 multiplex (¹⁄₂bias):V _LCD

• 1:4 multiplex (¹⁄₂bias):V _LCD

=

6 × V _{off (RMS)}= 2.449V _{off (RMS)}

(4 × 3)

= 2.309V _{off (RMS)}

---------------------

3

These compare withV _LCD= 3V _{off (RMS)}when ¹⁄₃bias is used.

It should be noted that V_LCDis sometimes referred as the LCD operating voltage.

PCF85134_1

Product data sheet

Rev. 01 — 17 December 2009

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PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.4 LCD drive mode waveforms

7.4.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD.

Backplane and segment drive waveforms for this mode are shown in Figure 4.

T

fr

LCD segments

V

LCD

BP0

Sn

V

SS

state 1

(on)

state 2

(off)

V

LCD

V

SS

V

LCD

Sn+1

V

SS

(a) Waveforms at driver.

V

LCD

0 V

state 1

−V

LCD

V

LCD

state 2

0 V

−V

LCD

(b) Resultant waveforms

at LCD segment.

013aaa207

V_state1(t) = V_Sn(t) − V_BP0(t).

V_on(RMS)= V_LCD

.

V_state2(t) = V_{(Sn + 1)}(t) − V_BP0(t).

V_off(RMS)= 0 V.

Fig 4. Static drive mode waveforms

PCF85134_1

Product data sheet

Rev. 01 — 17 December 2009

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PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.4.2 1:2 Multiplex drive mode

When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The

PCF85134 allows the use of ¹⁄₂bias or ¹⁄₃bias in this mode as shown in Figure 5 and

Figure 6.

T

fr

V

LCD

LCD segments

V

/2

BP0

BP1

Sn

LCD

SS

state 1

V

LCD

state 2

V

LCD

SS

V

LCD

V

SS

LCD

Sn+1

V

SS

(a) Waveforms at driver.

V

LCD

/2

LCD

0 V

−V

state 1

/2

LCD

−V

LCD

V

LCD

/2

LCD

0 V

state 2

−V

/2

LCD

−V

(b) Resultant waveforms

at LCD segment.

013aaa208

V_state1(t) = V_Sn(t) − V_BP0(t).

V_on(RMS)= 0.791V_LCD

V_state2(t) = V_Sn(t) − V_BP1(t).

V_off(RMS)= 0.354V_LCD

.

Fig 5. Waveforms for the 1:2 multiplex drive mode with ¹⁄₂bias

PCF85134_1

Product data sheet

Rev. 01 — 17 December 2009

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PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

T

fr

V

LCD

LCD segments

2V

/3

LCD

BP0

BP1

Sn

V

/3

LCD

SS

state 1

V

LCD

state 2

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+1

V

/3

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

/3

LCD

V

/3

LCD

0 V

−V

state 1

/3

LCD

−2V

/3

LCD

−V

LCD

V

LCD

2V

/3

LCD

V

/3

LCD

0 V

−V

state 2

/3

LCD

−2V

/3

LCD

−V

LCD

(b) Resultant waveforms

at LCD segment.

013aaa209

V_state1(t) = V_Sn(t) − V_BP0(t).

V_on(RMS)= 0.745V_LCD

V_state2(t) = V_Sn(t) − V_BP1(t).

V_off(RMS)= 0.333V_LCD

.

Fig 6. Waveforms for the 1:2 multiplex drive mode with ¹⁄₃bias

PCF85134_1

Product data sheet

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PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.4.3 1:3 Multiplex drive mode

When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as

shown in Figure 7.

T

fr

V

LCD

LCD segments

2V

/3

LCD

BP0

BP1

BP2

Sn

V

/3

LCD

SS

state 1

state 2

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+1

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+2

V

/3

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

/3

LCD

V

LCD

/3

state 1

0 V

−V

/3

LCD

−2V

/3

LCD

−V

LCD

V

LCD

2V

/3

LCD

V

LCD

/3

state 2

0 V

−V

/3

LCD

−2V

/3

LCD

−V

LCD

(b) Resultant waveforms

at LCD segment.

013aaa210

V_state1(t) = V_Sn(t) − V_BP0(t).

V_on(RMS)= 0.638V_LCD

V_state2(t) = V_Sn(t) − V_BP1(t).

V_off(RMS)= 0.333V_LCD

.

Fig 7. Waveforms for the 1:3 multiplex drive mode with ¹⁄₃bias

PCF85134_1

Product data sheet

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PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.4.4 1:4 Multiplex drive mode

When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as

shown in Figure 8.

T

fr

V

LCD segments

LCD

2V

/3

LCD

BP0

BP1

BP2

V

/3

LCD

SS

state 1

state 2

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

BP3

Sn

V

/3

LCD

SS

V

LCD

2V

/3

LCD

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+1

V

/3

LCD

SS

V

LCD

2V

/3

LCD

Sn+2

Sn+3

V

/3

LCD

SS

V

LCD

2V

/3

LCD

V

/3

LCD

SS

(a) Waveforms at driver.

V

LCD

2V

/3

LCD

V /3

LCD

state 1

0 V

−V

/3

LCD

−2V

/3

LCD

−V

LCD

V

LCD

2V

/3

LCD

V /3

LCD

0 V

−V

state 2

/3

LCD

−2V

/3

LCD

−V

LCD

(b) Resultant waveforms

at LCD segment.

013aaa211

V_state1(t) = V_Sn(t) − V_BP0(t).

V_on(RMS)= 0.577V_LCD

V_state2(t) = V_Sn(t) − V_BP1(t).

V_off(RMS)= 0.333V_LCD

.

Fig 8. Waveforms for the 1:4 multiplex drive mode with ¹⁄₃bias

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Product data sheet

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PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.5 Oscillator

The internal logic and the LCD drive signals of the PCF85134 are timed by the frequency

f_clk, which equals either the built-in oscillator frequency f_oscor the external clock frequency

f_clk(ext). The clock frequency f_clkdetermines the LCD frame frequency (f_fr).

7.5.1 Internal clock

The internal oscillator is enabled by connecting pin OSC to pin V_SS. In this case, the

output from pin CLK is the clock signal for any cascaded PCF85134 in the system.

7.5.2 External clock

Connecting pin OSC to V_DDenables an external clock source. Pin CLK becomes the

external clock input.

A clock signal must always be supplied to the device; removing the clock may freeze the

LCD in a DC state, which is not suitable for the liquid crystal.

7.6 Timing and frame frequency

The timing of the PCF85134 organizes the internal data ﬂow of the device. This includes

the transfer of display data from the display RAM to the display segment outputs. In

cascaded applications, the synchronization signal (SYNC) maintains the correct timing

relationship between all the PCF85134 in the system. The timing also generates the LCD

frame frequency which is derived as an integer division of the clock frequency

(see Table 6). The frame frequency is a ﬁxed division of the internal clock or of the

frequency applied to pad CLK when an external clock is used.

Table 6.

LCD frame frequencies

Frame frequency

Nominal frame frequency (Hz)

82

f _clk

f _fr

=

---------

24

7.7 Display register

The display register holds the display data while the corresponding multiplex signals are

generated. There is a one-to-one relationship between the data in the display register, the

LCD segment outputs, and one column of the display RAM.

7.8 Segment outputs

The LCD drive section includes 60 segment outputs (S0 to S59) which must be connected

directly to the LCD. The segment output signals are generated based on the multiplexed

backplane signals and with data resident in the display register. When less than

60 segment outputs are required the unused segment outputs must be left open-circuit.

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PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

7.9 Backplane outputs

The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane

output signals are generated based on the selected LCD drive mode.

• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.

If less than four backplane outputs are required the unused outputs can be left

open-circuit.

• In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

• In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same

signals and can also be paired to increase the drive capabilities.

• In static drive mode: The same signal is carried by all four backplane outputs; and

they can be connected in parallel for very high drive requirements.

7.10 Display RAM

The display RAM is a static 60 × 4 bit RAM which stores LCD data. A logic 1 in the RAM

bit map indicates the on-state of the corresponding LCD element; similarly, a logic 0

indicates the off-state. There is a one-to-one correspondence between the RAM

addresses and the segment outputs and between the individual bits of a RAM word and

the backplane outputs. The display RAM bit map, Figure 9, shows rows 0 to 3 which

correspond with the backplane outputs BP0 to BP3, and columns 0 to 59 which

correspond with the segment outputs S0 to S59. In multiplexed LCD applications the

segment data of the ﬁrst, second, third, and fourth row of the display RAM are

time-multiplexed with BP0, BP1, BP2, and BP3 respectively.

columns

display RAM addresses/segment outputs (S)

0

1

2

3

4

55 56 57 58 59

rows

0

1

2

3

display RAM rows/

backplane outputs

(BP)

013aaa212

The display RAM bit map shows the direct relationship between the display RAM addresses and

the segment outputs and between the bits in a RAM word and the backplane outputs.

Fig 9. Display RAM bit map

When display data is transmitted to the PCF85134, the received display bytes are stored

in the display RAM in accordance with the selected LCD drive mode. The data is stored as

it arrives and does not wait for the acknowledge cycle as with the commands. Depending

on the current multiplex drive mode, data is stored singularly, in pairs, triples, or

quadruples. To illustrate the ﬁlling order, an example of a 7-segment display showing all

drive modes is given in Figure 10; the RAM ﬁlling organization depicted applies equally to

other LCD types.

PCF85134_1

Product data sheet

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PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

The following applies to Figure 10:

• In static drive mode the eight transmitted data bits are placed into row 0 of eight

successive 4-bit RAM words.

• In 1:2 multiplex mode the eight transmitted data bits are placed in pairs into

row 0 and 1 of four successive 4-bit RAM words.

• In 1:3 multiplex mode the eight bits are placed in triples into row 0, 1, and 2 of three

successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is not

recommended to use this bit in a display because of the difﬁcult addressing. This last

bit may, if necessary, be controlled by an additional transfer to this address, but care

should be taken to avoid overwriting adjacent data because always full bytes are

transmitted.

• In the 1:4 multiplex mode the eight transmitted data bits are placed in quadruples into

row 0, 1, 2, and 3 of two successive 4-bit RAM words.

7.11 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte, or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load-data-pointer command (see Table 9). Following this command, an

arriving data byte is stored at the display RAM address indicated by the data pointer. The

ﬁlling order is shown in Figure 10. After each byte is stored, the content of the data pointer

is automatically incremented by a value dependent on the selected LCD drive mode:

• In static drive mode by eight.

• In 1:2 multiplex drive mode by four.

• In 1:3 multiplex drive mode by three.

• In 1:4 multiplex drive mode by two.

If an I²C-bus data access terminates early, the state of the data pointer is unknown.

Consequently, the data pointer must be rewritten prior to further RAM accesses.

7.12 Subaddress counter

The storage of display data is conditioned by the content of the subaddress counter.

Storage is allowed only when the content of the subaddress counter match with the

hardware subaddress applied to A0, A1 and A2. The subaddress counter value is deﬁned

by the device-select command (see Table 12). If the content of the subaddress counter

and the hardware subaddress do not match, then data storage is inhibited but the data

pointer is incremented as if data storage had taken place. The subaddress counter is also

incremented when the data pointer overﬂows.

In cascaded applications each PCF85134 in the cascade must be addressed separately.

Initially, the ﬁrst PCF85134 is selected by sending the device-select command matching

the ﬁrst device's hardware subaddress. Then the data pointer is set to the preferred

display RAM address by sending the load-data-pointer command.

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Once the display RAM of the ﬁrst PCF85134 has been written, the second PCF85134 is

selected by sending the device-select command again. This time however the command

matches the second device's hardware subaddress. Next the load-data-pointer command

is sent to select the preferred display RAM address of the second PCF85134.

This last step is very important because during writing data to the ﬁrst PCF85134, the

data pointer of the second PCF85134 is incremented. In addition, the hardware

subaddress should not be changed whilst the device is being accessed on the I²C-bus

interface.

7.13 Output bank selector

The output bank selector (see Table 13) selects one of the four rows per display RAM

address for transfer to the display register. The actual row selected depends on the

particular LCD drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by

the contents of row 1, 2, and then 3

• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially

• In 1:2 multiplex mode, rows 0 and 1 are selected

• In static mode, row 0 is selected

The SYNC signal resets these sequences to the following starting points: bit 3 for

1:4 multiplex, bit 2 for 1:3 multiplex, bit 1 for 1:2 multiplex, and bit 0 for static mode.

The PCF85134 includes a RAM bank switching feature in the static and 1:2 multiplex drive

modes. In the static drive mode, the bank-select command may request the contents of

row 2 to be selected for display instead of the contents of row 0. In the 1:2 mode, the

contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the

provision for preparing display information in an alternative bank and to be able to switch

to it, once it is assembled.

7.14 Input bank selector

The input bank selector loads display data into the display RAM in accordance with the

selected LCD drive conﬁguration. Display data can be loaded in row 2 in static drive mode

or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command. The

input bank selector functions independently to the output bank selector.

7.15 Blinker

The display blink capabilities of the PCF85134 are very versatile. The whole display can

blink at frequencies selected by the blink-select command (see Table 14). The blink

frequencies are fractions of the clock frequency. The ratios between the clock and blink

frequencies depend on the blink mode selected (see Table 7).

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PCF85134

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Universal LCD driver for low multiplex rates

Table 7.

Blink frequencies

Blink mode Operating mode ratio Blink frequency with respect to f_clk(typical)

Unit

f_clk= 1.970 kHz

blinking off

2.5

off

1

-

Hz

f _clk

---------

768

2

3

1.3

0.6

Hz

f _clk

-----------

1536

f _clk

-----------

3072

An additional feature is for an arbitrary selection of LCD segments to blink. This applies to

the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. By means of the output bank selector, the displayed RAM

banks are exchanged with alternate RAM banks at the blink frequency. This mode can

also be speciﬁed by the blink-select command.

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD segments can blink by selectively changing the display RAM data at ﬁxed time

intervals.

The entire display can blink at a frequency other then the nominal blink frequency. This

can be effectively performed by resetting and setting the display enable bit E at the

required rate using the mode-set command (see Table 10).

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8. Basic architecture

8.1 Characteristics of the I²C-bus

The I²C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

8.1.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal. Bit transfer is illustrated in Figure 11.

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 11. Bit transfer

8.1.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW change of the data line, while the clock is HIGH, is deﬁned as the START

condition (S).

A LOW-to-HIGH change of the data line, while the clock is HIGH, is deﬁned as the STOP

condition (P).

The START and STOP conditions are illustrated in Figure 12.

SDA

SCL

SDA

SCL

S

P

START condition

STOP condition

mbc622

Fig 12. Deﬁnition of START and STOP conditions

8.1.2 System conﬁguration

A device generating a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message is the master; and the devices which are

controlled by the master are the slaves. The system conﬁguration is shown in Figure 13.

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MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

SDA

SCL

mga807

Fig 13. System conﬁguration

8.1.3 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

• A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte.

• A master receiver must generate an acknowledge after the reception of each byte that

has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I²C-bus is illustrated in Figure 14.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from

master

1

2

8

9

S

clock pulse for

acknowledgement

START

condition

mbc602

Fig 14. Acknowledgement of the I²C-bus

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8.1.4 I²C-bus controller

The PCF85134 acts as an I²C-bus slave receiver. It does not initiate I²C-bus transfers or

transmit data to an I²C-bus master receiver. The only data output from the PCF85134 are

the acknowledge signals of the selected devices. Device selection depends on the

I²C-bus slave address, the transferred command data and the hardware subaddress.

In single device applications, the hardware subaddress inputs A0, A1, and A2 are

normally tied to V_SSwhich deﬁnes the hardware subaddress 0. In multiple device

applications A0, A1, and A2 are tied to V_SSor V_DDusing a binary coding scheme, so that

no two devices with a common I²C-bus slave address have the same hardware

subaddress.

8.1.5 Input ﬁlters

To enhance noise immunity in electrically adverse environments, RC low-pass ﬁlters are

provided on the SDA and SCL lines.

8.2 I²C-bus protocol

Two I²C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF85134.

The least signiﬁcant bit of the slave address is bit R/W. The PCF85134 is a write-only

device. It will not respond to a read access, so this bit should always be logic 0. The

second bit of the slave address is deﬁned by the level tied at input SA0. Two displays

controlled by PCF85134 can be recognized on the same I²C-bus which allows:

• Up to 16 PCF85134s on the same I²C-bus for very large LCD applications

• The use of two types of LCD multiplex drive mode on the same I²C-bus

The I²C-bus protocol is shown in Figure 15. The sequence is initiated with a START

condition (S) from the I²C-bus master which is followed by one of the available PCF85134

slave addresses. All PCF85134s with the same SA0 level acknowledge in parallel to the

slave address. All PCF85134s with the alternative SA0 level ignore the whole I²C-bus

transfer.

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Universal LCD driver for low multiplex rates

R/W = 0

slave address

control byte

RAM/command byte

S

A

0

M

S

B

L

S

B

C

O

R

S

0

1

0

A

P

A

EXAMPLES

a) transmit two bytes of RAM data

S

0

1

0

A

0

A

0

1

0

RAM DATA

COMMAND

RAM DATA

A

P

A

b) transmit two command bytes

S

0

1

0

A

0

A

0

1

COMMAND

RAM DATA

A

P

c) transmit one command byte and two RAM date bytes

S

0

1

0

A

0

A

1

0

RAM DATA

A

P

mgl752

Fig 15. I²C-bus protocol

After acknowledgement, the control byte is sent deﬁning if the next byte is a RAM or

command information. The control byte also deﬁnes if the next byte is a control byte or

further RAM or command data (see Figure 16 and Table 8). In this way it is possible to

conﬁgure the device and then ﬁll the display RAM with little overhead.

MSB

LSB

7

6

5

4

3

2

1

0

CO RS

not relevant

mgl753

Fig 16. Control byte format

Table 8.

Control byte description

Bit

Symbol Value

Description

continue bit

last control byte

7

CO

0

1

control bytes continue

register selection

command register

data register

6

RS

0

1

5 to 0

-

not relevant

The command bytes and control bytes are also acknowledged by all addressed

PCF85134s connected to the bus.

The display bytes are stored in the display RAM at the address speciﬁed by the data

pointer and the subaddress counter. Both data pointer and subaddress counter are

automatically updated.

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The acknowledgement after each byte is made only by the (A0, A1, and A2) addressed

PCF85134. After the last display byte, the I²C-bus master issues a STOP condition (P).

Alternatively a START may be issued to RESTART I²C-bus access.

8.3 Command decoder

The command decoder identiﬁes command bytes that arrive on the I²C-bus. There are

ﬁve commands:

Table 9.

Deﬁnition of commands

Operation code

Command

Bit

Reference

7

1

0

1

6

5

4

3

2

1

0

Mode-set

1

0

E

B

M[1:0]

Table 10

Table 11

Table 12

Table 13

Table 14

Load-data-pointer

Device-select

Bank-select

Blink-select

P[6:0]

1

0

1

0

1

0

A[2:0]

0

I

O

A

BF[1:0]

Table 10. Mode-set command bit description

Bit

7 to 4

3

Symbol Value

Description

ﬁxed value

-

1100

E

display status

0

1

disabled (blank)^[1]

enable

2

B

LCD bias conﬁguration

¹⁄₃bias

¹⁄₂bias

0

1

1 to 0

M[1:0]

LCD drive mode selection

static; 1 backplane

01

10

11

00

1:2 multiplex; 2 backplanes

1:3 multiplex; 3 backplanes

1:4 multiplex; 4 backplanes

[1] The possibility to disable the display allows implementation of blinking under external control.

Table 11. Load-data-pointer command bit description

See Section 7.11.

Bit

7

Symbol Value

Description

-

0

ﬁxed value

6 to 0

P[6:0]

0000000 to 7-bit binary value of 0 to 59

0111011

Table 12. Device-select command bit description

See Section 7.12.

Bit

Symbol Value

Description

7 to 3

2 to 0

-

11100

ﬁxed value

A[2:0]

000 to 111 3-bit binary value of 0 to 7

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Table 13. Bank-select command bit description

See Section 7.10, Section 7.11, Section 7.12, Section 7.13 and Section 7.14.

Bit

Symbol

Value

Description

Static

1:2 multiplex^[1]

7 to 2

1

-

I

111110

ﬁxed value

input bank selection: storage of arriving display data

0

1

RAM row 0

RAM row 2

RAM rows 0 and 1

RAM rows 2 and 3

0

O

output bank selection: retrieval of LCD display data

0

1

RAM row 0

RAM row 2

RAM rows 0 and 1

RAM rows 2 and 3

[1] The bank-select command has no effect in 1:3 or 1:4 multiplex drive modes.

Table 14. Blink-select command bit description

See Section 7.15.

Bit

7 to 3

2

Symbol Value

Description

-

11110

ﬁxed value

A

blink mode selection

0

1

normal blinking^[1]

blinking by alternating display RAM banks

1 to 0

BF[1:0]

blink frequency selection

00

01

10

11

off

1

2

3

[1] Normal blinking can only be selected in multiplex drive mode 1:3 or 1:4.

[2] For the blink frequencies, see Table 7.

8.4 Display controller

The display controller executes the commands identiﬁed by the command decoder. It

contains the status registers of the PCF85134 and coordinates their effects. The controller

also loads display data into the display RAM as required by the storage order.

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Universal LCD driver for low multiplex rates

9. Internal circuitry

V

DD

SA0

CLK

V

SS

DD

SS

SCL

V

SS

DD

V

SS

OSC

V

SS

DD

SDA

SYNC

V

SS

DD

A0, A1, A2

V

LCD

V

SS

LCD

V

SS

BP0, BP1,

BP2, BP3

V

SS

LCD

S0 to S59

V

001aah615

SS

Fig 17. Device protection diagram

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Universal LCD driver for low multiplex rates

10. Limiting values

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(V_LCD) is on while the IC supply voltage (V_DD) is off, or vice versa. This may cause unwanted

display artifacts. To avoid such artifacts, V_LCDand V_DDmust be applied or removed together.

Table 15. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol Parameter

Conditions

Min

−0.5

−50

−0.5

−50

−0.5

−10

−0.5

−10

-

Max

+6.5

+50

Unit

V

V_DD

I_DD

supply voltage

supply current

mA

V

V_LCD

I_DD(LCD)

I_SS

LCD supply voltage

LCD supply current

ground supply current

input voltage

+7.5

+50

mA

V

+50

[2]

V_I

+6.5

+10

I_I

input current

mA

V

[2]

V_O

output voltage

+6.5

+7.5

+10

[3]

V

[2][3]

I_O

output current

mA

mW

V

P_tot

total power dissipation

power dissipation per output

electrostatic discharge voltage

400

P/out

V_ESD

-

100

[4]

[5]

[6]

[7]

HBM

MM

-

±2500

±200

200

-

V

I_lu

latch-up current

-

mA

°C

T_stg

storage temperature

−65

+150

[1] Stresses above these values listed may cause permanent damage to the device.

[2] Pins SDA, SCL, CLK, SYNC, SA0, OSC and A0 to A2.

[3] Pins S0 to S59 and BP0 to BP3.

[4] HBM: Human Body Model, according to Ref. 5 “JESD22-A114”.

[5] MM: Machine Model, according to Ref. 6 “JESD22-A115”.

[6] Pass level; latch-up testing according to Ref. 7 “JESD78” at maximum ambient temperature

(T_amb(max)= +85 °C).

[7] According to the NXP store and transport requirements (see Ref. 9 “NX3-00092”) the devices have to be

stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products

deviant conditions are described in that document.

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Universal LCD driver for low multiplex rates

11. Static characteristics

Table 16. Static characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 6.5 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Supplies

Conditions

Min

Typ

Max

Unit

V_DD

V_LCD

I_DD

supply voltage

1.8

2.5

-

5.5

6.5

20

V

LCD supply voltage

supply current

-

V

[1]

f_clk(ext)= 1536 Hz

8

24

µA

I_DD(LCD)LCD supply current

-

60

Logic

V_I

input voltage

V_SS− 0.5 -

V_DD+ 0.5 V

V_IL

LOW-level input voltage on pins CLK, SYNC, OSC, A0 to A2 and SA0

HIGH-level input voltage on pins CLK, SYNC, OSC, A0 to A2 and SA0

power-on reset voltage

V_SS

0.7V_DD

1.0

1

-

0.3V_DD

V_DD

1.6

V

V_IH

V_POR

I_OL

-

V

1.3

-

V

LOW-level output current output sink current; V_OL= 0.4 V;

-

mA

V

_DD= 5 V; on pins CLK and SYNC

output source current; V_OH= 4.6 V;

_DD= 5 V; on pin CLK

I_OH

I_L

HIGH-level output

current

1

-

mA

V

leakage current

V_I= V_DDor V_SS; on pins SA0, A0 to A2 and

CLK

−1

+1

µA

V_I= V_DD; on pin OSC

−1

-

+1

7

µA

[2]

C_I

input capacitance

-

pF

I²C-bus; pins SDA and SCL

V_I

input voltage

V_SS− 0.5 -

5.5

V

V_IL

LOW-level input voltage pin SCL

pin SDA

V_SS

0.7V_DD

3

-

0.3V_DD

0.2V_DD

5.5

V

V_IH

I_OL

HIGH-level input voltage

V

LOW-level output current output sink current; V_OL= 0.4 V; V_DD= 5 V;

on pin SDA

-

mA

I_L

leakage current

V_I= V_DDor V_SS

−1

-

+1

7

µA

[2]

C_i

input capacitance

-

pF

LCD outputs

Output pins BP0 to BP3

[3]

[4]

V_BP

R_BP

voltage on pin BP

C_bpl= 35 nF

V_LCD= 5 V

−100

-

+100

10

mV

resistance on pin BP

-

1.5

kΩ

Output pins S0 to S59

[5]

[4]

V_S

R_S

voltage on pin S

C_sgm= 35 nF

V_LCD= 5 V

−100

-

+100

13.5

mV

resistance on pin S

-

6.0

kΩ

[1] LCD outputs are open-circuit; inputs at V_SSor V_DD; external clock with 50 % duty factor; I²C-bus inactive.

[2] Not tested, design speciﬁcation only.

[3] C_bpl= backplane capacitance.

[4] Measured on sample basis only.

[5] C_sgm= segment capacitance.

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Universal LCD driver for low multiplex rates

12. Dynamic characteristics

Table 17. Dynamic characteristics

V_DD= 1.8 V to 5.5 V; V_SS= 0 V; V_LCD= 2.5 V to 6.5 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Clock

Parameter

Conditions

Min

Typ

Max

Unit

Internal: output pin CLK

[1]

f_osc

oscillator frequency

V_DD= 5 V

1440

1970

2640

Hz

External: input pin CLK

f_clk(ext)

t_clk(H)

t_clk(L)

external clock frequency

800

130

-

3600

Hz

µs

HIGH-level clock time

LOW-level clock time

-

Synchronization: input pin SYNC

t_{PD(SYNC_N)}SYNC propagation delay

-

30

-

ns

t_{SYNC_NL}

Outputs: pins BP0 to BP3 and S0 to S59

t_PD(drv)driver propagation delay

SYNC LOW time

1

µs

V_LCD= 5 V

-

30

µs

I²C-bus: timing^[2]

Pin SCL

f_SCL

SCL frequency

-

400

kHz

µs

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

1.3

0.6

-

t_HIGH

µs

Pin SDA

t_SU;DAT

t_HD;DAT

data set-up time

data hold time

100

0

-

ns

Pins SCL and SDA

t_BUF

bus free time between a STOP and

1.3

-

µs

START condition

t_SU;STO

t_HD;STA

t_SU;STA

set-up time for STOP condition

hold time (repeated) START condition

0.6

-

µs

set-up time for a repeated START

condition

t_r

rise time of both SDA and SCL signals

fall time of both SDA and SCL signals

capacitive load for each bus line

spike pulse width

-

0.3

400

50

µs

pF

ns

t_f

C_b

t_w(spike)

[1] Typical output (duty cycle δ = 50 %).

[2] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V_ILand V_IHwith an

input voltage swing of V_SSto V_DD

.

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PCF85134

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Universal LCD driver for low multiplex rates

1 / f

clk

t

clk(L)

clk(H)

0.7V

DD

CLK

0.3V

DD

0.7V

DD

SYNC

0.3V

t

PD(SYNC_N)

t

SYNC_NL

0.5 V

(V

BP0 to BP3,

and S0 to S59

= 5 V)

DD

0.5 V

t

PD(drv)

001aah618

Fig 18. Driver timing waveforms

SDA

t

f

BUF

LOW

SCL

SDA

t

HD;STA

t

SU;DAT

r

HD;DAT

t

HIGH

t

SU;STA

t

SU;STO

mga728

Fig 19. I²C-bus timing waveforms

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Universal LCD driver for low multiplex rates

13. Application information

13.1 Cascaded operation

Large display conﬁgurations of up to 16 PCF85134 can be recognized on the same

I²C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable

I²C-bus slave address (SA0).

Table 18. Addressing cascaded PCF85134

Cluster

Bit SA0

Pin A2

Pin A1

Pin A0

Device

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

2

1

8

9

10

11

12

13

14

15

When cascaded PCF85134 are synchronized, they can share the backplane signals from

one of the devices in the cascade. Such an arrangement is cost-effective in large LCD

applications since the backplane outputs of only one device need to be through-plated to

the backplane electrodes of the display. The other PCF85134 of the cascade contribute

additional segment outputs, but their backplane outputs are left open-circuit

(see Figure 20).

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PCF85134

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Universal LCD driver for low multiplex rates

V

LCD

DD

SDA

SCL

60 segment drives

PCF85134

SYNC

CLK

BP0 to BP3

OSC

(open-circuit)

A0 A1 A2 SA0 V

SS

LCD PANEL

V

LCD

V

t

r

DD

≤

R

2C

V

LCD

b

DD

60 segment drives

SDA

SCL

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

SYNC

CLK

4 backplanes

BP0 to BP3

PCF85134

OSC

A0 A1 A2 SA0

V

SS

V

SS

013aaa213

Fig 20. Cascaded PCF85134 conﬁguration

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCF85134. Synchronization is guaranteed after a power-on reset. The only time that

SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in

adverse electrical environments or by deﬁning a multiplex drive mode when PCF85134

with different SA0 levels are cascaded).

SYNC is organized as an input/output pin. The output selection is realized as an

open-drain driver with an internal pull-up resistor. A PCF85134 asserts the SYNC line at

the onset of its last active backplane signal and monitors the SYNC line at all other times.

If synchronization in the cascade is lost, it is restored by the ﬁrst PCF85134 to assert

SYNC. The timing relationship between the backplane waveforms and the SYNC signal

for the various drive modes of the PCF85134 are shown in Figure 21.

PCF85134_1

Product data sheet

Rev. 01 — 17 December 2009

32 of 40

PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

1

T

=

fr

f

fr

BP0

SYNC

(a) static drive mode.

BP0

(1/2 bias)

BP0

(1/3 bias)

SYNC

(b) 1:2 multiplex drive mode.

BP0

(1/3 bias)

SYNC

(c) 1:3 multiplex drive mode.

BP0

(1/3 bias)

SYNC

(d) 1:4 multiplex drive mode.

mgl755

Fig 21. Synchronization of the cascade for various PCF85134 drive modes

The contact resistance between the SYNC pins of cascaded devices must be controlled. If

the resistance is too high, the device will not be able to synchronize properly.

Table 19 shows the maximum contact resistance values.

Table 19. SYNC contact resistance

Number of devices

Maximum contact resistance

2

6000 Ω

2200 Ω

1200 Ω

700 Ω

3 to 5

6 to 10

11 to 16

PCF85134_1

Product data sheet

Rev. 01 — 17 December 2009

33 of 40

PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

14. Package outline

LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm

SOT315-1

y

X

A

60

41

Z

61

40

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

L

pin 1 index

80

21

detail X

1

20

Z

D

v

M

A

e

w M

b

p

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

v

w

y

Z

θ

1

2

3

p

D

E

p

D

E

max.

7^o

0^o

0.16 1.5

0.04 1.3

0.27 0.18 12.1 12.1

0.13 0.12 11.9 11.9

14.15 14.15

13.85 13.85

0.75

0.30

1.45 1.45

1.05 1.05

mm

1.6

0.25

0.5

1

0.2 0.15 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT315-1

136E15

MS-026

Fig 22. Package outline SOT315-1 (LQFP80)

PCF85134_1

Product data sheet

Rev. 01 — 17 December 2009

34 of 40

PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

15. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC61340-5 or equivalent

standards.

16. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

PCF85134_1

Product data sheet

Rev. 01 — 17 December 2009

35 of 40

PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

16.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

16.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 23) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 20 and 21

Table 20. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 21. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 23.

PCF85134_1

Product data sheet

Rev. 01 — 17 December 2009

36 of 40

PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 23. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

17. Abbreviations

Table 22. Abbreviations

Acronym

CMOS

ESD

Description

Complementary Metal-Oxide Semiconductor

ElectroStatic Discharge

Human Body Model

HBM

IC

Integrated Circuit

LCD

Liquid Crystal Display

MM

Machine Model

RAM

Random Access Memory

PCF85134_1

Product data sheet

Rev. 01 — 17 December 2009

37 of 40

PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

18. References

[1] AN10365 — Surface mount reﬂow soldering description

[2] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[4] IPC/JEDEC J-STD-020D — Moisture/Reﬂow Sensitivity Classiﬁcation for

Nonhermetic Solid State Surface Mount Devices

[5] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[6] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model

(MM)

[7] JESD78 — IC Latch-Up Test

[8] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[9] NX3-00092 — NXP store and transport requirements

[10] SNV-FA-01-02 — Marking Formats Integrated Circuits

[11] UM10204 — I²C-bus speciﬁcation and user manual

19. Revision history

Table 23. Revision history

Document ID

Release date

20091217

Data sheet status

Change notice

Supersedes

PCF85134_1

Product data sheet

-

PCF85134_1

Product data sheet

Rev. 01 — 17 December 2009

38 of 40

PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

20. Legal information

20.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

20.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

20.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

20.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

PCF85134_1

Product data sheet

Rev. 01 — 17 December 2009

39 of 40

PCF85134

NXP Semiconductors

Universal LCD driver for low multiplex rates

22. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

13.1

14

Cascaded operation. . . . . . . . . . . . . . . . . . . . 31

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 34

Handling information . . . . . . . . . . . . . . . . . . . 35

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

15

16

Soldering of SMD packages . . . . . . . . . . . . . . 35

Introduction to soldering. . . . . . . . . . . . . . . . . 35

Wave and reﬂow soldering . . . . . . . . . . . . . . . 35

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 36

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 36

16.1

16.2

16.3

16.4

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

17

18

19

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 37

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Revision history . . . . . . . . . . . . . . . . . . . . . . . 38

7

7.1

7.2

7.3

Functional description . . . . . . . . . . . . . . . . . . . 6

Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 6

LCD bias generator. . . . . . . . . . . . . . . . . . . . . . 7

LCD voltage selector . . . . . . . . . . . . . . . . . . . . 7

LCD drive mode waveforms . . . . . . . . . . . . . . . 9

Static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9

1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 10

1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 12

1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 13

Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 14

External clock . . . . . . . . . . . . . . . . . . . . . . . . . 14

Timing and frame frequency. . . . . . . . . . . . . . 14

Display register. . . . . . . . . . . . . . . . . . . . . . . . 14

Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14

Backplane outputs . . . . . . . . . . . . . . . . . . . . . 15

Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 15

Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Subaddress counter . . . . . . . . . . . . . . . . . . . . 17

Output bank selector. . . . . . . . . . . . . . . . . . . . 18

Input bank selector . . . . . . . . . . . . . . . . . . . . . 18

Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

20

Legal information . . . . . . . . . . . . . . . . . . . . . . 39

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 39

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.4

20.1

20.2

20.3

20.4

7.4.1

7.4.2

7.4.3

7.4.4

7.5

7.5.1

7.5.2

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.13

7.14

7.15

21

22

Contact information . . . . . . . . . . . . . . . . . . . . 39

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8

8.1

Basic architecture . . . . . . . . . . . . . . . . . . . . . . 20

Characteristics of the I²C-bus. . . . . . . . . . . . . 20

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

START and STOP conditions . . . . . . . . . . . . . 20

System conﬁguration . . . . . . . . . . . . . . . . . . . 20

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 21

I²C-bus controller . . . . . . . . . . . . . . . . . . . . . . 22

Input ﬁlters . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

I²C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 22

Command decoder . . . . . . . . . . . . . . . . . . . . . 24

Display controller . . . . . . . . . . . . . . . . . . . . . . 25

8.1.1

8.1.1.1

8.1.2

8.1.3

8.1.4

8.1.5

8.2

8.3

8.4

9

Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 26

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27

Static characteristics. . . . . . . . . . . . . . . . . . . . 28

Dynamic characteristics . . . . . . . . . . . . . . . . . 29

Application information. . . . . . . . . . . . . . . . . . 31

10

11

12

13

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 17 December 2009

Document identifier: PCF85134_1


型号：	PCF85134HL-1
厂家：	NXP
描述：	Universal LCD driver for low multiplex rates 低复用率的通用LCD驱动器驱动器 CD
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