PCD50912H-T [NXP]
暂无描述;型号: | PCD50912H-T |
厂家: | NXP |
描述: | 暂无描述 控制器 |
文件: | 总16页 (文件大小:93K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
PCD509x2/zuu/v family
Low cost; low power DECT
baseband controllers (ABC-PRO)
1998 Apr 27
Objective specification
File under Integrated Circuits, IC17
Philips Semiconductors
Objective specification
Low cost; low power DECT baseband
controllers (ABC-PRO)
PCD509x2/zuu/v family
CONTENTS
1
2
3
4
5
FEATURES
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING INFORMATION
5.1
5.2
Pinning
Pin description
6
FUNCTIONAL DESCRIPTION
DECT baseband controller system
PACKAGE OUTLINES
6.1
7
8
SOLDERING
8.1
8.2
8.3
8.4
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
9
DEFINITIONS
10
11
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
1998 Apr 27
2
Philips Semiconductors
Objective specification
Low cost; low power DECT baseband
controllers (ABC-PRO)
PCD509x2/zuu/v family
1
FEATURES
• The PCD50912 is designed for GAP compatible DECT
handsets
• The PCD50922 is designed for GAP compatible DECT
base stations serving up to six handsets
• Fully static 80C51 microcontroller
• Comparator for use as bit-slicer
• Emulation supported for 80C51 program development
• Four 8-bit ports (P0, P1, P2 and P3), 32 I/O lines
• 3 channel time-multiplexed 8-bit ADC for RSSI, battery
and general input voltage measurement
• Dedicated port pins for keyboard, I2C-bus, interrupt
sources and/or external memory
• Battery management supported by programmable
current source for temperature or charge current
measurement
• Fifteen interrupt sources (including those from TICB,
BML and DSP) with two priority levels
• I2C-bus interface
• On-chip 8-bit DAC for various purposes
• Low power crystal oscillator at 13.824 MHz
• UART with IrDA-compatible Data Transmission Mode
• 256 bytes of microcontroller main RAM
• 3 kbytes of microcontroller AUX RAM
• 1 kbyte of shared System Data RAM
• 64 kbytes of mask programmable ROM
• Programmable on-chip capacitors for frequency
adjustment to 13.824 MHz with large pulling range
• High performance DAC and ADC for dynamic earpiece
and dynamic or electret microphone
• Analog-to-digital path switchable sensitivity for
microphone or line interface input
• 128 kbyte address space for external ROM access,
maximum 192 kbytes together with internal ROM
• On-chip reference voltage and supply for electret
microphone
• 128 kbytes of external RAM addressable
• Embedded DSP with 6.912, 13.824 or 27.648 Mips
• Speech and IOM-2 interface
• Very low ohmic buzzer output
• Pulse density modulated or pulse width modulated
buzzer output signal
• BML for TDMA frame (de)multiplexing. Transmission or
reception can be programmed for any slot
• Power-on-reset
• Low power operation optimized for 2 battery cells in
handset
• Ciphering, scrambling, CRC checking/generation,
protected B-fields
• Long standby time due to reduced digital supply voltage
and reduced activity in idle-locked mode
• Local call and B-field loop-back
• Automatic receiver delay adjustment programmable per
slot to correct for terminal mobility
• Flexible supply voltage concept due to use of level
shifters between each supply voltage domain
• Phase error measurement and phase error correction by
hardware
• Eight independent supply voltage domains:
– 1.8 to 3.6 V for digital core, microcontroller ports P0
and P2, and also P1 and P3
• Serial interface to synthesizer for frequency
programming
– 1.8 to 3.6 V for buzzer, oscillator and battery
– 2.7 to 3.6 V for RF interface and analog circuits
• CMOS technology
• Programmable timing and polarity of radio-control
signals
• Easy interfacing with radio circuits, operating at different
• Small and flat LQFP80 package.
supply voltages
• GMSK pulse shaper with two different pulse shapes
(BT = 0.5 and BT = 0.8)
1998 Apr 27
3
Philips Semiconductors
Objective specification
Low cost; low power DECT baseband
controllers (ABC-PRO)
PCD509x2/zuu/v family
This family specification contains the hardware description
that is independent of the used ROM codes.
2
GENERAL DESCRIPTION
The PCD509x2 family is designed for low power GAP
compatible DECT handset (PP) and base station (FP)
applications. The circuit includes the audio interface, the
DSP, the microcontroller and the Burst Mode Logic, and
contains all functionality to convert speech and data
signals from/to the analog side (microphone and earpiece
or line interface circuit) to/from the radio side
The numerical digit ‘x’ in PCD509x2 determines the
intended application area (e.g. PCD50912 for use in
handsets or PCD50922 for use in simple base stations,
etc.). The last numerical digit ‘2’ is used to denote
hardware derivatives. The extension digits ‘z’ (A to Z) and
‘uu’ (00 to 99) denote the DSP and the microcontroller
software version, respectively. The extension ‘v’ denotes
the hardware version updates of the circuit.
(1.152 Mbits/s data).
This circuit is a member of the ABC family, where A stands
for ‘ADPCM codec’, B for ‘Burst Mode Logic’ and C for
‘microController’. The name ABC-PRO stands for
PROfessional ABC.
Although the microcontroller ROM code is present on-chip,
an external program memory for the microcontroller code
can be used. This is not the case for the DSP ROM code
which is fixed by the chip version.
The PCD509x2/zuu/v contains on-chip ROM for the
embedded DSP code and on-chip ROM for the embedded
microcontroller code. It is these ROM codes that
differentiate between various chip derivatives. For each
DSP code a separate DSP user manual is published.
Please contact Philips Semiconductors for more
information.
Throughout this family specification the term PCD509x2 is
used to cover all sub types and versions. If any specific
feature or parameter is connected to a certain sub type or
version this will be specifically written. Until otherwise
stated this family specification is valid for hardware
version 1 (v = 1).
3
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
PCD50912H
PCD50922H
LQFP80
plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm
SOT315-1
1998 Apr 27
4
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(1)
P1
(1)
P3
P0
P2
ALE
A16
EA
PSEN
8
8
8
8
V
digital pins
analog pins
supply pins
V
DD(P0, P2)
DD(P1, P3)
V
DDD
LEVEL SHIFTER
PORT 0
LEVEL SHIFTER
PORT 2
LEVEL SHIFTER
PORT 1
LEVEL SHIFTER
PORT 3
LEVEL
SHIFTER
V
DDD
PCD509x2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IB BUS
DDD
80CL51 CORE
SPEECH
INTERFACE
IOM ADPCM
(SPI)
SSD
DD(P1, P3)
DD(P0, P2)
SS(P0, P2)
DD(BZ)
SS(BZ)
AUX-RAM
(3 kBYTES)
MICROCONTROLLER-RAM
(256 BYTES)
ROM
(64 kBYTES)
2
I
C-BUS
UART
DD(RF)
SS(RF)
DDA
MICROCONTROLLER
AB-MICROCONTROLLER
INTERFACE (ABCIF)
SSA
DD(OSC)
SS(OSC)
DD(BAT)
V
V
DD(RF)
DDD
V
V
V
DDD
DDD
DD(BZ)
ANT_SW0
ANT_SW1
T_ENABLE
T_PWR
V
DIGITAL
DDD
LEVEL
BUZZER BUFFER
(ABB)
BZP
BZM
PULSE
SHAPER
(DPS)
GPP
SHIFTER
S_ENABLE
S_DATA
S_CLK
DIGITAL
RECEIVE
FILTER
(DRF)
DIGITAL
SIGNAL
S_PWR
BURST
MODE
LOGIC
(BML)
R_ENABLE
R_PWR
PROCESSOR
(DSP)
DIGITAL
NOISE
SHAPER
(DNS)
LEVEL
SHIFTER
EARP
EARM
1-BIT DAC (ARD)
CODEC
Σ ∆
SYSTEM
DATA
SLICE_CTR
REF_CLK
RAM
(SDR)
(1 kBYTE)
LEVEL
SHIFTER
R_DATAP
R_DATAM
DIGITAL
DECIMATING
FILTER
MICP/LIFM
MICM/LIFP
1-BIT ADC
MEMORY
AMP
(DDF)
T_GSMK/
T_DATA
ATS
AGM
V
DDA
ISB
V
V
V
DD(OSC)
DDD
DDA
V
CLOCK
GENERATOR
(CLG)
V
ANALOG SWITCH (ASW)
ref
ref
LEVEL
SHIFTER
DIGITAL
CONTROL
OF
ANALOG
(DCA)
ISB BUS
CONTROLLER
(IBC)
XTAL1
XTAL2
V
ANALOG SUBTRACTOR (ASU)
ANALOG RSSI TREATMENT (ART)
ADJUSTABLE CURRENT SOURCE (ACS)
DD(BAT)
V
ANALOG
DD(BAT)
TIMING
CONTROL
BLOCK
VOLTAGE
SOURCE
(AVS)
LEVEL
SHIFTER
AUXILIARY
ADC
(AAD)
RSSI_AN
ANALOG VOLTAGE
(TICB)
REFERENCE
(AVR)
LEVEL
SHIFTER
RESET
WATCHDOG
TIMER
(WDT)
VANLI
GENERATOR
(RGE)
POWER-ON-RESET
(POR)
MGM858
M_RESET
VBGP
VANLO
(1) Ports 1 and 3 are shared with alternative functions.
Fig.1 Block diagram.
Philips Semiconductors
Objective specification
Low cost; low power DECT baseband
controllers (ABC-PRO)
PCD509x2/zuu/v family
5
PINNING INFORMATION
Pinning
5.1
a
P1.1/INT3
P1.0/INT2
M_RESET
ANT_SW0
ANT_SW1
T_ENABLE
T_PWR
1
2
3
4
5
6
7
8
9
60 P0.2
59 P0.3
58 P0.4
57 P0.5
56 P0.6
55 P0.7
54 ALE
GPP
53
52
51
PSEN
V
S_ENABLE
DD(P0, P2)
S_DATA 10
S_CLK 11
V
SS(P0, P2)
PCD509x2/zuu/v
50 A16
49 P2.7
48 P2.6
47 P2.5
46 P2.4
45 P2.3
44 P2.2
43 P2.1
42 P2.0
S_PWR 12
R_ENABLE 13
R_PWR 14
SLICE_CTR 15
V
DD(RF) 16
V
SS(RF) 17
REF_CLK 18
RSSI_AN 19
V
41
T_GSMK/T_DATA 20
SS(BZ)
MGM857
Fig.2 Pin configuration (LQPF80).
1998 Apr 27
6
Philips Semiconductors
Objective specification
Low cost; low power DECT baseband
controllers (ABC-PRO)
PCD509x2/zuu/v family
5.2
Pin description
Table 1 LQFP80 package
STATE
AFTER
SUPPLY
DOMAIN
SYMBOL
P1.1/INT3
PIN
I/O
DESCRIPTION
RESET(1)
1
2
3
4
5
6
7
8
I/O
I/O
I
HIGH
HIGH
−
VDD(P1,P3) 80C51 port pin/external interrupt 3
VDD(P1,P3) 80C51 port pin/external interrupt 2
P1.0/INT2
M_RESET
ANT_SW0
ANT_SW1
T_ENABLE
T_PWR
VDDD
master reset input (Schmitt trigger)
antenna switch 0
O
O
O
O
O
HIGH
HIGH
HIGH
LOW
LOW
VDD(RF)
VDD(RF)
VDD(RF)
VDD(RF)
VDD(RF)
antenna switch 1
enable transmitter
switch transmitter power
GPP
general purpose pin used for the following:
100 Hz signal related to DECT frame timing
VCO band switch
CLK100
VCO_BND_SW
GP_CLK7
GP_CLK3
GP_CLK05
R_SLICED
on/of
6.912 MHz general purpose clock
3.456 MHz general purpose clock
576 kHz general purpose clock
ABS bitslice comparator output
static high/low.
S_ENABLE
S_DATA
9
O
O
O
O
O
O
O
−
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
−
VDD(RF)
VDD(RF)
VDD(RF)
VDD(RF)
VDD(RF)
VDD(RF)
VDD(RF)
−
synthesizer enable
10
11
12
13
14
15
16
17
18
19
serial synthesizer data
S_CLK
clock for serial synthesizer interface
switch synthesizer power
S_PWR
R_ENABLE
R_PWR
enable receiver
switch receiver power
SLICE_CTR
VDD(RF)
switch slicer time constant
positive supply voltage for RF interface pins
negative supply voltage for RF interface pins
programmable reference clock for synthesizer
analog input for RSSI measurement
transmitter data output, filtered/digital
positive input for receiver data
negative input for receiver data
positive supply for crystal oscillator
VSS(RF)
−
−
−
REF_CLK
RSSI_AN
O
I
running
−
VDD(RF)
VDD(RF)
VDD(RF)
VDD(RF)
VDD(RF)
−
T_GMSK/T_DATA 20
O
I
off
R_DATAP
R_DATAM
VDD(OSC)
XTAL2
21
22
23
24
25
−
I
−
−
−
O
I
running
−
VDD(OSC) crystal oscillator output
VDD(OSC) crystal oscillator input
XTAL1
1998 Apr 27
7
Philips Semiconductors
Objective specification
Low cost; low power DECT baseband
controllers (ABC-PRO)
PCD509x2/zuu/v family
STATE
AFTER
RESET(1)
SUPPLY
DOMAIN
SYMBOL
VSS(OSC)
PIN
26
I/O
DESCRIPTION
−
I
−
−
−
negative supply for crystal oscillator
VDD(BAT)
VANLI
VANLO
VDDA
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
−
positive battery supply voltage
analog input to ADC, current output
analog output from DAC
I/O
O
−
VDDA
VDDA
−
off
−
−
positive supply voltage for analog circuits
negative output to earpiece
EARM
EARP
VSSA
O
off
VDDA
VDDA
−
O
off
positive output to earpiece
−
−
negative supply voltage for analog circuits
VBGP
Vref
O
1.2 V
off
VDD(BAT) bandgap output voltage (+1.2 V)
O
VDDA
VDDA
VDDA
−
reference voltage, microphone supply (+2 V)
MICM/LIFP
MICP/LIFM
VDD(BZ)
BZM
I
off
negative/positive input from microphone/line
positive/negative input from microphone/line
positive supply voltage for buzzer
negative buzzer output
I
off
−
−
O
LOW
LOW
−
VDD(BZ)
VDD(BZ)
−
BZP
O
positive buzzer output
VSS(BZ)
P2.0
−
negative supply voltage for buzzer
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
−
VDD(P0,P2) bidirectional Port 3 pins (80C51)
P2.1
VDD(P0,P2)
P2.2
VDD(P0,P2)
P2.3
VDD(P0,P2)
P2.4
VDD(P0,P2)
P2.5
VDD(P0,P2)
P2.6
VDD(P0,P2)
P2.7
VDD(P0,P2)
A16
VDD(P0,P2) A16 address select
VSS(P0,P2)
VDD(P0,P2)
PSEN
ALE
−
−
−
negative supply voltage
−
−
positive supply voltage for periphery pins
O
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
VDD(P0,P2) program store enable (80C51), active LOW
O
VDD(P0,P2) address latch enable (80C51)
P0.7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD(P0,P2) bidirectional Port 0 pins (80C51)
P0.6
VDD(P0,P2)
VDD(P0,P2)
VDD(P0,P2)
VDD(P0,P2)
VDD(P0,P2)
VDD(P0,P2)
VDD(P0,P2)
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
1998 Apr 27
8
Philips Semiconductors
Objective specification
Low cost; low power DECT baseband
controllers (ABC-PRO)
PCD509x2/zuu/v family
STATE
AFTER
RESET(1)
SUPPLY
DOMAIN
SYMBOL
PIN
63
I/O
DESCRIPTION
EA
I
−
VDD(P0,P2) external access (80C51), active LOW
VDD(P1,P3) 80C51 port pin/Read data, active LOW
VDD(P1,P3) 80C51 port pin/Write data, active LOW
VDD(P1,P3) 80C51 port pin/Timer 1 input
P3.7/RD
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
−
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
−
P3.6/WR
P3.5/T1
P3.4/T0
VDD(P1,P3) 80C51 port pin/Timer 0 input
P3.3/INT1/IrDA
P3.2/INT0
P3.1/TXD
VDD(P1,P3) 80C51 port pin/external interrupt 1/IrDA clock
VDD(P1,P3) 80C51 port pin/external interrupt 0
VDD(P1,P3) 80C51 port pin/UART transmit data
VDD(P1,P3) 80C51 port pin/UART receive data
P3.0/RXD
VSSD
−
−
−
negative supply voltage for digital core
positive supply voltage for digital core
positive supply voltage for periphery pins
VDDD
−
−
VDD(P1,P3)
−
−
P1.7/INT9/SDA
P1.6/INT8/SCL
P1.5/INT7/FS1
P1.4/INT6/DCK
P1.3/INT5/DO
P1.2/INT4/DI
I/O
I/O
I/O
I/O
I/O
I/O
off
VDD(P1,P3) 80C51 port pin/external interrupt 9/I2C-bus data
VDD(P1,P3) 80C51 port pin/external interrupt 8/I2C-bus clock
VDD(P1,P3) 80C51 port pin/external interrupt 7/SPI Frame Sync
VDD(P1,P3) 80C51 port pin/external interrupt 6/SPI Data Clock
VDD(P1,P3) 80C51 port pin/external interrupt 5/SPI Data Out
VDD(P1,P3) 80C51 port pin/external interrupt 4/SPI Data In
off
HIGH
HIGH
HIGH
HIGH
Note
1. In the ‘State After Reset’ column the following symbols are used:
a) HIGH means active HIGH, for BUPxSW pin types this means weak pull-up
b) LOW means active LOW
c) ‘running’ means the clock signal is active
d) ‘off’ means the high-impedance state.
1998 Apr 27
9
Philips Semiconductors
Objective specification
Low cost; low power DECT baseband
controllers (ABC-PRO)
PCD509x2/zuu/v family
Refer to the block diagram in Fig.1. The DECT Controller
consists of a number of functional blocks that operate
more or less autonomously and communicate with each
other via the System Data RAM (SDR). Blocks have
access to SDR via the Internal System Bus (ISB). The ISB
consists of an 8-bit data bus, a 10-bit address bus and a
number of bus-request/bus-grant signals. Access to the
ISB is controlled by ISB Bus Controller (IBC). The IBC
acknowledges bus requests on the basis of a priority
scheme. The embedded 80C51 controller is to be
programmed by the user. It must contain DECT software
from Man-Machine Interface (MMI) to the DECT protocols
TBC, CBC and DBC (refer to “Figures 10 to 13, in
Section 6 of prETS 300 175-3: June 1996”). Software is
available from Philips Semiconductors.
6
FUNCTIONAL DESCRIPTION
6.1
DECT baseband controller system
The PCD509x2 is a family of baseband controllers,
designed for use in Digital Enhanced Cordless
Telecommunications systems (DECT). The family is
designed for minimal component-count and minimal power
consumption for very long standby times. All baseband
controllers include an embedded 80C51 microcontroller
with on-chip memory, including an IrDA (Infrared Data
Association) compatible UART and I2C-bus. The Burst
Mode Logic performs the time-critical MAC layer functions
for applications in DECT handsets and base stations.
The implemented RF Interface is compatible with the
Philips Burst Mode Controller PCD504x. The ADPCM
transcoding is in compliance with the CCITT
Recommendation G.726. Also included is an on-chip
codec with receive and transmit filters, complying with
CCITT Recommendation G.712. Power-on-reset logic and
power management functions further reduce power
consumption and external components.
Hardware state machines in the Burst Mode Logic (BML)
and the Speech Interface (SPI) execute the lower blocks in
the TBC, CBC and DBC. The 80C51 has control over the
BML and the SPI via tables in SDR. The BML saves serial
data, received via R_DATAP/M, in buffer areas in SDR.
The position of the buffers in SDR is fixed by the 80C51
software by means of the tables previously mentioned.
A-fields and B-fields are stored in separate buffers. In this
way, two traffic bearers, each with their private A-fields,
can share the same B-field buffer as is required in case of
bearer hand-over or local call. The DSP and Codec
support speech processing functions like analog-to-digital
and digital-to-analog conversion, filtering, ADPCM
encoding and decoding, 8-bit µ-law PCM to 14-bit linear
PCM conversion and its reverse, echo cancelling, tone
generation etc.
The chip is intended to support stand-alone systems only
(see Fig.3). There are no provisions to build clusters of
base stations. There are no provisions for external
controllers to exert control over the embedded 80C51.
There are no provisions for external controllers to have
direct access to the on-chip data memories. There are no
provisions to allow handsets to receive from two
unsynchronised base stations simultaneously, but a
handset can operate in a multi base station environment
as long as they are synchronous base stations.
EARPIECE
PCD50912
RADIO
CIRCUITS
MICROPHONE
MGM860
a. Handset.
LINE
INTERFACE
(e.g. PCA1070)
RADIO
CIRCUITS
PCD50922
a/b line
MGM859
b. Base station.
Fig.3 Block diagram examples of DECT systems with PCD509xy.
10
1998 Apr 27
Philips Semiconductors
Objective specification
Low cost; low power DECT baseband
controllers (ABC-PRO)
PCD509x2/zuu/v family
7
PACKAGE OUTLINE
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SOT315-1
y
X
A
60
41
Z
61
40
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
L
pin 1 index
80
21
detail X
1
20
Z
D
v
M
A
e
w M
b
p
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
7o
0o
0.16 1.5
0.04 1.3
0.27 0.18 12.1 12.1
0.13 0.12 11.9 11.9
14.15 14.15
13.85 13.85
0.75
0.30
1.45 1.45
1.05 1.05
mm
1.6
0.25
0.5
1.0
0.2 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-12-19
97-07-15
SOT315-1
1998 Apr 27
11
Philips Semiconductors
Objective specification
Low cost; low power DECT baseband
controllers (ABC-PRO)
PCD509x2/zuu/v family
If wave soldering cannot be avoided, for LQFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
8
SOLDERING
Introduction
8.1
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
8.2
Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
8.4
Repairing soldered joints
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
8.3
Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
CAUTION
Wave soldering is NOT applicable for all LQFP
packages with a pitch (e) equal or less than 0.5 mm.
1998 Apr 27
12
Philips Semiconductors
Objective specification
Low cost; low power DECT baseband
controllers (ABC-PRO)
PCD509x2/zuu/v family
9
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
Short-form specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
The data in this specification is extracted from a full data sheet with the same type
number and title. For detailed information see the relevant data sheet or data handbook.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
10 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
11 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Apr 27
13
Philips Semiconductors
Objective specification
Low cost; low power DECT baseband
controllers (ABC-PRO)
PCD509x2/zuu/v family
NOTES
1998 Apr 27
14
Philips Semiconductors
Objective specification
Low cost; low power DECT baseband
controllers (ABC-PRO)
PCD509x2/zuu/v family
NOTES
1998 Apr 27
15
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For all other countries apply to: Philips Semiconductors,
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International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA59
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
435102/1200/01/pp16
Date of release: 1998 Apr 27
Document order number: 9397 750 03527
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