NVT4556AUKZ_技术文档

NVT4556

SIM card interface level translator with I²C-bus control and

LDO

Rev. 1.1 — 25 August 2015

Product data sheet

1. General description

The NVT4556 device is built for interfacing a SIM card with a single low-voltage host-side

interface. The NVT4556 contains an LDO that can deliver two different voltages, 1.8 V or

3 V, from a typical mobile phone battery voltage, and three level translators to convert the

data, RSTn and CLKn signals between a SIM card and a host microcontroller.

The NVT4556 V_CCpin provides power to the host side I/Os and doubles as an enable pin,

for this reason it can be connected to a GPIO that matches the host side voltage. The total

current draw from the V_CCpin is only 100 A maximum. The NVT4556 also uses the

I²C-bus interface to enable normal operation and to select either 1.8 V or 3 V for the SIM

card power supply. The NVT4556 can also disable the LDO functionality while maintaining

the level translator paths so that the user can use a system-controlled regulator to power

the SIM card power supply. The NVT4556 can enable users to provide second and third

SIM card functionality with a low-voltage one host SIM port, at the same time reducing the

number of GPIOs used in the system. The NVT4556 is compliant with all ETSI, IMT-2000

and ISO-7816 SIM/Smart card interface requirements.

The NVT4556 is available in a 12-pin WLCSP package and has three factory

programmed slave address options.

2. Features and benefits

 Support SIM card supply voltages 1.8 V and 3 V

 Input voltage range to LDO: 2.5 V to 5.25 V

 Host microcontroller operating voltage range: 1.55 V to 3.6 V

 V_CCinput pin provides both host supply voltage and logic level hardware

enable/disable pin: source through Host GPIO (I_CC<100 A)

 RST_HOST/EN pin can be programmed as a reset pin or as a device enable/disable

 Level translation of I/O, RSTn and CLKn between SIM card and host-side interface

with capacitive isolation

 I²C-bus interface for device enable and LDO voltage selection

 Low current shutdown mode < 3 A

 Supports clock speed beyond 5 MHz clock

 Supports CLK stop mode

 Integrated EMI filters

 Incorporates ISO-7816-3 shutdown feature for the SIM card signals

 ETSI, IMT2000 and ISO-7816 compliant

 8 kV IEC61000-4-2 ESD protected on all SIM card contact pins

NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

 Pb-free, Restriction of Hazardous Substances (RoHS) compliant and free of halogen

and antimony (Dark Green compliant)

 Available in 12-pin WLCSP package (1.205 mm  1.605 mm  0.412 mm,

0.4 mm pitch)

3. Applications

 NVT4556 can be used with a range of SIM card attached devices including:

 Mobile and personal phones

 Wireless modems

 SIM card terminals

4. Ordering information

Table 1.

Ordering information

Type number

Topside Package

mark

Name

WLCSP12 wafer level chip-size package; 12 balls;

body 1.205  1.605  0.412 mm (Backside coating included)

WLCSP12 wafer level chip-size package; 12 balls;

body 1.205  1.605  0.412 mm (Backside coating included)

Description

Version

NVT4556AUK

NVT4556BUK

556A

NVT4556AUK

556B

NVT4556BUK

4.1 Ordering options

Table 2.

Ordering options

Type number Orderable

part number

Package

Packing method

Minimum Temperature

order

Slave

address

quantity

NVT4556AUK NVT4556AUKZ

NVT4556BUK NVT4556BUKZ

WLCSP12 Reel 7” Q1/T1

*Special mark chips

3000

T_amb= 40 C to +85 C 1100 000xb

dry pack

WLCSP12 Reel 7” Q1/T1

3000

T_amb= 40 C to +85 C 1100 001xb

*Special mark chips

dry pack

NVT4556

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Product data sheet

Rev. 1.1 — 25 August 2015

2 of 27

NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

5. Functional diagram

SDA

REGISTERS

2

I C-BUS

AND

SCL

CONTROL LOGIC

V

BAT

VSIM

LDO

V

CC

UVLO

RST_HOST/EN

RST_SIM

CLK_SIM

CLK_HOST

IO_HOST

IO_SIM

GND

002aah626

Fig 1. Functional diagram

6. Pinning information

bump A1

index area

NVT4556UK

A1

B1

C1

D1

A2

A3

B3

C3

B2

C2

D2

1

2

3

A

B

C

D

IO_HOST

GND

SDA

V

CC

RST_HOST/

EN

V

BAT

CLK_HOST

SCL

VSIM

D3

CLK_SIM

RST_SIM

IO_SIM

002aah627

002aah634

Transparent top view

Fig 2. Bump configuration for WLCSP12

Fig 3. Bump mapping for WLCPS12

NVT4556

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Product data sheet

Rev. 1.1 — 25 August 2015

3 of 27

NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

6.1 Pin description

Table 3.

Symbol

IO_HOST

Pin description

Type

Description

A1

I/O

Host controller bidirectional data input/output. This output

must be on an open-drain configuration.

GND

V_CC

A2

A3

ground Ground for the SIM card and host controller. Proper grounding

and bypassing are required to meet ESD specifications.

power

Supply voltage for the host controller side input/output pins

(CLK_HOST, RST_HOST/EN, IO_HOST). When V_CCis below

the UVLO threshold, the VSIM supply is disabled. This pin

should be bypassed with a 100 nF ceramic capacitor close to

the pin.

RST_HOST/EN B1

I

Reset input from host controller or acts as a programmable

logic-level enable/disable when bit 6 = 1.

SDA

V_BAT

B2

B3

I/O

Digital input/output. I²C-bus serial bidirectional data line;

open-drain.

power

Battery voltage supply for internal LDO. This input voltage

ranges from 2.5 V to 5.25 V. This pin should be bypassed with

a 1.0 F ceramic capacitor close to the pin.

CLK_HOST

SCL

C1

C2

C3

I

Clock input from host controller.

Digital input. I²C-bus serial bidirectional clock line.

I

VSIM

power

SIM card supply voltage from internal LDO. The voltage at this

pin can be selected for either 1.8 V (CTRL = 0) or 3 V

(CTRL = 1). This pin should be bypassed with a 4.7 F

ceramic capacitor close to the pin.

CLK_SIM

RST_SIM

IO_SIM

D1

D2

D3

O

Clock output pin for the SIM card.

Reset output pin for the SIM card.

O

I/O

SIM card bidirectional data input/output. The SIM card output

must be on an open-drain driver.

NVT4556

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Product data sheet

Rev. 1.1 — 25 August 2015

4 of 27

NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

7. Functional description

Refer to Figure 1 “Functional diagram”.

7.1 Shutdown sequence of NVT4556

The ISO 7816-3 specification specifies the shutdown sequence for the SIM card signals.

This shutdown sequence ensures that these channels are properly disabled and does not

have any accidental corruption of data. Also during hot swap, the orderly shutdown of

these signals helps to avoid any improper write and corruption of data.

When the V_CCfalls below its UVLO threshold, a shutdown sequence is immediately

initiated. The RST_SIM is first driven LOW after a short delay the CLK_SIM and IO_SIM

are driven LOW followed by VSIM. An internal pull-down resistor on the SIM pins is used

to pull these channels LOW. The shutdown sequence is completed in a few

microseconds.

UVLO

threshold

V

CC

RST_SIM

CLK_SIM

IO_SIM

VSIM

t

dis(CLK_SIM)

ACTIVE DATA

t

dis(VSIM)

002aah639

Fig 4. V_CCUVLO shutdown sequence for RST_SIM, CLK_SIM, IO_SIM and VSIM of

NVT4556 SIM card translator

The shutdown sequence can also be initiated by one of two events: by de-asserting the

RST_HOST/EN pin if bit 6 (RST_HOST pin mode select bit) is set to 1, or by writing a 0 to

bit 0 (Device enable bit) if bit 6 is set to 0. The shutdown sequence consists of first

powering down the RST_SIM channel. Once the RST_SIM channel is powered down,

CLK_SIM, IO_SIM and VSIM are powered down sequentially one-by-one. An internal

pull-down resistor on the SIM pins is used to pull these channels LOW. The shutdown

sequence is completed in a few microseconds. It is important that enable is written LOW

before V_BATand V_CCsupplies go LOW to ensure that the shutdown sequence is properly

initiated. The NVT4556 is enabled and disabled at the end of the I²C-bus write sequence,

so a delay in the start of the I/O signals should account for time of this data sequence.

NVT4556

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Product data sheet

Rev. 1.1 — 25 August 2015

5 of 27

NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

SCL

SDA

SLAVE ADDRESS

ACK

DATA

ACK

t

dis(RST_SIM)

RST_SIM

CLK_SIM

IO_SIM

VSIM

dis(CLK_SIM)

t

dis(IO_SIM)

ACTIVE DATA

t

dis(VSIM)

002aah640

Fig 5. I²C-bus shutdown sequence for RST_SIM, CLK_SIM, IO_SIM and VSIM of

NVT4556 SIM card translator

7.2 RST_HOST/EN pin

The NVT4556 RST_HOST/EN pin can be programmed to accept the reset signal from the

host to the SIM card or programmed to be an enable pin for the part. When the NVT4556

is programmed with bit 6 = 0, the RST_HOST/EN pin acts as a pass-through logic-level

translator. A 0 on the host side appears as a 0 on the SIM side, and a 1 at the host side

appears as a 1 on the SIM side. When the NVT4556 is programmed with bit 6 = 1, the

RST_HOST/EN pin becomes a hardware enable/disable pin, so that the part can be

enabled and disabled with a logic level input. In this case, the V_CCcan be powered from

the host supply and does not need to be pulled down to disable the part. Also, the reset

signal for the SIM card must be written to bit 5. When a 1 is written to bit 5, a logic 1 is

asserted onto RST_SIM. When a 0 is written to bit 5, a logic 0 is asserted on onto

RST_SIM.

When bit 6 is set to 1 and RST_HOST/EN acts as an enable pin, bit 0 is ignored and only

logic signals acting on RST_HOST/EN and the V_CCenable and disable the part. Bit 0 can

be read to see the state of the RST_HOST/EN pin and bit 3 can be programmed to set the

EN polarity to be active HIGH or active LOW.

7.3 Clock stop, latch I/O state

The NVT4556 can also support clock stop modes as well as an I/O stop so that two

NVT4556 devices can operate from a single host SIM port. The NVT4556 can latch the

state of the IO_HOST, CLK_HOST and RST_HOST/EN when bit 4 is toggled to 1. This

asserts the logic value onto the IO_SIM, CLK_SIM and RST_SIM pins. This effectively

initiates the clock stop mode and free the user to activate a secondary NVT4556 attached

to the same host port. The NVT4556 devices must have different I²C-bus addresses so

that they can be accessed independently of each other.

If bit 6 is programmed to 1 and the RST_HOST/EN pin is acting as an enable pin, then

bit 5 must be used to latch the RST_SIM state through the I²C-bus.

NVT4556

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Product data sheet

Rev. 1.1 — 25 August 2015

6 of 27

NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

7.4 Software reset

The Software Reset Call allows all the devices in the I²C-bus to be reset to the power-up

state value through a specific formatted I²C-bus command. To be performed correctly, it

implies that the I²C-bus is functional and that there is no device hanging the bus.

The Software Reset sequence is defined as the following (see Figure 6):

1. A START command is sent by the I²C-bus master.

2. The reserved General Call I²C-bus address ‘0000 000’ with the R/W bit set to 0 (write)

is sent by the I²C-bus master.

3. The NVT4556 device(s) acknowledge(s) after seeing the General Call address

‘0000 0000’ (00h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to

the I²C-bus master.

4. Once the General Call address has been sent and acknowledged, the master sends

1 byte. The value of the byte must be equal to 06h. The NVT4556 acknowledges this

value only. If the byte is not equal to 06h, the NVT4556 does not acknowledge it. If

more than 1 byte of data is sent, the NVT4556 does not acknowledge any more.

5. Once the right byte has been sent and correctly acknowledged, the master sends a

STOP command to end the Software Reset sequence: NVT4556 then resets to the

default value (power-up value) and is ready to be addressed again within the specified

bus free time. If the master sends a Repeated START instead, no reset is performed.

2

SWRST Call I C-bus address

SWRST data = 06h

S

0

A

0

1

0

A

P

START condition

R/W acknowledge

from slave(s)

acknowledge

from slave(s)

STOP condition;

NVT4556 is(are) reset.

Registers are set to default power-up values.

002aah742

Fig 6. Software reset sequence

The I²C-bus master must interpret a non-acknowledge from the NVT4556 (at any time)

as a ‘Software Reset Abort’.

NVT4556

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Product data sheet

Rev. 1.1 — 25 August 2015

7 of 27

NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

8. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

[1]

V_ESD

electrostatic discharge voltage

SIM card side and VSIM pins;

IEC 61000-4-2

-

8

kV

[1]

[2]

[3]

all other pins; IEC 61000-4-2

all other pins; HBM

-

2

kV

V

2

all other pins; CDM

500

V_CC

supply voltage

GND  0.5 3.6

V

V_BAT

battery supply voltage

GND  0.5 5.5

V

V_{I(CLK_HOST)}

input voltage on pin CLK_HOST input signal voltage, HOSTside

GND  0.5 V_CC+ 0.5

V

V_{I(RST_HOST/EN)}input voltage on pin

RST_HOST/EN

input signal voltage, HOSTside

V

V_{I(IO_HOST)}

V_{I(CLK_SIM)}

V_{I(RST_SIM)}

V_{I(IO_SIM)}

T_stg

input voltage on pin IO_HOST

input signal voltage, HOSTside

input signal voltage, SIM side

GND  0.5 V_CC+ 0.5

GND  0.5 V_VSIM+ 0.5

V

input voltage on pin CLK_SIM

input voltage on pin RST_SIM

input voltage on pin IO_SIM

storage temperature

V

55

40

+125

+85

C

T_amb

ambient temperature

[1] IEC 61000-4-2, level 4, contact discharge.

[2] Human Body Model (HBM) according to JESD22-A114.

[3] Charged-Device Model (CDM) according to JESD22-C101.

NVT4556

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Product data sheet

Rev. 1.1 — 25 August 2015

8 of 27

NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

9. Characteristics

Table 5.

Supplies

2.5 V  V_BAT 5.5 V; 1.55 V  V_CC 3.6 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

V_CC

Parameter

Conditions

Min

1.55

-

Typ^[1]Max

Unit

V

supply voltage

supply current

-

3.6

I_CC

operating mode; register 00h = 01h/03h;

40

100

A

SDA = IO_HOST = V_CC

RST_HOST/EN = GND;

_clk= 1 MHz; f_clk(SCL)= 400 kHz

;

f

operating mode; register 00h = 01h/03h;

SDA = SCL = IO_HOST = V_CC

RST_HOST/EN = GND; f_clk= 1 MHz

-

10

5

20

10

A

;

operating mode; register 00h = 01h/03h;

SCL = SDA = IO_HOST = V_CC

;

CLK_HOST = RST_HOST/EN = GND

standby mode; register 00h = 00h;

SDA = SCL = IO_HOST = V_CC

;

CLK_HOST = RST_HOST/EN = GND;

V_CC= 1.8 V

shut-down mode; register 00h = 00h;

-

1

A

V_CC= 0 V

V_BAT

I_BAT

battery supply voltage

battery supply current

2.5

-

5.25

40

V

operating mode; register 00h = 01h/03h;

IO_HOST = V_CC

30

A

;

CLK_HOST = RST_HOST/EN = GND

shutdown mode; register 00h = 00h

V_CCrising; V_BAT= 3.6 V

-

2

-

3

A

V_th(UVLO)

undervoltage lockout

threshold voltage

1.2

1.5

V

V_hys(UVLO)

undervoltage lockout

hysteresis voltage

-

100

-

mV

[1] Typical values measured at 25 C. V_CC= 1.8 V; V_BAT= 3.6 V; V_VSIM(VSIM pin) = 1.8 V.

Table 6.

Static characteristics

2.5 V  V_BAT 5.5 V; 1.55 V  V_CC 3.6 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

I²C-bus

f_clk(SCL)

V_IH

Parameter

Conditions

Min

Typ^[1]

Max

Unit

SCL clock frequency

-

400

-

kHz

V

HIGH-level input voltage pins SCL, SDA

LOW-level input voltage pins SCL, SDA

0.7  V_CC

-

V_IL

-

0.3  V_CC

V

I_{OL(sink)(SDA)}LOW-level output sink

current on pin SDA

V_OL= 0.4 V

3

-

mA

NVT4556

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Product data sheet

Rev. 1.1 — 25 August 2015

9 of 27

NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

Table 6.

Static characteristics …continued

2.5 V  V_BAT 5.5 V; 1.55 V  V_CC 3.6 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

LDO

Parameter

Conditions

Min

Typ^[1]

Max

Unit

V_VSIM

voltage on pin VSIM

VSIM pin; 00h = 03h;

3.2 V  V_BAT 5.25 V;

0 mA  I_SIM 50 mA

2.85

3.0

3.15

V

VSIM pin; 00h = 01h;

2.5 V  V_BAT 5.25 V;

0 mA  I_SIM 50 mA

1.7

1.8

1.9

V

V_do

dropout voltage

short-circuit current

start-up time

I_O= 50 mA; V_BAT= 2.90 V

VSIM shorted to GND

-

100

135

-

150

170

400

mV

mA

s

I_sc

90

-

t_startup

V_VSIM= 1.8 V or 3 V;

I_O= 50 mA; C_o= 1 F

T_j(sd)

shutdown junction

temperature

-

160

20

-

°C



T_sd(hys)

R_pd

hysteresis of shutdown

temperature

pull-down resistance

VSIM discharge; 00h = 00h;

V_BAT= 3.6 V; V_CC= 1.55 V

100

PSRR

power supply rejection

ratio

V_BAT= 3.6 V; I_SIM= 20 mA;

V_VSIM= 1.8 V or 3 V

f = 1 kHz

-

60

50

-

dB

f = 10 kHz

Level shifter

V_IH

HIGH-level input voltage IO_HOST, RST_HOST/EN,

CLK_HOST

[2]

1.55 V  V_CC< 3.6 V

0.7  V_CC

0.7  V_VSIM

0.15

-

V_CC+ 0.2

V_VSIM+ 0.2

0.15  V_CC

V

IO_SIM

V_IL

LOW-level input voltage IO_HOST, RST_HOST/EN,

CLK_HOST

[2]

[3]

[2]

IO_SIM

0.3

4

-

0.15  V_VSIM

V

R_PU

pull-up resistance

IO_SIM connected to VSIM

IO_HOST connected to V_CC

6

5

8

k

V

3.5

-

6.5

V_OH

HIGH-level

RST_SIM, CLK_SIM;

0.7  V_VSIMV_VSIM

output voltage

I_OH= 1 mA

[2]

IO_SIM; I_OH= 10 A

IO_HOST; I_OH= 10 A

RST_SIM, CLK_SIM;

-

0.7  V_VSIMV_VSIM

V

0.7  V_CC

V_CC

300

V

V_OL

LOW-level

100

mV

output voltage

I_OL= 1 mA

[2]

IO_SIM; I_OL= 1 mA

-

100

300

130

mV

k

IO_HOST; I_OL= 1 mA

-

R_pd

pull-down resistance

CLK_HOST,

70

RST_HOST/EN; EN = 0

NVT4556

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Product data sheet

Rev. 1.1 — 25 August 2015

10 of 27

NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

Table 6.

Static characteristics …continued

2.5 V  V_BAT 5.5 V; 1.55 V  V_CC 3.6 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

EMI filter

R_s

Parameter

Conditions

Min

Typ^[1]

Max

Unit

[2][4]

[4]

series resistance

IO_SIM

-

200

45

-



RST_SIM

CLK_SIM



[2][4]

[4]



C_io

input/output capacitance IO_SIM

RST_SIM

pF

45

[2][4]

CLK_SIM

45

[1] Typical values measured at 25 C.

[2] V_IL, V_IHdepend on the individual supply voltage per interface.

[3] See Figure 10 for details.

[4] Guaranteed by design.

Table 7.

Dynamic characteristics

2.5 V  V_BAT 5.5 V; f_clk= f_io= 1 MHz; T_amb= 40 C to +85 C; unless otherwise specified. Refer to Figure 7.

Symbol Parameter Conditions Min Typ Max Unit

V_CC= 1.8 V; VSIM = 3 V; SIM card C_L 30 pF; host C_L 10 pF

[1]

t_d(latch)

latch delay time

time after ACK from I²C-bus write to latch host I/Os

to SIM I/Os; bit 4 = 1

-

5

s

[1]

[2]

[1]

t_t

transition time

-

10

-

ns

t_sk(o)

t_PD

output skew time

propagation delay

between channels; IO_SIM and CLK_SIM

I/O channel; SIM card side to host side

all channels; host side to SIM card side

CLK_SIM

-

2

ns

-

15

-

25

-

ns

-

ns

f_o(clk)

clock output frequency

5

-

MHz

s

t_{dis(RST_SIM)}RST_SIM disable time

disable time from initiating RST_HOST/EN bit 6 = 1

or from I²C-bus disable ACK

20

50

t_{dis(CLK_SIM)}CLK_SIM disable time

-

25

60

65

-

s

t_{dis(IO_SIM)}

t_dis(VSIM)

IO_SIM disable time

VSIM disable time

35

C_o(L)= 4.7 F

200

[1] All dynamic measurements are done with a 50 pF load. Rise times are determined by internal pull-up resistors.

[2] Skew between any two outputs of the same package switching in the same direction with the same C_L.

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Product data sheet

Rev. 1.1 — 25 August 2015

11 of 27

NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

9.1 Waveforms

V

I

input

V

M

GND

t

PHL

PLH

V

OH

90 %

output

V

M

10 %

OL

t

TLH

THL

002aag078

Measurement points are given in Table 7.

V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 7. Data input to data output propagation delay times

NVT4556

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Product data sheet

Rev. 1.1 — 25 August 2015

12 of 27

NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

10. Application information

Figure 8 is the application circuit for the NVT4556 and shows the typical interface with a

SIM card. The V_CCpin on the NVT4556 powers the host I/O pins and is designed to be

driven from a GPIO. This GPIO then acts as both the host-side power supply and an

enable/disable pin. The NVT4556 provides a Low-DropOut (LDO) regulator that is

designed for high Power Supply Rejection Ratio (PSRR) at a very low drop-out voltage

(V_BAT V_VSIM). The LDO regulator provides two levels of fixed voltage regulation at 1.8 V

or 3 V, which are selected with an I²C-bus write. Since there is only one register, a

subaddress is not necessary.

V

BAT

(2.5 V to 5.25 V)

1 μF

100 nF

GPIO

V

CC

2

(1.8 V or 3 V; 50 mA max.)

VSIM

SCL

SDA

LDO

REGULATOR

I C-BUS

INTERFACE

4.7 μF

HOST

PROCESSOR

NVT4556

SIM CARD

RST_HOST/EN

CLK_HOST

IO_HOST

RST_SIM

CLK_SIM

IO_SIM

LEVEL

TRANSLATOR

002aah630

Fig 8. NVT4556 application circuit interfacing with typical SIM card

NVT4556

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Product data sheet

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NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

10.1 Input/output capacitor considerations

It is recommended that a 1 F capacitor and a 100 nF capacitor having low Equivalent

Series Resistance (ESR) are used respectively at the battery (V_BAT) and V_CCinput

terminals of the NVT4556. X5R and X7R type multi-layer ceramic capacitors (MLCC) are

preferred because they have minimal variation in value and ESR over temperature. The

maximum ESR should be < 500 m(50 m typical).

Also, a 2.2 F to 4.7 F capacitor is recommended at the Low Dropout regulator (LDO)

output terminal to ensure stability. X5R and X7R type are recommended for their minimal

variation over temperature and low ESR over frequency which avoids stability issues at

high frequencies. The maximum ESR should be < 1.0 . Furthermore, the decrease in

capacitance with an increase in the bias voltage should be considered to optimize LDO

stability. In addition, the trade-off in LDO stability versus the value and constraint in case

size of the capacitor determined by the application must be considered. As output load

capacitance decreases, the LDO stability becomes marginal. A given 4.7 F ceramic

capacitor may become 0.33 F capacitance depending on the effects of bias voltage and

temperature. It is recommended to refer to the manufacturer’s characterization of a

capacitor based on case size, bias voltage and type. Figure 9 is an example of how a

4.7 F capacitor is affected by the above parameters.

002aah650

20

∆C

/

C

(%)

1206, 6.3 V

−20

1206, 10 V

0805, 6.3 V

0603, 6.3 V

−60

0805, 10 V

0603, 10 V

0402, 6.3 V

−100

0

2

4

6

8

10

V

DC

(V)

Fig 9. Variation of capacitance for a 4.7 F capacitor versus DC voltage, value, and case size

10.2 Layout consideration

The capacitors should be placed directly at the terminals and ground plane. Since the

internal band gap regulator is the dominant noise source in a typical application,

connections and routing of the ground is very important to improve and optimize noise

performance, PSRR and transient response. It is recommended to design the PCB with

separate ground planes for the V_I(V_BAT) and V_O(VSIM) of the LDO regulator with each

ground plane connected only at the GND pin of the NVT4556.

NVT4556

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NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

10.3 Dropout voltage

The NVT4556 uses a PMOS pass transistor to achieve a very low dropout voltage. When

V_BAT V_VSIMis less than the dropout voltage, the PMOS transistor operates in the linear

region and the input-to-output resistance is R_DSonof the PMOS device. The dropout

voltage, V_do, scales with the output current since the PMOS device behaves like a resistor

in the input-to-output path.

10.4 Level translator stage

The architecture of the NVT4556 I/O channel is shown in Figure 10. The device does not

require an extra input signal to control the direction of data flow from host to SIM or from

SIM to host. As a change of driving direction is possible only when both sides are in HIGH

state, the control logic is recognizing the first falling edge granting it control about the

other signal side. During a rising edge signal, the non-driving output is driven by a

one-shot circuit to accelerate the rising edge. In case of a communication error or some

other unforeseen incident that would drive both connected sides to be drivers at the same

time, the internal logic automatically prevents stuck-at situation, so both I/Os return to

HIGH level once released from being driven LOW.

The channels RST and CLK contain single direction drivers without the holding

mechanism of the I/O channel, as these are driven only from the host to the card side.

VSIM

side B supply

RISING EDGE

DETECT

ONE

SHOT

pull-up

IO_SIM

DIRECTION

CONTROL

CIRCUITRY

V

CC

side A supply

ONE

SHOT

RISING EDGE

DETECT

pull-up

IO_HOST

aaa-012269

Fig 10. Automatic direction control level translator for HIGH-level direction change interfaces

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NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

10.5 LDO block diagram

The block diagram of the LDO is depicted in Figure 11. It contains a pull-down mechanism

to avoid any uncontrolled voltage level at the VSIM pin in the disabled state. Furthermore,

thermal protection as well as an overcurrent protection are integrated to disable the output

in case of a permanent short that may result in excessive self-heating.

VSIM

V

BAT

R1

V

ref

enable and control

GENERATOR

2

from I C-bus

THERMAL

PROTECTION

R2

OVERCURRENT

PROTECTION

002aah629

GND

Fig 11. LDO block diagram

The default LDO output voltage is 1.8 V but can be selected to be either 1.8 V or 3.0 V

through the proper I²C-bus writes.

The I²C-bus has the ability to disable the LDO such that the VSIM can be powered

through an external system regulator. If the LDO is disabled, the RSTn, CLKn and IOn

data paths are still active. It is necessary to supply external power to the V_CC, VSIM, and

V

_BATpower supply pins, since there is active circuitry that still exists on the three supplies.

10.6 Power-on reset

When power is applied to V_CC, an internal Power-On Reset (POR) holds the NVT4556 in

a reset condition until V_CChas reached V_POR. At that point, the reset condition is released

and the NVT4556 registers and I²C-bus state machine initialize to their default states.

Thereafter V_CCmust be lowered below 1.2 V to reset the device.

10.7 Serial bus interface

The NVT4556 communicates with a host controller by means of the 2-wire serial bus

(I²C-bus) that consists of a serial clock (SCL) and serial data (SDA) signals. The device

supports I²C-bus Standard-mode and Fast-mode. The I²C-bus Standard-mode speed is

defined to have bus speeds from 0 Hz to 100 kHz. I²C-bus Fast-mode speed is from 0 Hz

to 400 kHz. The host or bus master generates the SCL signal and the NVT4556 uses the

SCL signal to receive or send data on the SDA line. Data transfer is serial, bidirectional,

and is 1 byte at a time with the Most Significant Bit (MSB) transferred first. Since SCL and

SDA are open-drain, pull-up resistors must be installed on these pins.

NVT4556

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NVT4556

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SIM card interface level translator with I²C-bus control and LDO

10.8 Slave address

The NVT4556 uses a 7-bit slave address to identify it on the I²C-bus. The last bit of the

address byte defines the operation to be performed. When set to logic 1, a read is

selected, while a logic 0 selects a write operation. The level translator’s 7-bit fixed slave

address is ‘60h’ for the NVT4556AUK, ‘61h’ for the NVT4556BUK and ‘62h’ for the

NVT4556CUK. However, for a write operation (R/W bit = 0) to the NVT4556, the address

byte content (8 bits) is ‘C0h’ for the NVT4556AUK, ‘C2h’ for the NVT4556BUK, and

‘C4h’ for the NVT4556CUK.

Remark: Device variant NVT4556CUK is under development.

slave address

R/W

X

slave address

R/W

X

slave address

R/W

X

MSB

1

LSB

0

MSB

1

LSB

1

MSB

1

LSB

0

1

0

1

0

1

0

1

002aah651

002aah656

002aah657

a. NVT4556A

Fig 12. Slave address; normal read/write

b. NVT4556B

c. NVT4556C

(under development)

10.9 I²C-bus interface

There is only one data register in this device, so the Pointer register is always set to ‘00h’.

For this reason, a subaddress is not required for reading or writing. Only data is required

to be sent on the bus after a slave address acknowledge.

A ‘write’ to this device always includes the slave address byte and data byte.

A ‘read’ to this device always includes the slave address byte and data byte.

The data byte has the most significant bit first. At the end of a read, this device can accept

either Acknowledge (ACK) or No Acknowledge (NACK) from the Master (No Acknowledge

is typically used as a signal for the slave that the Master has read its last byte).

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

SCL

SDA

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

S

W

A

P

START

device address and write

ACK

by slave

register data

ACK

by slave

STOP

002aah652

A = ACK = Acknowledge bit. W = Write bit = 0.

Fig 13. I²C-bus write to NVT4556A

NVT4556

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SIM card interface level translator with I²C-bus control and LDO

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

SCL

SDA

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

S

R

A

P

START

device address and read

ACK

by slave

register data

NACK STOP

by master

002aah653

A = ACK = Acknowledge bit. R = Read bit = 1.

Fig 14. I²C-bus read from NVT4556A

10.10 Write operations

10.10.1 Byte Write

In Byte Write mode, the master creates a START condition and then broadcasts the slave

address and data to be written. The slave acknowledges the bytes by pulling down the

SDA line during the ninth clock cycle following each byte. The master creates a STOP

condition after the last ACK from the slave, which then starts the internal write operation

(see Figure 15). During internal write, the slave ignores any read/write request from the

master.

slave address

data

SDA

S

1

0

A

0

D1 D0

A

P

START condition

R/W acknowledge

from slave

acknowledge

from slave

STOP condition

002aah654

Fig 15. Byte Write for NVT4556A

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SIM card interface level translator with I²C-bus control and LDO

10.11 Read operations

10.11.1 Byte Read

If the NVT4556 decodes a slave address with a ‘1’ in the R/W bit position (Figure 16), it

issues an Acknowledge in the ninth clock cycle and then transmits the data byte. The

master can then stop further transmission by issuing a No Acknowledge on the ninth bit

then followed by a STOP condition.

slave address

data

SDA

S

1

0

1

A

P

START condition

R/W acknowledge

from slave

no acknowledge

from master

STOP condition

002aah655

Fig 16. Byte Read for NVT4556A

10.12 User accessible registers

10.12.1 Register overview

This section describes all the registers used in the NVT4556. The device contains only

one register which is read/write-able. No subaddress is necessary when reading or writing

to the device.

Table 8.

Address

00h

Register summary

Register name

DEV_CFG

Description

Device information and revision and enable functions

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NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

10.12.2 Register map

Table 9.

User accessible register maps

Legend: * = default. Register modes and default values are only valid with operating the NVT4556 in I²C-bus mode.

Address Register

name

Symbol Bit Description

00h

DEV_CFG

Device information. Contains enable functions.

D7

D6

7

6

LDO disable; enables/disables the LDO. The I/O paths are still operational. V_VSIM

(VSIM pin) must be provided from the system. V_BATmust be connected to the

battery voltage.

0* — LDO enabled (default)

1 — LDO disabled

RST_HOST/EN pin mode select

0* — RST_HOST enabled (default)

The RST_HOST/EN pin passes the logic on the input directly to the RST_SIM pin.

1 — EN

The RST_HOST/EN pin becomes an enable/disable pin for the device. The

polarity of the RST_HOST/EN pin is set by bit 3.

The RST_SIM signal is sent through bit 5.

RST_SIM active: this bit is active only when bit 6 = 1.

0* — RST_SIM disable (default)

D5

D4

5

4

This sends and latches a logic LOW to the RST_SIM pin.

1 — RST_SIM enabled

This sends and latches a logic HIGH to the RST_SIM pin.

Latch IO states

Setting this bit latches the state of the input pins IO_HOST, CLK_HOST and

RST_HOST/EN (when bit 6 = 0) to the output pins IO_SIM, CLK_SIM, and

RST_SIM.

This can be used for clock stop when two NVT4556 devices are used on the same

host.

0* — Latch OFF (default)

1 — I/Os latched

D3

3

Enable polarity. This bit sets the RST_HOST/EN pin polarity when bit 6 is set to 1.

0* — Active HIGH enable: Device enables when RST_HOST/EN pin = 1.

1 — Active LOW enable: Device enables when RST_HOST/EN pin = 0.

-

2

1

reserved

D1

Voltage selection: selects the output voltage of the LDO

0* — 1.8 V (default)

1 — 3 V

D0

0

Device enable

0* — Disable (default)

1 — Enable

bit 6 = 0: R/W

bit 6 = 1: R only and displays RST_HOST/EN status

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NVT4556

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SIM card interface level translator with I²C-bus control and LDO

11. Package outline

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Fig 17. Package outline NVT4556UK (WLCSP12)

NVT4556

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NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

12. Soldering of WLCSP packages

12.1 Introduction to soldering WLCSP packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note

AN10439 “Wafer Level Chip Scale Package” and in application note AN10365 “Surface

mount reflow soldering description”.

Wave soldering is not suitable for this package.

All NXP WLCSP packages are lead-free.

12.2 Board mounting

Board mounting of a WLCSP requires several steps:

1. Solder paste printing on the PCB

2. Component placement with a pick and place machine

3. The reflow soldering itself

12.3 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 18) than a SnPb process, thus

reducing the process window

• Solder paste printing issues, such as smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature), and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic) while being low enough that the packages and/or boards are not

damaged. The peak temperature of the package depends on package thickness and

volume and is classified in accordance with Table 10.

Table 10. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

260

> 2000

260

< 1.6

1.6 to 2.5

> 2.5

260

250

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 18.

NVT4556

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Product data sheet

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NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 18. Temperature profiles for large and small components

For further information on temperature profiles, refer to application note AN10365

“Surface mount reflow soldering description”.

12.3.1 Stand off

The stand off between the substrate and the chip is determined by:

• The amount of printed solder on the substrate

• The size of the solder land on the substrate

• The bump height on the chip

The higher the stand off, the better the stresses are released due to TEC (Thermal

Expansion Coefficient) differences between substrate and chip.

12.3.2 Quality of solder joint

A flip-chip joint is considered to be a good joint when the entire solder land has been

wetted by the solder from the bump. The surface of the joint should be smooth and the

shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps

after reflow can occur during the reflow process in bumps with high ratio of bump diameter

to bump height, i.e. low bumps with large diameter. No failures have been found to be

related to these voids. Solder joint inspection after reflow can be done with X-ray to

monitor defects such as bridging, open circuits and voids.

12.3.3 Rework

In general, rework is not recommended. By rework we mean the process of removing the

chip from the substrate and replacing it with a new chip. If a chip is removed from the

substrate, most solder balls of the chip will be damaged. In that case it is recommended

not to re-use the chip again.

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NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

Device removal can be done when the substrate is heated until it is certain that all solder

joints are molten. The chip can then be carefully removed from the substrate without

damaging the tracks and solder lands on the substrate. Removing the device must be

done using plastic tweezers, because metal tweezers can damage the silicon. The

surface of the substrate should be carefully cleaned and all solder and flux residues

and/or underfill removed. When a new chip is placed on the substrate, use the flux

process instead of solder on the solder lands. Apply flux on the bumps at the chip side as

well as on the solder pads on the substrate. Place and align the new chip while viewing

with a microscope. To reflow the solder, use the solder profile shown in application note

AN10365 “Surface mount reflow soldering description”.

12.3.4 Cleaning

Cleaning can be done after reflow soldering.

13. Abbreviations

Table 11. Abbreviations

Acronym

CDM

EMI

Description

Charged-Device Model

ElectroMagnetic Interference

ElectroStatic Discharge

ESD

GPIO

HBM

I²C-bus

I/O

General Purpose Input/Output

Human Body Model

Inter-Integrated Circuit bus

Input/Output

LDO

Low DropOut regulator

PCB

Printed-Circuit Board

PMOS

SIM

Positive-channel Metal-Oxide Semiconductor

Subscriber Identification Module

UnderVoltage Lock-Out

UVLO

14. Revision history

Table 12. Revision history

Document ID

NVT4556 v.1.1

Modifications:

NVT4556 v.1

Release date

20150825

Data sheet status

Change notice

Supersedes

Product data sheet

-

NVT4556 v.1

• Table 3 “Pin description”: V_CCdescription; changed “1.0 nF” to “100 nF”

20140602

Product data sheet

-

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SIM card interface level translator with I²C-bus control and LDO

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

15.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

NVT4556

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 25 August 2015

25 of 27

NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP Semiconductors N.V.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NVT4556

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 25 August 2015

26 of 27

NVT4556

NXP Semiconductors

SIM card interface level translator with I²C-bus control and LDO

17. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

15.1

15.2

15.3

15.4

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

3

4

4.1

5

16

17

Contact information . . . . . . . . . . . . . . . . . . . . 26

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6

6.1

7

Functional description . . . . . . . . . . . . . . . . . . . 5

Shutdown sequence of NVT4556. . . . . . . . . . . 5

RST_HOST/EN pin. . . . . . . . . . . . . . . . . . . . . . 6

Clock stop, latch I/O state. . . . . . . . . . . . . . . . . 6

Software reset. . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.1

7.2

7.3

7.4

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 9

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

9

9.1

10

Application information. . . . . . . . . . . . . . . . . . 13

Input/output capacitor considerations. . . . . . . 14

Layout consideration . . . . . . . . . . . . . . . . . . . 14

Dropout voltage . . . . . . . . . . . . . . . . . . . . . . . 15

Level translator stage . . . . . . . . . . . . . . . . . . . 15

LDO block diagram. . . . . . . . . . . . . . . . . . . . . 16

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 16

Serial bus interface. . . . . . . . . . . . . . . . . . . . . 16

Slave address. . . . . . . . . . . . . . . . . . . . . . . . . 17

I²C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 17

Write operations . . . . . . . . . . . . . . . . . . . . . . . 18

10.1

10.2

10.3

10.4

10.5

10.6

10.7

10.8

10.9

10.10

10.10.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

10.11 Read operations . . . . . . . . . . . . . . . . . . . . . . . 19

10.11.1 Byte Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

10.12 User accessible registers . . . . . . . . . . . . . . . . 19

10.12.1 Register overview. . . . . . . . . . . . . . . . . . . . . . 19

10.12.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . 20

11

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21

12

12.1

12.2

12.3

12.3.1

12.3.2

12.3.3

12.3.4

Soldering of WLCSP packages. . . . . . . . . . . . 22

Introduction to soldering WLCSP packages . . 22

Board mounting . . . . . . . . . . . . . . . . . . . . . . . 22

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 22

Stand off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Quality of solder joint . . . . . . . . . . . . . . . . . . . 23

Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

13

14

15

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 24

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24

Legal information. . . . . . . . . . . . . . . . . . . . . . . 25

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 25 August 2015

Document identifier: NVT4556


型号：	NVT4556AUKZ
厂家：	NXP
描述：	NVT4556 - SIM card interface level translator with I2C-bus control and LDO 接口集成电路
文件：	总27页 (文件大小：1168K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NVT4556AUKZ [NXP]

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