MK65FN2M0VMI18R [NXP]
RISC MICROCONTROLLER;
| 型号： | MK65FN2M0VMI18R |
| 厂家： | 
NXP |
| 描述： | RISC MICROCONTROLLER 时钟 外围集成电路 |
| 文件： | 总90页 (文件大小：1297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Data Sheet: Technical Data
K65P169M180SF5V2
Rev. 2, 05/2015
Kinetis K65 Sub-Family
MK65FN2M0VMI18
MK65FX1M0VMI18
180 MHz ARM® Cortex®-M4F Microcontroller.
The K65 sub-family members provide greater performance,
memory options up to 2 MB total flash and 256 KB of SRAM, as
well as higher peripheral integration with features such as Dual
USB and a 10/100 Mbit/s Ethernet MAC. These devices maintain
hardware and software compatibility with the existing Kinetis
family. This product also offers:
• Integration of a High Speed USB Physical Transceiver
• Greater performance flexibility with a High Speed Run
mode
169 MAPBGA (MI)
• Smarter peripherals with operation in Stop modes
9 mm x 9 mm Pitch 0.65 mm
Performance
• Up to 180 MHz ARM Cortex-M4 based core with DSP
instructions and Single Precision Floating Point unit
Memories and memory expansion
• Up to 2 MB program flash memory on non-
FlexMemory devices with 256 KB RAM
• Up to 1 MB program flash memory and 256 KB of
FlexNVM on FlexMemory devices
• 4 KB FlexRAM on FlexMemory devices
• FlexBus external bus interface and SDRAM controller
System and Clocks
• Multiple low-power modes to provide power
optimization based on application requirements
• Memory protection unit with multi-master protection
• 3 to 32 MHz main crystal oscillator
Analog modules
• 32 kHz low power crystal oscillator
• 48 MHz internal reference
• Two 16-bit SAR ADCs and two 12-bit DAC
• Four analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
• Voltage reference 1.2V
Security
• Hardware random-number generator
• Supports DES, AES, SHA accelerator (CAU)
• Multiple levels of embedded flash security
Communication interfaces
• Ethernet controller with MII and RMII interface to
external PHY and hardware IEEE 1588 capability
• USB high-/full-/low-speed On-the-Go with on-chip
high speed transceiver
• USB full-/low-speed OTG with on-chip transceiver
• Two CAN, three SPI and four I2C modules
• Low Power Universal Asynchronous Receiver/
Transmitter 0 (LPUART0) and five standard UARTs
• Secure Digital Host Controller (SDHC)
• I2S module
Timers
• Four Periodic interrupt timers
• 16-bit low-power timer
• Two 16-bit low-power timer PWM modules
• Two 8-channel motor control/general purpose/PWM
timers
• Two 2-ch quad decoder/general purpose timers
• Real-time clock
Human-machine interface
Operating Characteristics
• Low-power hardware touch sensor interface (TSI)
• General-purpose input/output
• Voltage/Flash write voltage range:1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C
© 2013–2015 Freescale Semiconductor, Inc. All rights reserved.
Ordering Information
Memory
Part Number
Maximum number of I\O's
Flash
SRAM
256 KB
256 KB
MK65FN2M0VMI18
MK65FX1M0VMI18
2 MB
116
116
1.25 MB
Related Resources
Type
Description
Resource
Selector
Guide
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Solution Advisor
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K65P169M180SF5RMV2-1
This document.
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
Chip Errata
The chip mask set Errata provides additional or corrective information for Kinetis_K_0N65N -1
a particular device mask set.
Package
drawing
Package dimensions are provided in package drawings.
MAPBGA 169-pin :
98ASA00628D-1
2
Kinetis K65 Sub-Family, Rev. 2, 05/2015
Freescale Semiconductor, Inc.
Kinetis K65 Sub-Family
ARM® Cortex®-M4
Core
System
Memories and Memory Interfaces
Clocks
Internal
and external
watchdogs
Program
flash
Phase-
locked loop
RAM
Debug
Memory
protection
Frequency-
locked loop
FlexMemory
DSP
Cache
interfaces
Serial
Low/high
frequency
oscillators
Interrupt
Floating-
point unit
External
bus
programming
DMA
controller
interface
Internal
reference
clocks
Low-leakage
wakeup
SDRAM
controller
Security
and Integrity
Communication Interfaces
Human-Machine
Interface (HMI)
Analog
Timers
I2C
x4
16-bit ADC
x2
I2S
x1
Timers
x4 (20ch)
CRC
GPIO
Xtrinsic
touch-sensing
interface
Random
number
generator
Carrier
modulator
transmitter
Analog
comparator
x4
UART
x5
Secure
Digital
Hardware
encryption
Programmable
delay block
SPI
x3
USB LS/FS
OTG
controller
with
6-bit DAC
x4
Periodic
interrupt
timers
CAN
x2
12-bit DAC
x2
transceiver
Voltage
reference
USB LS/FS/HS
OTG
controller
with
Low power
timer
IEEE 1588
Ethernet
Independent
real-time
clock
transceiver
LPUART
USB DCD/
USBHSDCD
IEEE 1588
Timers
USB voltage
regulator
Low power
TPM x 2 (4ch)
Figure 1. K65 Block Diagram
Kinetis K65 Sub-Family, Rev. 2, 05/2015
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Kinetis K65 Sub-Family, Rev. 2, 05/2015
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings..................................................................................6
3.8.1
3.8.2
Ethernet switching specifications.....................56
1.1 Thermal handling ratings............................................... 6
1.2 Moisture handling ratings...............................................6
1.3 ESD handling ratings..................................................... 6
1.4 Voltage and current operating ratings............................6
2 General................................................................................. 7
2.1 AC electrical characteristics...........................................7
2.2 Nonswitching electrical specifications............................8
USB Voltage Regulator Electrical
Specifications.................................................. 58
USB Full Speed Transceiver and High Speed
PHY specifications...........................................59
USB DCD electrical specifications...................60
CAN switching specifications...........................60
DSPI switching specifications (limited voltage
range).............................................................. 60
DSPI switching specifications (full voltage
3.8.3
3.8.4
3.8.5
3.8.6
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
Voltage and current operating requirements... 8
LVD and POR operating requirements............9
Voltage and current operating behaviors.........9
Power mode transition operating behaviors.... 11
Power consumption operating behaviors........ 12
EMC radiated emissions operating behaviors. 17
Designing with radiated emissions in mind......18
Capacitance attributes.....................................18
3.8.7
range).............................................................. 62
I2C switching specifications.............................63
UART switching specifications........................ 64
3.8.8
3.8.9
3.8.10 Low Power UART switching specifications......64
3.8.11 SDHC specifications........................................64
3.8.12 I2S switching specifications.............................65
3.9 Human-machine interfaces (HMI)..................................71
2.3 Switching specifications.................................................18
2.3.1
2.3.2
Device clock specifications..............................18
General switching specifications..................... 19
3.9.1
TSI electrical specifications............................. 71
4 Dimensions........................................................................... 72
4.1 Obtaining package dimensions......................................72
5 Pinout....................................................................................72
5.1 K65_169BGA Signal Multiplexing and Pin
2.4 Thermal specifications................................................... 20
2.4.1
2.4.2
Thermal operating requirements..................... 20
Thermal attributes............................................20
3 Peripheral operating requirements and behaviors................ 22
3.1 Core modules................................................................ 22
Assignments.................................................................. 72
5.2 Recommended connection for unused analog and
3.1.1
3.1.2
Debug trace timing specifications....................22
JTAG electricals.............................................. 23
digital pins......................................................................80
5.3 K65 Pinouts................................................................... 81
6 Ordering parts....................................................................... 82
6.1 Determining valid orderable parts..................................82
7 Part identification...................................................................83
7.1 Description.....................................................................83
7.2 Format........................................................................... 83
7.3 Fields............................................................................. 83
7.4 Example.........................................................................84
8 Terminology and guidelines.................................................. 84
8.1 Definition: Operating requirement..................................84
8.2 Definition: Operating behavior....................................... 85
8.3 Definition: Attribute........................................................ 85
8.4 Definition: Rating........................................................... 86
8.5 Result of exceeding a rating.......................................... 86
8.6 Relationship between ratings and operating
3.2 System modules............................................................ 26
3.3 Clock modules............................................................... 26
3.3.1
3.3.2
3.3.3
3.3.4
MCG specifications..........................................26
IRC48M specifications.....................................29
Oscillator electrical specifications....................30
32 kHz oscillator electrical characteristics....... 32
3.4 Memories and memory interfaces................................. 33
3.4.1
3.4.2
3.4.3
3.4.4
Flash (FTFE) electrical specifications..............33
EzPort switching specifications....................... 37
Flexbus switching specifications......................38
SDRAM controller specifications..................... 41
3.5 Security and integrity modules.......................................44
3.6 Analog............................................................................44
3.6.1
3.6.2
3.6.3
3.6.4
ADC electrical specifications........................... 44
CMP and 6-bit DAC electrical specifications... 49
12-bit DAC electrical characteristics................51
Voltage reference electrical specifications...... 54
requirements..................................................................86
8.7 Guidelines for ratings and operating requirements........87
8.8 Definition: Typical value.................................................87
8.9 Typical value conditions.................................................88
9 Revision History.................................................................... 89
3.7 Timers............................................................................55
3.8 Communication interfaces............................................. 55
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Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
VHBM
Description
Min.
-2000
-500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
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Freescale Semiconductor, Inc.
General
Symbol
VDD
Description
Min.
–0.3
—
Max.
3.8
Unit
Digital supply voltage
V
mA
V
IDD
Digital supply current
300
VDIO
Digital1 input voltage,including RESET_b
Analog1 input voltage, including EXTAL32 and XTAL32
Maximum current single pin limit (digital output pins)
Analog supply voltage
–0.3
–0.3
–25
VDD + 0.3
VDD + 0.3
25
VAIO
V
ID
mA
V
VDDA
VDD – 0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
VDD + 0.3
3.63
VUSB0_DP
VUSB1_DP
VUSB0_DM
VUSB1_DM
USB0_DP input voltage
V
USB1_DP input voltage
3.63
V
USB0_DM input voltage
3.63
V
USB1_DM input voltage
3.63
V
VUSB1_VBUS USB1_VBUS detect voltage
6.0
V
VREG_IN0, USB regulator input
VREG_IN1
6.0
V
VBAT
RTC battery supply voltage
–0.3
3.8
V
1. Digital pins have a general purpose I/O port assigned (e.g. PTA0). Analog pins do not have an associated general
purpose I/O port.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
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Freescale Semiconductor, Inc.
General
• are slew rate disabled, and
• are normal drive strength
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
1.71
–0.1
–0.1
1.71
Max.
3.6
3.6
0.1
0.1
3.6
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
V
V
VBAT
VIH
RTC battery supply voltage
Input high voltage
V
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.71 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.71 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICDIO
Input hysteresis
Digital1 input pin negative DC injection current —
single pin
0.06 × VDD
-5
—
—
V
2
2
mA
• VIN < VSS-0.3V
IICAIO
Analog1 input pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current injection)
mA
-5
—
—
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pin
-25
mA
• Negative current injection
VODPU
VRAM
Pseudo Open drain pullup voltage level
VDD voltage required to retain RAM
VDD
1.2
VDD
—
V
V
V
3
VRFVBAT VBAT voltage required to retain the VBAT register file
VPOR_VBAT
—
1. Digital pins have a general purpose I/O port assigned (e.g. PTA0). Analog pins do not have an associated general
purpose I/O port.
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Kinetis K65 Sub-Family, Rev. 2, 05/2015
Freescale Semiconductor, Inc.
General
2. All digital and analog I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VSS-0.3V, a current limiting resistor is required. The minimum negative DC
injection current limiting resistor value is calculated as R=(-0.3-VIN)/|IICDIO| or R=(-0.3-VIN)/|IICAIO|. The actual resistor
should be an order of magnitude higher to tolerate transient voltages.
3. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
80
—
mV
V
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
60
—
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR_VBAT Falling VBAT supply POR detect voltage
0.8
1.1
1.5
V
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General
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
VOH
Output high voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤VDD ≤ 2.7 V, IOH = -5mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
Output high voltage — High drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -20mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -10mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
IOHT
Output high current total for all ports
—
—
100
mA
V
VOH_RTC_WAKEUP Output high voltage— normal drive pad
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -5 mA
VBAT – 0.5
VBAT – 0.5
—
—
V
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -2.5
mA
IOH_RTC_WAKEUP Output high current total for
RTC_WAKEUP pins
—
—
100
mA
VOL
Output low voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 5 mA
—
—
—
—
0.5
0.5
V
V
Output low voltage — high drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
—
—
—
—
0.5
0.5
V
V
IOLT
Output low current total for all ports
—
—
100
mA
V
VOL_RTC_WAKEUP Output low voltage— normal drive pad
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 5 mA
—
—
0.5
0.5
V
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 2.5mA
IOL_RTC_WAKEUP Output low current total for
RTC_WAKEUPpins
—
—
—
100
0.5
mA
µA
IIN
Input leakage current, analog and digital
0.002
1
pins
• VSS ≤ VIN ≤ VDD
IOZ_RTC_WAKEUP Hi-Z (off-state) leakage current (per
RTC_WAKEUP pin)
—
20
20
—
—
—
0.25
50
µA
kΩ
kΩ
RPU
Internal pullup resistors(except
RTC_WAKEUP pins)
2
3
RPD
Internal pulldown resistors (except
RTC_WAKEUP pins)
50
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
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General
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx –> RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 100MHz
• Bus clock = 50MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode=FEI
Table 5. Power mode transition operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point
VDD reaches 1.71 V to execution of the first
instruction across the operating temperature range
of the chip.
—
300
µs
—
—
—
—
—
—
—
—
172
172
94
µs
µs
µs
µs
µs
µs
µs
µs
• VLLS0 –> RUN
• VLLS1 –> RUN
• VLLS2 –> RUN
• VLLS3 –> RUN
• LLS2 –> RUN
• LLS3 –> RUN
• VLPS –> RUN
• STOP –> RUN
94
5.8
5.8
5.4
5.4
Table 6. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
1
IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder.
Measured by entering STOP or VLPS mode
with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KH 32 kHz internal reference clock (IRC) adder.
52
52
52
52
52
52
µA
Measured by entering STOP mode with the
z
32 kHz IRC enabled.
Table continues on the next page...
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General
Table 6. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
1
IEREFSTEN4MH External 4 MHz crystal clock adder.
206
228
237
245
251
258
uA
Measured by entering STOP or VLPS mode
z
with the crystal enabled.
IEREFSTEN32K External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN and
Hz
EREFSTEN] bits. Measured by entering all
modes with the crystal enabled.
nA
440
440
490
490
510
510
511
22
490
490
490
490
560
560
520
22
540
540
540
540
560
560
545
22
560
560
560
560
560
560
556
22
570
570
570
570
610
610
563
22
580
580
680
680
680
680
576
22
VLLS1
VLLS3
LLS2
LLS3
VLPS
STOP
I48MIRC
ICMP
48MHz IRC
µA
µA
CMP peripheral adder measured by placing
the device in VLLS1 mode with CMP
enabled using the 6-bit DAC and a single
external input for compare. Includes 6-bit
DAC power consumption.
IRTC
RTC peripheral adder measured by placing
the device in VLLS1 mode with external 32
kHz crystal enabled by means of the
RTC_CR[OSCE] bit and the RTC ALARM
set for 1 minute. Includes ERCLK32K (32
kHz external crystal) power consumption.
432
357
388
475
532
810
nA
µA
IUART
UART peripheral adder measured by placing
the device in STOP or VLPS mode with
selected clock source waiting for RX data at
115200 baud rate. Includes selected clock
source power consumption.
66
66
66
66
66
66
MCGIRCLK (4 MHz internal reference clock)
OSCERCLK (4 MHz external crystal)
214
45
234
45
246
45
254
45
260
45
268
45
IBG
Bandgap adder when BGEN bit is set and
device is placed in VLPx, LLS, or VLLSx
mode.
µA
µA
IADC
ADC peripheral adder combining the
366
366
366
366
366
366
measured values at VDD and VDDA by placing
the device in STOP or VLPS mode. ADC is
configured for low power mode using the
internal clock and continuous conversions.
1. Applicable to LQFP and BGA packages only
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General
2.2.5 Power consumption operating behaviors
NOTE
The maximum values represent characterized results
equivalent to the mean plus three times the standard
deviation (mean + 3 sigma)
Table 7. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
2
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
—
—
32.3
32.4
71.03
71.81
mA
mA
• @ 1.8V
• @ 3.0V
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
3, 4
—
50.5
89.58
mA
• @ 1.8V
• @ 3.0V
—
—
50.6
69.7
55.95
99.85
mA
mA
• @ 25°C
• @ 105°C
IDD_RUNC Run mode current in compute operation - 120
5
6
—
28.5
67.74
mA
MHz core / 24 MHz flash / bus clock disabled,
O
code of while(1) loop executing from flash
• at 3.0 V
IDD_HSRU Run mode current — all peripheral clocks
disabled, code executing from flash
N
—
—
47.2
47.3
91.25
91.62
mA
mA
• @ 1.8V
• @ 3.0V
IDD_HSRU Run mode current — all peripheral clocks
7, -1
enabled, code executing from flash
N
—
71.4
103.58
mA
• @ 1.8V
• @ 3.0V
71.5
93.3
79.13
mA
mA
—
—
• @ 25°C
• @ 105°C
115.08
IDD_HSRU HSRun mode current in compute operation –
—
42.9
91.97
mA
5
168 MHz core/ 28 MHz flash / bus clock
NCO
disabled, code of while(1) loop executing from
flash at 3.0V
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
—
16.9
35
45.2
mA
mA
8
8
IDD_WAIT Wait mode reduced frequency current at 3.0 V
— all peripheral clocks enabled
62.81
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Table 7. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
1.1
9.56
mA
9
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
—
2
9.88
9.47
mA
μA
10
11
IDD_VLPRC Very-low-power run mode current in compute
986
operation - 4 MHz core / 1 MHz flash / bus clock
O
disabled, LPTMR running with 4 MHz internal
reference clock
• at 3.0 V
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
—
—
0.690
1.5
9.25
mA
mA
12
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks enabled
10.00
IDD_STOP Stop mode current at 3.0 V
—
—
—
0.791
3.8
2.39
6.91
mA
mA
mA
• @ –40 to 25°C
• @ 70°C
13.2
18.91
• @ 105°C
IDD_VLPS Very-low-power stop mode current at 3.0 V
—
—
—
202
1400
5100
353.77
2464.54
8949.06
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_LLS3 Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
—
—
—
9.0
76.3
402
13.05
88.63
μA
μA
μA
• @ 70°C
• @ 105°C
656.08
IDD_LLS2 Low leakage stop mode current at 3.0 V
—
5.7
32.2
μA
μA
• @ –40 to 25°C
• @ 70°C
—
—
41.3
229
55.80
• @ 105°C
276.81
μA
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
—
—
—
5.5
46.3
249
7.31
58.33
380.77
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
—
—
—
2.7
3.24
18.72
84.77
μA
μA
μA
• @ –40 to 25°C
13.1
76.6
• @ 70°C
• @ 105°C
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
Table continues on the next page...
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General
Notes
Table 7. Power consumption operating behaviors (continued)
Symbol Description
• @ –40 to 25°C
Min.
Typ.
Max.
Unit
—
0.847
1.48
μA
• @ 70°C
—
—
6.5
11.31
81.78
μA
μA
• @ 105°C
46.7
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
—
—
—
0.551
6.3
.65
7.12
53.68
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
49.6
• @ 105°C
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
—
—
—
0.254
6.3
0.445
10.99
85.27
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
48.7
• @ 105°C
IDD_VBAT Average current with RTC and 32kHz disabled
at 3.0 V
—
—
—
0.19
0.49
2.2
0.22
0.64
3.2
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VBAT Average current when CPU is not accessing
RTC registers
13
• @ 1.8V
0.68
1.2
—
—
—
0.8
1.56
5.3
• @ –40 to 25°C
• @ 70°C
μA
μA
μA
3.6
• @ 105°C
• @ 3.0V
• @ –40 to 25°C
• @ 70°C
0.81
1.45
4.3
—
—
—
0.96
1.89
6.33
μA
μA
μA
• @ 105°C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. MCG configured for PEE mode.
6. 168 MHz core and system clock, 56 MHz bus and FlexBus clock, and 28 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
7. 168 MHz core and system clock, 56 MHz bus and FlexBus clock, and 28 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled.
8. 120 MHz core and system clock, 60MHz bus clock, and FlexBus. MCG configured for PEE mode.
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General
9. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled. Code executing from flash.
10. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
11. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized
for balanced.
12. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled.
13. Includes 32kHz oscillator current and RTC operation.
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE
Figure 3. Run mode supply current vs. core frequency
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General
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 8. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band
Typ.
Unit
Notes
(MHz)
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
23
27
28
14
K
dBμV
dBμV
dBμV
dBμV
—
1, 2
VRE3
150–500
500–1000
0.15–1000
VRE4
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,
150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits -
Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM
Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic
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General
application code. The reported emission level is the value of the maximum measured emission, rounded up to the next
whole number, from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = MHz, fBUS = MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
pF
Input capacitance: analog pins
Input capacitance: digital pins
7
7
CIN_D
—
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 10. Device clock specifications
Symbol
fSYS
Description
Min.
Max.
Unit
Notes
High Speed run mode
System and core clock
—
180
MHz
Normal run mode (and High Speed run mode unless otherwise specified above)
fSYS
System and core clock
—
120
—
MHz
MHz
System and core clock when Full Speed USB in
operation
20
fSYS_USBHS System and core clock when High Speed USB in
operation
100
—
MHz
MHz
fENET
System and core clock when ethernet in operation
• 10 Mbps
• 100 Mbps
5
—
—
50
Table continues on the next page...
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General
Notes
Table 10. Device clock specifications (continued)
Symbol
fBUS
Description
Bus clock
Min.
—
Max.
60
Unit
MHz
MHz
MHz
MHz
FB_CLK
fFLASH
FlexBus clock
Flash clock
LPTMR clock
—
60
—
28
fLPTMR
—
25
VLPR mode1
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
—
—
—
—
—
4
4
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
FB_CLK
fFLASH
FlexBus clock
4
Flash clock
1
fERCLK
fLPTMR_pin
External reference clock
LPTMR clock
16
25
8
fFlexCAN_ERCLK FlexCAN external reference clock
fI2S_MCLK
fI2S_BCLK
I2S master clock
I2S bit clock
12.5
4
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, IEEE 1588 timer, timers, and I2C signals.
Table 11. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous
path
100
50
—
—
ns
ns
ns
3
3
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous
path
External reset pulse width (digital glitch filter
disabled)
100
2
—
—
Mode select (EZP_CS) hold time after reset
deassertion
Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew enabled
4
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General
Table 11. General switching specifications (continued)
Symbol
Description
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew disabled
Min.
Max.
Unit
Notes
—
25
ns
—
15
ns
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
7
7
ns
ns
Port rise and fall time (low drive strength)
• Slew enabled
5
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
25
15
ns
ns
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
7
7
ns
ns
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may
or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can
be recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
VLLSx modes.
4. 75 pF load
5. 15 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Notes
Die junction temperature
Ambient temperature
TA
105
°C
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ= = TA + θJA x chip power dissipation.
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General
2.4.2 Thermal attributes
Board type
Symbol
Description
169 MAPBGA
Unit
Notes
Single-layer (1s)
RθJA
Thermal
resistance,
junction to
ambient (natural
convection)
38
°C/W
°C/W
°C/W
°C/W
1
1
1
1
Four-layer (2s2p) RθJA
Thermal
resistance,
junction to
ambient (natural
convection)
21.9
30
Single-layer (1s)
RθJMA
Thermal
resistance,
junction to
ambient (200 ft./
min. air speed)
Four-layer (2s2p) RθJMA
Thermal
18.6
resistance,
junction to
ambient (200 ft./
min. air speed)
—
—
—
RθJB
RθJC
ΨJT
Thermal
resistance,
junction to board
14.4
8.2
°C/W
°C/W
°C/W
2
3
4
Thermal
resistance,
junction to case
Thermal
0.2
characterization
parameter,
junction to
package top
outside center
(natural
convection)
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
NOTES:
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits
Thermal Test Method Environmental Conditions—Natural Convection (Still Air)
with the single layer board horizontal. Board meets JESD51-9 specification.
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Peripheral operating requirements and behaviors
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal
Test Method Environmental Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard,
Microcircuits, with the cold plate temperature used for the case temperature. The
value includes the thermal resistance of the interface material between the top of
the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal
Test Method Environmental Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 Debug trace timing specifications
Table 13. Debug trace operating behaviors
Symbol
Tcyc
Twl
Description
Min.
Max.
Unit
MHz
ns
Clock period
Frequency dependent
Low pulse width
High pulse width
Clock and data rise time
Clock and data fall time
Data setup
2
2
—
—
3
Twh
Tr
ns
—
—
1.5
1.0
ns
Tf
3
ns
Ts
—
—
ns
Th
Data hold
ns
TRACECLK
T
r
T
f
T
wh
T
wl
T
cyc
Figure 5. TRACE_CLKOUT specifications
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Peripheral operating requirements and behaviors
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 6. Trace data specifications
3.1.2 JTAG electricals
Table 14. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
25
50
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
20
10
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
J4
J5
TCLK rise and fall times
—
20
2.0
—
—
8
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
—
—
28
25
—
—
19
17
—
—
J6
J7
J8
J9
J10
J11
J12
J13
J14
1
—
—
100
8
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
Table 15. JTAG full voltage range electricals
Symbol
Description
Operating voltage
Min.
Max.
Unit
1.71
3.6
V
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Peripheral operating requirements and behaviors
Table 15. JTAG full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
20
40
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
25
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
12.5
J4
J5
TCLK rise and fall times
—
20
2.0
—
—
8
3
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
J6
—
J7
30.6
25
J8
J9
—
J10
J11
J12
J13
J14
1.0
—
—
100
8
—
19.0
17.0
—
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
—
J2
J4
J3
J3
TCLK (input)
J4
Figure 7. Test clock input timing
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Peripheral operating requirements and behaviors
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 8. Boundary scan (JTAG) timing
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 9. Test Access Port timing
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Peripheral operating requirements and behaviors
TCLK
J14
J13
TRST
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 16. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
fints_t
Iints
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
Internal reference (slow clock) current
—
—
20
—
µA
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.3
0.6
%fdco
1
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
0.2
0.5
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
0.5
0.3
2
%fdco
%fdco
1
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
1.5
fintf_ft
fintf_t
Iintf
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
3
4
—
5
MHz
MHz
µA
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
—
25
Internal reference (fast clock) current
—
—
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Peripheral operating requirements and behaviors
Table 16. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
floc_low Loss of external clock minimum frequency —
(3/5) x
fints_t
—
—
kHz
RANGE = 00
ext clk freq: above (3/5)fint never reset
ext clk freq: between (2/5)fint and (3/5)fint maybe
reset (phase dependency)
ext clk freq: below (2/5)fint always reset
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
ext clk freq: above (16/5)fint never reset
ext clk freq: between (15/5)fint and (16/5)fint
maybe reset (phase dependency)
ext clk freq: below (15/5)fint always reset
FLL
ffll_ref
FLL reference frequency range
31.25
16.0
—
39.0625
26.66
kHz
fdco_ut
DCO output
Low range
23.04
MHz
2
frequency range
— untrimmed
(DRS=00, DMX32=0)
640 × fints_ut
Mid range
32.0
48.0
46.08
69.12
92.16
26.35
52.70
79.09
105.44
53.32
79.99
106.65
30.50
60.99
91.53
122.02
(DRS=01, DMX32=0)
1280 × fints_ut
Mid-high range
(DRS=10, DMX32=0)
1920 × fints_ut
High range
64.0
(DRS=11, DMX32=0)
2560 × fints_ut
Low range
18.3
(DRS=00, DMX32=1)
732 × fints_ut
Mid range
36.6
(DRS=01, DMX32=1)
1464 × fints_ut
Mid-high range
(DRS=10, DMX32=1)
2197 × fints_ut
54.93
73.23
High range
(DRS=11, DMX32=1)
2929 × fints_ut
Table continues on the next page...
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 16. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fdco
DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20
20.97
25
MHz
3, 4
Mid range (DRS=01)
1280 × ffll_ref
40
60
80
—
—
—
—
41.94
62.91
83.89
23.99
47.97
71.99
95.98
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
Low range (DRS=00)
732 × ffll_ref
5, 6
frequency
2
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Jcyc_fll
FLL period jitter
—
—
180
150
—
—
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
7
PLL
fpll_ref
PLL reference frequency range
8
180
90
90
—
—
—
16
360
180
180
—
MHz
MHz
fvcoclk_2x VCO output frequency
fvcoclk
PLL output frequency
—
—
MHz
MHz
fvcoclk_90 PLL quadrature output frequency
Ipll
PLL operating current
8
8
9
2.8
3.6
mA
mA
• VCO @ 176 MHz (fosc_hi_1 = 32 MHz,
fpll_ref = 8 MHz, VDIV multiplier = 22)
Ipll
PLL operating current
—
—
• VCO @ 360 MHz (fosc_hi_1 = 32 MHz,
fpll_ref = 8 MHz, VDIV multiplier = 45)
Jcyc_pll
PLL period jitter (RMS)
• fvco = 180 MHz
—
—
100
75
—
—
ps
ps
• fvco = 360 MHz
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
• fvco = 180 MHz
9
—
—
600
300
—
—
ps
ps
• fvco = 360 MHz
Table continues on the next page...
28
Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors
Table 16. MCG specifications (continued)
Symbol Description
Min.
4.47
—
Typ.
—
Max.
Unit
%
Notes
Dunl
Lock exit frequency tolerance
Lock detector detection time
5.97
150 × 10-6
+ 1075(1/
tpll_lock
—
s
10
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. This applies when SCTRIM at value (0x80) and SCFTRIM control bit at value (0x0).
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics
of each PCB and results will vary.
10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
3.3.2 IRC48M specifications
Table 17. IRC48M specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
—
Unit
V
Notes
Supply voltage
IDD48M
firc48m
Supply current
520
48
μA
Internal reference frequency
—
—
MHz
Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at
low voltage (VDD=1.71V-1.89V) over temperature
• Regulator disable
—
—
0.5
0.5
1.0
1.5
%firc48m
(USB_CLK_RECOVER_IRC_EN[REG_EN]=0)
• Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over temperature
• Regulator enable
—
—
0.5
—
1.0
0.1
%firc48m
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Δfirc48m_cl Closed loop total deviation of IRC48M frequency
%fhost
1
2
over voltage and temperature
Jcyc_irc48m Period Jitter (RMS)
—
—
35
2
150
3
ps
μs
tirc48mst
Startup time
1. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation.
It is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover
Kinetis K65 Sub-Family, Rev. 2, 05/2015
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1,
USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).
2. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the
clock by one of the following settings:
• USB_CLK_RECOVER_IRC_EN[IRC_EN]=1, or
• MCG_C7[OSCSEL]=10, or
• SIM_SOPT2[PLLFLLSEL]=11
3.3.3 Oscillator electrical specifications
3.3.3.1 Oscillator DC electrical specifications
Table 18. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
600
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
7.5
500
650
2.5
3.25
4
—
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
10
—
1
—
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Table continues on the next page...
30
Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors
Table 18. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Series resistor — low-frequency, high-gain
—
200
—
kΩ
mode (HGO=1)
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C, Internal capacitance = 20 pf
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.3.2 Oscillator frequency specifications
Table 19. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
fosc_hi_1 Oscillator crystal or resonator frequency —
high-frequency mode (low range)
3
8
—
—
8
MHz
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency —
high frequency mode (high range)
(MCG_C2[RANGE]=1x)
32
fec_extal Input clock frequency (external clock mode)
tdc_extal Input clock duty cycle (external clock mode)
—
40
—
—
50
50
60
—
MHz
%
1, 2
3, 4
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 19. Oscillator frequency specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Crystal startup time — 8 MHz high-frequency
—
0.6
—
ms
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
3.3.4 32 kHz oscillator electrical characteristics
3.3.4.1 32 kHz oscillator DC electrical specifications
Table 20. 32kHz oscillator DC electrical specifications
Symbol
VBAT
RF
Description
Min.
1.71
—
Typ.
—
Max.
3.6
—
Unit
V
Supply voltage
Internal feedback resistor
100
5
MΩ
pF
Cpara
Parasitical capacitance of EXTAL32 and
XTAL32
—
7
1
Vpp
Peak-to-peak amplitude of oscillation
—
0.6
—
V
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
3.3.4.2 32 kHz oscillator frequency specifications
Table 21. 32 kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32.768
1000
32.768
—
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
—
1
2
fec_extal32 Externally provided input clock frequency
vec_extal32 Externally provided input clock amplitude
—
—
kHz
mV
700
VBAT
2, 3
32
Freescale Semiconductor, Inc.
Kinetis K65 Sub-Family, Rev. 2, 05/2015
Peripheral operating requirements and behaviors
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
The oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VBAT
.
3.4 Memories and memory interfaces
3.4.1 Flash (FTFE) electrical specifications
This section describes the electrical characteristics of the FTFE module.
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 22. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
Max.
18
Unit
μs
Notes
thvpgm8 Program Phrase high-voltage time
thversscr Erase Flash Sector high-voltage time
thversblk256k Erase Flash Block high-voltage time for 256 KB
thversblk512k Erase Flash Block high-voltage time for 512 KB
—
13
113
ms
ms
ms
1
1
1
—
208
416
1808
3616
—
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 23. Flash command timing specifications
Symbol Description
Read 1s Block execution time
Min.
Typ.
Max.
Unit
Notes
trd1blk256k
trd1blk512k
• 256 KB data flash
—
—
—
—
1.0
1.8
ms
ms
• 512 KB program flash
trd1sec4k Read 1s Section execution time (4 KB flash)
tpgmchk Program Check execution time
—
—
—
—
—
—
—
90
100
95
μs
μs
μs
μs
1
1
1
trdrsrc
tpgm8
Read Resource execution time
Program Phrase execution time
Erase Flash Block execution time
40
150
2
tersblk256k
—
220
1850
ms
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 23. Flash command timing specifications (continued)
Symbol Description
tersblk512k • 256 KB data flash
Min.
Typ.
Max.
Unit
Notes
—
435
3700
ms
• 512 KB program flash
tersscr
Erase Flash Sector execution time
—
—
15
5
115
—
ms
ms
2
tpgmsec1k Program Section execution time (1KB flash)
Read 1s All Blocks execution time
trd1allx
trd1alln
• FlexNVM devices
—
—
—
—
5.9
6.7
ms
ms
• Program flash only devices
trdonce
Read Once execution time
—
—
—
—
—
90
30
—
μs
μs
ms
μs
1
tpgmonce Program Once execution time
tersall
Erase All Blocks execution time
Verify Backdoor Access Key execution time
Swap Control execution time
• control code 0x01
1750
—
14,800
30
2
1
tvfykey
tswapx01
tswapx02
tswapx04
tswapx08
tswapx10
—
—
—
—
—
200
90
90
—
—
μs
μs
μs
μs
μs
• control code 0x02
150
150
30
• control code 0x04
• control code 0x08
• control code 0x10
90
150
Program Partition for EEPROM execution time
• 32 KB EEPROM backup
tpgmpart32k
tpgmpart256k
—
—
70
78
—
—
ms
ms
• 256 KB EEPROM backup
Set FlexRAM Function execution time:
• Control Code 0xFF
tsetramff
tsetram32k
tsetram64k
tsetram128k
tsetram256k
—
—
—
—
—
70
0.8
1.3
2.4
4.5
—
μs
ms
ms
ms
ms
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
1.2
1.9
3.1
5.5
teewr8bers Byte-write to erased FlexRAM location
execution time
—
175
275
μs
3
Byte-write to FlexRAM execution time:
teewr8b32k
teewr8b64k
teewr8b128k
teewr8b256k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
—
385
475
1700
2000
2350
3250
μs
μs
μs
μs
650
1000
teewr16bers 16-bit write to erased FlexRAM location
execution time
—
175
275
μs
16-bit write to FlexRAM execution time:
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 23. Flash command timing specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
teewr16b32k
teewr16b64k
teewr16b128k
teewr16b256k
• 32 KB EEPROM backup
—
385
1700
μs
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
475
650
2000
2350
3250
μs
μs
μs
1000
teewr32bers 32-bit write to erased FlexRAM location
execution time
—
360
550
μs
32-bit write to FlexRAM execution time:
teewr32b32k
teewr32b64k
teewr32b128k
teewr32b256k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
—
—
—
630
810
2000
2250
2650
3500
μs
μs
μs
μs
1200
1900
1. Assumes 25MHz or greater flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
3.4.1.3 Flash high voltage current behaviors
Table 24. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current
adder during high
voltage flash
programming
operation
—
3.5
7.5
mA
IDD_ERS
Average current
adder during high
voltage flash erase
operation
—
1.5
4.0
mA
3.4.1.4 Reliability specifications
Table 25. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
10 K
2
Data Flash
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 25. NVM reliability specifications (continued)
Symbol Description
Min.
Typ.1
Max.
—
Unit
years
years
cycles
Notes
tnvmretd10k Data retention after up to 10 K cycles
tnvmretd1k Data retention after up to 1 K cycles
nnvmcycd Cycling endurance
5
50
20
10 K
100
50 K
—
—
2
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
tnvmretee10 Data retention up to 10% of write endurance
nnvmcycee Cycling endurance for EEPROM backup
Write endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
20 K
2
3
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree2k
nnvmwree8k
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 2,048
• EEPROM backup to FlexRAM ratio = 8,192
70 K
630 K
2.5 M
10 M
40 M
175 K
1.6 M
6.4 M
25 M
—
—
—
—
—
writes
writes
writes
writes
writes
100 M
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the
cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem.
Minimum and typical values assume all byte-writes to FlexRAM.
3.4.1.5 Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set
size can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the
FTFE to obtain an effective endurance increase for the EEPROM data. The built-in
EEPROM record management system raises the number of program/erase cycles that
can be attained prior to device wear-out by cycling the EEPROM data through a larger
EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout
the entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
EEPROM – 2 × EEESPLIT × EEESIZE
Writes_subsystem =
× Write_efficiency × nnvmcycee
36
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Peripheral operating requirements and behaviors
where
• Writes_subsystem — minimum number of writes to each FlexRAM location for
subsystem (each subsystem can have different endurance)
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on
DEPART; entered with the Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program
Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program
Partition command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycee — EEPROM-backup cycling endurance
Figure 11. EEPROM backup writes to FlexRAM
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.4.2 EzPort switching specifications
Table 26. EzPort full voltage range switching specifications
Num
Description
Min.
1.71
—
Max.
3.6
Unit
V
Operating voltage
EP1
EZP_CK frequency of operation (all commands except
READ)
fSYS/2
MHz
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid
—
fSYS/8
—
MHz
ns
2 x tEZP_CK
5
5
—
ns
—
ns
2
—
ns
5
—
ns
—
0
14
—
ns
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
ns
—
12
ns
EZP_CK
EP2
EP3
EP4
EZP_CS
EP9
EP8
EP7
EZP_Q (output)
EZP_D (input)
EP5
EP6
Figure 12. EzPort Timing Diagram
3.4.3 Flexbus switching specifications
All processor bus timings are synchronous; input setup/hold and output delay are given
in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency
may be the same as the internal system bus frequency or an integer divider of that
frequency.
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Peripheral operating requirements and behaviors
The following timing numbers indicate when data is latched or driven onto the
external bus, relative to the Flexbus output clock (FB_CLK). All other timing
relationships can be derived from these values.
Table 27. Flexbus limited voltage range switching specifications
Num
Description
Min.
2.7
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
—
FB_CLK
—
MHz
ns
FB1
FB2
FB3
FB4
FB5
1/FB_CLK
—
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
11.8
—
ns
1.0
ns
1
2
11.9
0.0
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],
FB_ALE, and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 28. Flexbus full voltage range switching specifications
Num
Description
Min.
1.71
—
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
FB_CLK
—
MHz
ns
FB1
FB2
FB3
FB4
FB5
1/FB_CLK
—
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
12.6
—
ns
1.0
ns
1
2
12.5
0
—
ns
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],
FB_ALE, and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB3
FB5
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
Address
FB4
FB2
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 13. FlexBus read timing diagram
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Freescale Semiconductor, Inc.
Kinetis K65 Sub-Family, Rev. 2, 05/2015
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB2
FB3
Address
Address
Data
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 14. FlexBus write timing diagram
3.4.4 SDRAM controller specifications
Following figure shows SDRAM read cycle.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
0
1
2
3
4
5
6
7
8
9
10
11
12
13
D0
CLKOUT
D3
D1
Row
Column
A[23:0]
D4
SRAS
SCAS
D2
1
D4
DRAMW
D[31:0]
D5
D6
D4
SDRAM_CS[1:0]
BS[3:0]
NOP
ACTV
NOP
READ
PRE
1
DACR[CASL] = 2
Figure 15. SDRAM read timing diagram
Table 29. SDRAM Timing (Full voltage range)
NUM
Characteristic 1
Symbol
1.71
MIn
Max
Unit
Operating voltage
3.6
V
Frequency of operation
—
CLKOUT
MHz
D0
D1
D2
D3
D4
D5
D6
D73
D83
Clock period
1/CLKOUT
tCHDAV
tCHDCV
tCHDAI
—
-
ns
2
CLKOUT high to SDRAM address valid
CLKOUT high to SDRAM control valid
CLKOUT high to SDRAM address invalid
CLKOUT high to SDRAM control invalid
SDRAM data valid to CLKOUT high
CLKOUT high to SDRAM data invalid
CLKOUT high to SDRAM data valid
CLKOUT high to SDRAM data invalid
11.2
ns
ns
ns
ns
ns
ns
ns
ns
11.1
1.0
1.0
12.0
1.0
-
-
tCHDCI
-
tDDVCH
tCHDDI
tCHDDVW
tCHDDIW
-
-
12.0
-
1.0
1. All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
2. CLKOUT is same as FB_CLK, maximum frequency can be 60 MHz
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Peripheral operating requirements and behaviors
3. D7 and D8 are for write cycles only.
Table 30. SDRAM Timing (Limited voltage range)
NUM
Characteristic -1
Symbol
2.7
MIn
3.6
Max
Unit
Operating voltage
V
Frequency of operation
—
1/CLKOUT
tCHDAV
tCHDCV
tCHDAI
CLKOUT
MHz
D0
D1
Clock period
—
-
ns
-1
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT high to SDRAM address valid
CLKOUT high to SDRAM control valid
CLKOUT high to SDRAM address invalid
CLKOUT high to SDRAM control invalid
SDRAM data valid to CLKOUT high
CLKOUT high to SDRAM data invalid
CLKOUT high to SDRAM data valid
CLKOUT high to SDRAM data invalid
11.1
D2
11.1
D3
1.0
1.0
11.3
1.0
-
-
D4
tCHDCI
-
D5
tDDVCH
tCHDDI
tCHDDVW
tCHDDIW
-
D6
-
11.1
-
D7-1
D8-1
1.0
Following figure shows an SDRAM write cycle.
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Peripheral operating requirements and behaviors
0
1
2
3
4
5
6
7
8
9
10
11
12
D0
CLKOUT
D3
D1
Row
Column
A[23:0]
SRAS
D2
1
SCAS
D4
DRAMW
D[31:0]
D7
D8
D4
SDRAM_CS[1:0]
D4
D2
BS[3:0]
D4
ACTV
NOP
WRITE
NOP
PALL
1
DACR[CASL] = 2
Figure 16. SDRAM write timing diagram
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 1 and Table 32 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
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Peripheral operating requirements and behaviors
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
3.6.1.1 16-bit ADC operating conditions
Table 31. 16-bit ADC operating conditions
Symbol Description
VDDA Supply voltage
ΔVDDA Supply voltage
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
Absolute
—
—
2
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
ΔVSSA
Ground voltage Delta to VSS (VSS – VSSA
)
0
2
VREFH
ADC reference
voltage high
VDDA
VREFL
VADIN
ADC reference
voltage low
VSSA
VSSA
VSSA
V
V
Input voltage
• 16-bit differential mode
• All other modes
• 16-bit mode
VREFL
VREFL
—
—
31/32 *
VREFH
—
—
VREFH
CADIN
Input
capacitance
—
—
8
4
10
5
pF
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input series
resistance
—
—
2
5
5
kΩ
kΩ
—
3
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
fADCK
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
2.0
—
—
24
MHz
MHz
4
4
5
ADC conversion 16-bit mode
clock frequency
12.0
ADC conversion ≤ 13-bit modes
rate
20.000
—
1200
Kbps
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
5
37.037
—
461.467
Kbps
rate
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 17. ADC input impedance equivalency diagram
3.6.1.2 16-bit ADC electrical characteristics
Table 32. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
mA
Notes
IDDA_ADC Supply current
—
3
ADC
asynchronous
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
4.0
5.2
6.2
MHz
MHz
MHz
MHz
tADACK =
1/fADACK
2.4
clock source
fADACK
3.0
4.4
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total
unadjusted error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
0.7
0.2
–1.1 to
+1.9
–0.3 to 0.5
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 32. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
INL
Integral non-
linearity
• 12-bit modes
—
1.0
–2.7 to
+1.9
LSB4
5
• <12-bit modes
—
0.5
–0.7 to
+0.5
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
—
—
—
–4
–1.4
–1 to 0
—
–5.4
–1.8
—
LSB4
LSB4
VADIN
VDDA
=
5
Quantization
error
0.5
ENOB Effective
number of bits
16-bit differential mode
• Avg = 32
6
bits
bits
12.8
11.9
14.5
13.8
• Avg = 4
—
—
bits
bits
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.9
13.1
—
—
• Avg = 4
Signal-to-noise See ENOB
plus distortion
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic 16-bit differential mode
7
7
dB
dB
distortion
—
—
-94
-85
—
—
• Avg = 32
16-bit single-ended mode
• Avg = 32
SFDR
Spurious free
dynamic range
16-bit differential mode
• Avg = 32
—
—
dB
dB
82
78
95
90
16-bit single-ended mode
• Avg = 32
EIL
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
Across the full temperature range
of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
8
VTEMP25 Temp sensor
voltage
25 °C
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Peripheral operating requirements and behaviors
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
12.30
12.00
Averaging of 8 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 18. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
12.75
12.50
12.25
12.00
11.75
11.50
11.25
Averaging of 4 samples
Averaging of 32 samples
11.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 19. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
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Peripheral operating requirements and behaviors
3.6.2 CMP and 6-bit DAC electrical specifications
Table 33. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
VDD – 0.5
—
—
—
50
250
—
7
—
0.5
200
600
40
V
V
Output low
Propagation delay, high-speed mode (EN=1, PMODE=1)
Propagation delay, low-speed mode (EN=1, PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
20
ns
tDLS
80
ns
—
μs
IDAC6b
INL
—
—
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
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Peripheral operating requirements and behaviors
0.08
0.07
0.06
0.05
0.04
0.03
HYSTCTR
Setting
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 20. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 21. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
3.6.3.1 12-bit DAC operating requirements
Table 34. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
CL
Desciption
Min.
Max.
3.6
3.6
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Output load capacitance
Output load current
1.13
—
V
1
2
pF
mA
IL
—
1. The DAC reference can be selected to be VDDA or VREFH
.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
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Peripheral operating requirements and behaviors
3.6.3.2 12-bit DAC operating behaviors
Table 35. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
150
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
100
15
700
200
30
μA
μs
μs
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-speed
mode
0.7
1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
—
—
—
—
—
—
100
mV
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
VDACR
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR > 2
V
Differential non-linearity error — VDACR
VREF_OUT
=
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
AC
Temperature coefficient offset voltage
Temperature coefficient gain error
Offset aging coefficient
3.7
—
μV/C
%FSR/C
μV/yr
Ω
6
0.000421
—
—
100
250
Rop
SR
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
—
V/μs
• High power (SPHP
• Low power (SPLP
)
1.2
1.7
—
—
)
0.05
0.12
CT
Channel to channel cross talk
3dB bandwidth
—
—
-80
dB
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
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Peripheral operating requirements and behaviors
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC
set to 0x800, temperature range is across the full range of the device
8
6
4
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 22. Typical INL error vs. digital code
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
85
25
105
125
-40
Temperature °C
Figure 23. Offset at half scale vs. temperature
3.6.4 Voltage reference electrical specifications
Table 36. VREF full-range operating requirements
Symbol
VDDA
TA
Description
Supply voltage
Temperature
Min.
Max.
Unit
Notes
—
3.6
V
Operating temperature
range of the device
°C
—
CL
Output load capacitance
100
nF
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range
of the device.
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Peripheral operating requirements and behaviors
Table 37. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.1915
1.195
1.1977
V
1
nominal VDDA and temperature=25C
Voltage reference output — factory trim
Voltage reference output — user trim
Voltage reference trim step
Vout
Vout
1.1584
1.193
—
—
—
1.2376
1.197
—
V
V
1
1
1
1
Vstep
Vtdrift
0.5
—
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range)
—
80
Ac
Ibg
Aging coefficient
—
—
—
—
400
80
uV/yr
µA
—
1
Bandgap only current
ΔVLOAD Load regulation
• current = 1.0 mA
µV
1, 2
—
200
—
Tstup
Buffer startup time
—
—
—
—
100
35
µs
—
—
Tchop_osc_st Internal bandgap start-up delay with chop
ms
oscillator enabled
up
Vvdrift
Voltage drift (Vmax -Vmin across the full
voltage range)
—
2
—
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 38. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
50
°C
—
Table 39. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim
1.173
1.225
V
—
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
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3.8.1 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
3.8.1.1 MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Table 40. MII signal switching specifications
Symbol
—
Description
Min.
2.7
Max.
3.6
Unit
V
Operating Voltage
RXCLK frequency
RXCLK pulse width high
—
—
25
MHz
RXCLK
period
RXCLK
period
ns
MII1
35%
65%
MII2
RXCLK pulse width low
35%
65%
MII3
MII4
—
RXD[3:0], RXDV, RXER to RXCLK setup
RXCLK to RXD[3:0], RXDV, RXER hold
TXCLK frequency
5
5
—
—
ns
—
25
MHz
TXCLK
period
TXCLK
period
ns
MII5
TXCLK pulse width high
35%
65%
MII6
TXCLK pulse width low
35%
65%
MII7
MII8
TXCLK to TXD[3:0], TXEN, TXER invalid
TXCLK to TXD[3:0], TXEN, TXER valid
2
—
—
25
ns
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Peripheral operating requirements and behaviors
MII6
MII5
TXCLK (input)
TXD[n:0]
TXEN
MII8
MII7
Valid data
Valid data
Valid data
TXER
Figure 24. RMII/MII transmit signal timing diagram
MII2
MII1
RXCLK (input)
RXD[n:0]
RXDV
MII3
MII4
Valid data
Valid data
Valid data
RXER
Figure 25. RMII/MII receive signal timing diagram
3.8.1.2 RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a
range of transceiver devices.
Table 41. RMII signal switching specifications
Num
—
Description
Min.
2.7
Max.
3.6
Unit
Operating Voltage
—
EXTAL frequency (RMII input clock RMII_CLK)
RMII_CLK pulse width high
—
50
MHz
RMII1
35%
65%
RMII_CLK
period
RMII2
RMII_CLK pulse width low
35%
65%
RMII_CLK
period
RMII3
RMII4
RXD[1:0], CRS_DV, RXER to RMII_CLK setup
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
4
2
—
—
ns
ns
Table continues on the next page...
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Table 41. RMII signal switching specifications
(continued)
Num
RMII7
RMII8
Description
Min.
4
Max.
—
Unit
ns
RMII_CLK to TXD[1:0], TXEN invalid
RMII_CLK to TXD[1:0], TXEN valid
—
15.4
ns
3.8.2 USB Voltage Regulator Electrical Specifications
Table 42. USB VREG electrical specifications
Symbol
Description
Min.
Typ.1
Max.
Unit
Notes
VREG_IN0 Regulator selectable input supply voltages
VREG_IN1
2.7
—
5.5
V
2
IDDon
Quiescent current — Run mode, load current
equal zero, input supply (VREG_IN*) > 3.6 V
μA
μA
—
—
—
—
VREG_IN0
VREG_IN1
157
157
2
IDDstby
Quiescent current — Standby mode, load
current equal zero
—
—
—
—
VREG_IN0
VREG_IN1
IDDoff
2
Quiescent current — Shutdown mode
VREG_IN0
VREG_IN1
• VREG_IN*= 5.0 V and temperature=25 °C
—
—
680
920
—
—
—
nA
ILOADrun
ILOADstby
Maximum load current — Run mode
—
150
1
mA
mA
mV
3
4
Maximum load current — Standby mode
—
—
VDROPOUT Regulator drop-out voltage — Run mode at
maximum load current with inrush current limit
disabled
300
—
—
VREG_OUT Regulator programmable output target voltage
— Selected input supply > programmed output
target voltage + VDROPOUT
3
3.3
2.8
3.6
3.6
V
V
2.1
• Run mode
• Standby mode
COUT
ESR
External output capacitor
1.76
1
2.2
—
8.16
100
μF
External output capacitor equivalent series
resistance
mΩ
ILIM
Short circuit current
Inrush current limit
—
350
—
—
mA
mA
5
IINRUSH
40
100
6, 7, 8,
9, 10
1. Typical values assume the selected input supply is 5.0 V, Temp = 25 °C unless otherwise stated.
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2. Operation range is 2.7 V to 5.5 V; tolerance voltage is up to 6 V.
3. 150mA is inclusive of the run mode current of the on-chip USB modules. Available load outside of the chip depends on
USB operation and device power dissipation limits.
4. The target voltage for the regulator is programmable, accounting for the range of the max and min values
5. Current limit disabled.
6. Current limit should be disabled after the powers have stabilized to allow full functionality of the regulator.
7. Limited Characterization
8. IINRUSH with VREGINx=4.0 V to 5.5 V
9. The minimum value of IINRUSH is stated for operation when only one of VREG_IN0 / VREG_IN1 is powered, or when
VREG_IN0 and VREG_IN1 both have the same voltage level. When VREG_IN0 and VREG_IN1 are operated at
different voltage levels with the selected VREG_IN lower than the non-selected VREG_IN, the minumum value of
IINRUSH may decrease to a lower value.
10. Total current load on startup should be less than IINRUSH min over full input voltage range of the regulator.
3.8.3 USB Full Speed Transceiver and High Speed PHY
specifications
This section describes the USB0 port Full Speed/Low Speed transceiver and USB1
port USB-PHY High Speed Phy parameters. The high speed phy is capable of full and
low speed signalling as well.
The USB0 (FS/LS Transceiver) and USB1 ((USB HS/FS/LS) meet the electrical
compliance requirements defined in the Universal Serial Bus Revision 2.0
Specification with the amendments below.
• USB ENGINEERING CHANGE NOTICE
• Title: 5V Short Circuit Withstand Requirement Change
• Applies to: Universal Serial Bus Specification, Revision 2.0
• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
• USB ENGINEERING CHANGE NOTICE
• Title: Pull-up/Pull-down resistors
• Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE
• Title: Suspend Current Limit Changes
• Applies to: Universal Serial Bus Specification, Revision 2.0
• On-The-Go and Embedded Host Supplement to the USB Revision 2.0
Specification
• Revision 2.0 version 1.1a July 27, 2012
• Battery Charging Specification (available from USB-IF)
• Revision 1.2 (including errata and ECNs through March 15, 2012), March 15,
2012
USB1_VBUS pin is a detector function which is 5v tolerant and complies with the
above specifications without needing any external voltage division components.
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3.8.4 USB DCD electrical specifications
Table 43. USB DCD electrical specifications
Symbol
VDP_SRC
Description
Min.
Typ.
Max.
Unit
,
USB_DP and USB_DM source voltages (up to 250
0.5
—
0.7
V
VDM_SRC μA)
VLGC
IDP_SRC
IDM_SINK
Threshold voltage for logic high
0.8
7
—
10
2.0
13
V
USB_DP source current
μA
μA
,
USB_DM and USB_DP sink currents
50
100
150
IDP_SINK
RDM_DWN D- pulldown resistance for data pin contact detect
VDAT_REF Data detect voltage
14.25
0.25
—
24.8
0.4
kΩ
V
0.33
3.8.5 CAN switching specifications
See General switching specifications.
3.8.6 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to
the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 44. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
30
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
1
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
—
15.0
—
ns
ns
1.0
Table continues on the next page...
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Table 44. Master mode DSPI timing (limited voltage range) (continued)
Num
DS7
DS8
Description
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Min.
15.8
0
Max.
—
Unit
ns
Notes
—
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 26. DSPI classic SPI timing — master mode
Table 45. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
15 1
V
MHz
ns
Frequency of operation
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
23.0
—
ns
ns
2.7
7.0
—
—
—
ns
—
ns
13
13
ns
ns
1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with
continuous CS and SCK, there is a constraint that SPI clock should not be greater than 1/6 of bus clock, for example,
when bus clock is 60MHz, SPI clock should not be greater than 10MHz.
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DSPI_SS
DS10
DS9
DSPI_SCK
DS15
DS12
DS16
DS11
(CPOL=0)
First data
Last data
DSPI_SOUT
Data
Data
DS13
DS14
First data
Last data
DSPI_SIN
Figure 27. DSPI classic SPI timing — slave mode
3.8.7 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 46. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
15
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
4 x tBUS
—
(tSCK/2) - 4 (tSCK/2) + 4
ns
(tBUS x 2) −
4
—
ns
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
1.0
15.8
0
15
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
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DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 28. DSPI classic SPI timing — master mode
Table 47. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
1.71
Frequency of operation
—
7.5
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
23.1
—
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
ns
ns
2.6
7.0
—
—
—
ns
—
ns
13.0
13.0
ns
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 29. DSPI classic SPI timing — slave mode
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3.8.8 I2C switching specifications
See General switching specifications.
3.8.9 UART switching specifications
See General switching specifications.
3.8.10 Low Power UART switching specifications
See General switching specifications.
3.8.11 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 48. SDHC full voltage range switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Card input clock
SD1
fpp
fpp
fpp
fOD
tWL
tWH
tTLH
tTHL
Clock frequency (low speed)
0
0
400
25\50
20\50
400
—
kHz
MHz
MHz
kHz
ns
Clock frequency (SD\SDIO full speed\high speed)
Clock frequency (MMC full speed\high speed)
Clock frequency (identification mode)
Clock low time
0
0
SD2
SD3
SD4
SD5
7
Clock high time
7
—
ns
Clock rise time
—
—
3
ns
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid) -5 8.6 8.3
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
ns
SD7
SD8
tISU
tIH
SDHC input setup time
SDHC input hold time
5
0
—
—
ns
ns
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Peripheral operating requirements and behaviors
Table 49. SDHC limited voltage range switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Card input clock
SD1
fpp
fpp
fpp
fOD
tWL
tWH
tTLH
tTHL
Clock frequency (low speed)
0
0
400
25\50
20\50
400
—
kHz
MHz
MHz
kHz
ns
Clock frequency (SD\SDIO full speed\high speed)
Clock frequency (MMC full speed\high speed)
Clock frequency (identification mode)
Clock low time
0
0
SD2
SD3
SD4
SD5
7
Clock high time
7
—
ns
Clock rise time
—
—
3
ns
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid) -5 7.6 8.3
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
ns
SD7
SD8
tISU
tIH
SDHC input setup time
SDHC input hold time
5
0
—
—
ns
ns
SD3
SD6
SD2
SD1
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
SD7
SD8
Input SDHC_DAT[3:0]
Figure 30. SDHC timing
3.8.12 I2S switching specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] =
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0, RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or
the frame sync (I2S_FS) shown in the figures below.
Table 50. I2S master mode timing (limited voltage range)
Num
Description
Min.
2.7
40
45%
80
45%
—
Max.
3.6
—
Unit
Operating voltage
V
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
55%
—
MCLK period
ns
I2S_BCLK pulse width high/low
I2S_BCLK to I2S_FS output valid
I2S_BCLK to I2S_FS output invalid
I2S_BCLK to I2S_TXD valid
I2S_BCLK to I2S_TXD invalid
I2S_RXD/I2S_FS input setup before I2S_BCLK
I2S_RXD/I2S_FS input hold after I2S_BCLK
55%
15
BCLK period
ns
ns
ns
ns
ns
ns
0
—
—
15
0
—
15
0
—
—
S1
S2
S2
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S3
S4
S4
S5
S6
S10
S9
S7
S8
S7
S8
S9
S10
I2S_RXD
Figure 31. I2S timing — master mode
Table 51. I2S slave mode timing (limited voltage range)
Num
Description
Operating voltage
Min.
2.7
Max.
Unit
3.6
—
V
ns
S11
S12
I2S_BCLK cycle time (input)
80
I2S_BCLK pulse width high/low (input)
45%
55%
MCLK period
Table continues on the next page...
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Table 51. I2S slave mode timing (limited voltage range) (continued)
Num
S13
S14
S15
S16
S17
S18
S19
Description
Min.
4.5
2
Max.
—
Unit
ns
I2S_FS input setup before I2S_BCLK
I2S_FS input hold after I2S_BCLK
I2S_BCLK to I2S_TXD/I2S_FS output valid
I2S_BCLK to I2S_TXD/I2S_FS output invalid
I2S_RXD setup before I2S_BCLK
I2S_RXD hold after I2S_BCLK
—
ns
—
0
20
—
ns
ns
4.5
2
—
ns
—
ns
I2S_TX_FS input assertion to I2S_TXD output valid1
25
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S12
S15
S16
S13
S14
S19
S15
S16
S15
S16
S17
S18
I2S_RXD
Figure 32. I2S timing — slave modes
3.8.12.1 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 52. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
40
3.6
—
V
S1
S2
S3
S4
I2S_MCLK cycle time
ns
I2S_MCLK (as an input) pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
45%
80
55%
—
MCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
55%
BCLK period
Table continues on the next page...
Kinetis K65 Sub-Family, Rev. 2, 05/2015
67
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 52. I2S/SAI master mode timing (continued)
Num.
Characteristic
Min.
Max.
Unit
S5
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
0
15
—
ns
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
15
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
15
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 33. I2S/SAI timing — master modes
Table 53. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
80
3.6
—
V
S11
S12
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
S14
S15
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
4.5
2
—
ns
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
23.1
Table continues on the next page...
68
Kinetis K65 Sub-Family, Rev. 2, 05/2015
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 53. I2S/SAI slave mode timing (continued)
Num.
S16
Characteristic
Min.
Max.
Unit
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
0
—
—
—
25
ns
ns
ns
ns
S17
S18
S19
4.5
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 34. I2S/SAI timing — slave modes
3.8.12.2 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 54. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
62.5
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
45%
250
55%
—
MCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
55%
45
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
Table continues on the next page...
Kinetis K65 Sub-Family, Rev. 2, 05/2015
69
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 54. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
Characteristic
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
Min.
Max.
Unit
S7
S8
S9
—
0
45
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 35. I2S/SAI timing — master modes
Table 55. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
250
3.6
—
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
S12
S13
S14
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
5
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
S15
S16
S17
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
56.5
—
ns
ns
ns
30
—
Table continues on the next page...
70
Kinetis K65 Sub-Family, Rev. 2, 05/2015
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 55. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
S18
S19
Characteristic
Min.
Max.
Unit
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
5
—
ns
ns
—
72
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 36. I2S/SAI timing — slave modes
3.9 Human-machine interfaces (HMI)
3.9.1 TSI electrical specifications
Table 56. TSI electrical specifications
Symbol
TSI_RUNF
TSI_RUNV
Description
Min.
—
Typ.
100
—
Max.
Unit
µA
Fixed power consumption in run mode
—
Variable power consumption in run mode
(depends on oscillator's current selection)
1.0
128
µA
TSI_EN
TSI_DIS
Power consumption in enable mode
Power consumption in disable mode
TSI analog enable time
—
—
100
1.2
66
—
—
µA
µA
µs
pF
V
TSI_TEN
—
—
TSI_CREF
TSI_DVOLT
TSI reference capacitor
—
1.0
—
—
Voltage variation of VP & VM around nominal
values
0.19
1.03
Kinetis K65 Sub-Family, Rev. 2, 05/2015
71
Freescale Semiconductor, Inc.
Dimensions
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
169-pin MAPBGA
Then use this document number
98ASA00628D
5 Pinout
5.1 K65_169BGA Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
169
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
A1
B1
C1
D1
PTE0
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE7a
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE7a
PTE0
SPI1_PCS1
SPI1_SOUT
SPI1_SCK
SPI1_SIN
UART1_TX
UART1_RX
SDHC0_D1
SDHC0_D0
TRACE_
CLKOUT
I2C1_SDA
I2C1_SCL
RTC_
CLKOUT
PTE1/
LLWU_P0
PTE1/
LLWU_P0
TRACE_D3
SPI1_SIN
PTE2/
LLWU_P1
PTE2/
LLWU_P1
UART1_CTS_ SDHC0_
b DCLK
TRACE_D2
PTE3
PTE3
UART1_RTS_ SDHC0_CMD TRACE_D1
b
SPI1_SOUT
G5
C3
E1
VDD
VSS
VDD
VDD
VSS
VSS
PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0
UART3_TX
UART3_RX
SDHC0_D3
SDHC0_D2
TRACE_D0
D2
E2
PTE5
DISABLED
DISABLED
PTE5
SPI1_PCS2
SPI1_PCS3
FTM3_CH0
FTM3_CH1
PTE6/
LLWU_P16
PTE6/
LLWU_P16
UART3_CTS_ I2S0_MCLK
b
USB0_SOF_
OUT
72
Freescale Semiconductor, Inc.
Kinetis K65 Sub-Family, Rev. 2, 05/2015
Pinout
169
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
E3
PTE7
DISABLED
PTE7
UART3_RTS_ I2S0_RXD0
b
FTM3_CH2
E4
F3
PTE8
DISABLED
DISABLED
PTE8
I2S0_RXD1
I2S0_TXD1
I2S0_RX_FS
LPUART0_TX FTM3_CH3
LPUART0_RX FTM3_CH4
PTE9/
LLWU_P17
PTE9/
LLWU_P17
I2S0_RX_
BCLK
F4
G4
H4
PTE10/
LLWU_P18
DISABLED
DISABLED
DISABLED
PTE10/
LLWU_P18
I2C3_SDA
I2C3_SCL
I2S0_TXD0
LPUART0_
CTS_b
FTM3_CH5
FTM3_CH6
FTM3_CH7
USB1_ID
PTE11
PTE11
I2S0_TX_FS
LPUART0_
RTS_b
PTE12
PTE12
I2S0_TX_
BCLK
G6
G8
H3
F5
VDD
VDD
VDD
VSS
VSS
VSS
PTE16
ADC0_SE4a
ADC0_SE5a
ADC0_SE4a
ADC0_SE5a
PTE16
SPI0_PCS0
SPI0_SCK
UART2_TX
UART2_RX
FTM_CLKIN0
FTM_CLKIN1
FTM0_FLT3
TPM_CLKIN0
TPM_CLKIN1
PTE17/
LLWU_P19
PTE17/
LLWU_P19
LPTMR0_
ALT3
F6
F7
PTE18/
LLWU_P20
ADC0_SE6a
ADC0_SE7a
ADC0_SE6a
ADC0_SE7a
PTE18/
LLWU_P20
SPI0_SOUT
SPI0_SIN
UART2_CTS_ I2C0_SDA
b
PTE19
PTE19
UART2_RTS_ I2C0_SCL
b
CMP3_OUT
G3
G1
F1
G2
F2
H2
K1
J1
VSS
VSS
VSS
USB0_DP
USB0_DM
VREG_OUT
VREG_IN0
VREG_IN1
USB1_VSS
USB1_DP
USB1_DM
USB1_VBUS
ADC1_DP1
ADC1_DM1
USB0_DP
USB0_DM
VREG_OUT
VREG_IN0
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
ADC1_DP1
ADC1_DM1
USB0_DP
USB0_DM
VREG_OUT
VREG_IN0
VREG_IN1
USB1_VSS
USB1_DP
USB1_DM
USB1_VBUS
ADC1_DP1
ADC1_DM1
H1
J2
L1
M1
M2
ADC0_DP0/
ADC1_DP3
ADC0_DP0/
ADC1_DP3
ADC0_DP0/
ADC1_DP3
L2
N1
N2
ADC0_DM0/
ADC1_DM3
ADC0_DM0/
ADC1_DM3
ADC0_DM0/
ADC1_DM3
ADC1_DP0/
ADC0_DP3
ADC1_DP0/
ADC0_DP3
ADC1_DP0/
ADC0_DP3
ADC1_DM0/
ADC0_DM3
ADC1_DM0/
ADC0_DM3
ADC1_DM0/
ADC0_DM3
J3
VDDA
VDDA
VDDA
K3
VREFH
VREFH
VREFH
Kinetis K65 Sub-Family, Rev. 2, 05/2015
73
Freescale Semiconductor, Inc.
Pinout
169
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
K4
J4
VREFL
VSSA
VREFL
VREFL
VSSA
VSSA
M3
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
L3
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
N3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
M4
N4
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
M5
TAMPER0/
RTC_
TAMPER0/
RTC_
TAMPER0/
RTC_
WAKEUP_B
WAKEUP_B
WAKEUP_B
L4
L5
K5
L6
K6
N5
N6
M6
J6
TAMPER1
TAMPER2
TAMPER3
TAMPER4
TAMPER5
XTAL32
EXTAL32
VBAT
TAMPER1
TAMPER2
TAMPER3
TAMPER4
TAMPER5
XTAL32
TAMPER1
TAMPER2
TAMPER3
TAMPER4
TAMPER5
XTAL32
EXTAL32
VBAT
EXTAL32
VBAT
TAMPER6
TAMPER7
VDD
TAMPER6
TAMPER7
VDD
TAMPER6
TAMPER7
VDD
J5
G7
N7
L7
K7
VSS
VSS
VSS
PTE24
ADC0_SE17
ADC0_SE18
ADC0_SE17
ADC0_SE18
PTE24
CAN1_TX
CAN1_RX
UART4_TX
UART4_RX
I2C0_SCL
I2C0_SDA
EWM_OUT_b
EWM_IN
PTE25/
PTE25/
LLWU_P21
LLWU_P21
K8
L8
PTE26
PTE27
PTE28
DISABLED
DISABLED
DISABLED
PTE26
PTE27
PTE28
ENET_1588_
CLKIN
UART4_CTS_
b
RTC_
CLKOUT
USB0_CLKIN
UART4_RTS_
b
M7
74
Freescale Semiconductor, Inc.
Kinetis K65 Sub-Family, Rev. 2, 05/2015
Pinout
169
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
N8
PTA0
JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1
PTA0
UART0_CTS_ FTM0_CH5
b/
UART0_COL_
b
LPUART0_
CTS_b
JTAG_TCLK/
SWD_CLK
EZP_CLK
N9
M9
PTA1
PTA2
JTAG_TDI/
EZP_DI
TSI0_CH2
TSI0_CH3
PTA1
PTA2
UART0_RX
FTM0_CH6
FTM0_CH7
I2C3_SDA
I2C3_SCL
LPUART0_RX
LPUART0_TX
JTAG_TDI
EZP_DI
JTAG_TDO/
TRACE_
SWO/
UART0_TX
JTAG_TDO/
TRACE_SWO
EZP_DO
EZP_DO
M8
L9
PTA3
JTAG_TMS/
SWD_DIO
TSI0_CH4
TSI0_CH5
PTA3
UART0_RTS_ FTM0_CH0
b
LPUART0_
RTS_b
JTAG_TMS/
SWD_DIO
PTA4/
NMI_b/
PTA4/
FTM0_CH1
NMI_b
EZP_CS_b
LLWU_P3
EZP_CS_b
LLWU_P3
N10
PTA5
DISABLED
PTA5
USB0_CLKIN
FTM0_CH2
RMII0_RXER/ CMP2_OUT
MII0_RXER
I2S0_TX_
BCLK
JTAG_TRST_
b
H5
H8
VDD
VSS
VDD
VDD
VSS
VSS
M10
PTA6
DISABLED
PTA6
PTA7
PTA8
FTM0_CH3
FTM0_CH4
FTM1_CH0
CLKOUT
TRACE_
CLKOUT
L10
K9
PTA7
PTA8
ADC0_SE10
ADC0_SE11
ADC0_SE10
ADC0_SE11
RMII0_MDIO/
MII0_MDIO
TRACE_D3
RMII0_MDC/
MII0_MDC
FTM1_QD_
PHA/
TRACE_D2
TPM1_CH0
K10
N11
M11
L12
L11
K13
PTA9
DISABLED
DISABLED
DISABLED
CMP2_IN0
CMP2_IN1
DISABLED
PTA9
FTM1_CH1
FTM2_CH0
FTM2_CH1
FTM1_CH0
FTM1_CH1
UART0_TX
UART0_RX
MII0_RXD3
MII0_RXD2
FTM1_QD_
PHB/
TPM1_CH1
TRACE_D1
TRACE_D0
PTA10/
LLWU_P22
PTA10/
LLWU_P22
FTM2_QD_
PHA/
TPM2_CH0
PTA11/
LLWU_P23
PTA11/
LLWU_P23
MII0_RXCLK
I2C2_SDA
FTM2_QD_
PHB/
TPM2_CH1
PTA12
CMP2_IN0
CMP2_IN1
PTA12
CAN0_TX
CAN0_RX
SPI0_PCS0
RMII0_RXD1/ I2C2_SCL
MII0_RXD1
I2S0_TXD0
FTM1_QD_
PHA/
TPM1_CH0
PTA13/
LLWU_P4
PTA13/
LLWU_P4
RMII0_RXD0/ I2C2_SDA
MII0_RXD0
I2S0_TX_FS
FTM1_QD_
PHB/
TPM1_CH1
PTA14
PTA14
RMII0_CRS_
DV/
MII0_RXDV
I2C2_SCL
I2S0_RX_
BCLK
I2S0_TXD1
K12
J13
PTA15
PTA16
CMP3_IN1
CMP3_IN2
CMP3_IN1
CMP3_IN2
PTA15
PTA16
SPI0_SCK
RMII0_TXEN/
MII0_TXEN
I2S0_RXD0
SPI0_SOUT
UART0_CTS_ RMII0_TXD0/
b/ MII0_TXD0
I2S0_RX_FS
I2S0_RXD1
Kinetis K65 Sub-Family, Rev. 2, 05/2015
75
Freescale Semiconductor, Inc.
Pinout
169
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
UART0_COL_
b
J12
PTA17
ADC1_SE17
ADC1_SE17
PTA17
SPI0_SIN
UART0_RTS_ RMII0_TXD1/
I2S0_MCLK
b
MII0_TXD1
N12
M12
N13
M13
VDD
VDD
VDD
VSS
VSS
VSS
PTA18
PTA19
EXTAL0
XTAL0
EXTAL0
XTAL0
PTA18
PTA19
FTM0_FLT2
FTM1_FLT0
FTM_CLKIN0
FTM_CLKIN1
TPM_CLKIN0
TPM_CLKIN1
LPTMR0_
ALT1
L13
K11
RESET_b
PTA24
RESET_b
CMP3_IN4
RESET_b
CMP3_IN4
PTA24
PTA25
PTA26
PTA27
MII0_TXD2
MII0_TXCLK
MII0_TXD3
MII0_CRS
FB_A15/
SDRAM_D15
FB_A29
FB_A28
FB_A27
FB_A26
J11
J10
H13
PTA25
PTA26
PTA27
CMP3_IN5
DISABLED
DISABLED
CMP3_IN5
FB_A14/
SDRAM_D14
FB_A13/
SDRAM_D13
FB_A12/
SDRAM_D12
H12
H11
H10
PTA28
PTA29
PTA30
DISABLED
DISABLED
DISABLED
PTA28
PTA29
PTA30
MII0_TXER
MII0_COL
FB_A25
FB_A24
CAN0_TX
CAN0_RX
I2C0_SCL
FB_A11/
SDRAM_D11
J9
PTA31
DISABLED
PTA31
FB_A10/
SDRAM_D10
G13
PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
PTB0/
LLWU_P5
FTM1_CH0
FTM1_CH1
RMII0_MDIO/
MII0_MDIO
SDRAM_
CAS_b
FTM1_QD_
PHA/
TPM1_CH0
G12
PTB1
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
PTB1
I2C0_SDA
RMII0_MDC/
MII0_MDC
SDRAM_
RAS_b
FTM1_QD_
PHB/
TPM1_CH1
G11
G10
PTB2
PTB3
ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
PTB2
PTB3
I2C0_SCL
I2C0_SDA
UART0_RTS_ ENET0_
SDRAM_WE
FTM0_FLT3
FTM0_FLT0
b
1588_TMR0
ADC0_SE13/
TSI0_CH8
ADC0_SE13/
TSI0_CH8
UART0_CTS_ ENET0_
SDRAM_
CS0_b
b/
1588_TMR1
UART0_COL_
b
H9
PTB4
PTB5
PTB6
PTB7
ADC1_SE10
ADC1_SE11
ADC1_SE12
ADC1_SE13
ADC1_SE10
ADC1_SE11
ADC1_SE12
ADC1_SE13
PTB4
PTB5
PTB6
PTB7
ENET0_
1588_TMR2
SDRAM_
CS1_b
FTM1_FLT0
FTM2_FLT0
F13
F12
F11
ENET0_
1588_TMR3
FB_AD23/
SDRAM_D23
FB_AD22/
SDRAM_D22
76
Freescale Semiconductor, Inc.
Kinetis K65 Sub-Family, Rev. 2, 05/2015
Pinout
169
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
F10
PTB8
DISABLED
DISABLED
ADC1_SE14
ADC1_SE15
DISABLED
PTB8
UART3_RTS_
b
FB_AD21/
SDRAM_D21
F9
PTB9
PTB9
SPI1_PCS1
SPI1_PCS0
SPI1_SCK
UART3_CTS_
b
FB_AD20/
SDRAM_D20
G9
PTB10
PTB11
PTB12
ADC1_SE14
ADC1_SE15
PTB10
PTB11
PTB12
UART3_RX
FB_AD19/
SDRAM_D19
FTM0_FLT1
FTM0_FLT2
E13
E12
UART3_TX
FB_AD18/
SDRAM_D18
UART3_RTS_ FTM1_CH0
b
FTM0_CH4
FTM0_CH5
FB_A9/
SDRAM_D9
FTM1_QD_
PHA/
TPM1_CH0
E11
PTB13
DISABLED
PTB13
UART3_CTS_ FTM1_CH1
b
FB_A8/
SDRAM_D8
FTM1_QD_
PHB/
TPM1_CH1
E10
E9
PTB14
PTB15
PTB16
PTB17
PTB18
DISABLED
DISABLED
TSI0_CH9
TSI0_CH10
TSI0_CH11
PTB14
PTB15
PTB16
PTB17
PTB18
CAN1_TX
CAN1_RX
FB_A7/
SDRAM_D7
FB_A6/
SDRAM_D6
F8
TSI0_CH9
TSI0_CH10
TSI0_CH11
SPI1_SOUT
SPI1_SIN
CAN0_TX
UART0_RX
UART0_TX
FTM2_CH0
FTM_CLKIN0
FTM_CLKIN1
FB_AD17/
SDRAM_D17
EWM_IN
TPM_CLKIN0
D13
D12
FB_AD16/
SDRAM_D16
EWM_OUT_b TPM_CLKIN1
I2S0_TX_
BCLK
FB_AD15/
SDRAM_A23
FTM2_QD_
PHA/
TPM2_CH0
D11
PTB19
TSI0_CH12
TSI0_CH12
PTB19
CAN0_RX
FTM2_CH1
I2S0_TX_FS
FB_OE_b
FTM2_QD_
PHB/
TPM2_CH1
D10
D9
PTB20
PTB21
PTB22
PTB23
PTC0
DISABLED
DISABLED
DISABLED
DISABLED
PTB20
PTB21
PTB22
PTB23
PTC0
SPI2_PCS0
SPI2_SCK
SPI2_SOUT
SPI2_SIN
FB_AD31/
SDRAM_D31
CMP0_OUT
CMP1_OUT
CMP2_OUT
CMP3_OUT
I2S0_TXD1
I2S0_TXD0
I2S0_TX_FS
FB_AD30/
SDRAM_D30
C13
C12
B13
B12
A13
FB_AD29/
SDRAM_D29
SPI0_PCS5
FB_AD28/
SDRAM_D28
ADC0_SE14/
TSI0_CH13
ADC0_SE14/
TSI0_CH13
SPI0_PCS4
SPI0_PCS3
SPI0_PCS2
PDB0_
EXTRG
USB0_SOF_
OUT
FB_AD14/
SDRAM_A22
PTC1/
LLWU_P6
ADC0_SE15/
TSI0_CH14
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6
UART1_RTS_ FTM0_CH0
b
FB_AD13/
SDRAM_A21
PTC2
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
PTC2
UART1_CTS_ FTM0_CH1
b
FB_AD12/
SDRAM_A20
A12
C11
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1
UART1_RX
FTM0_CH2
CLKOUT
I2S0_TX_
BCLK
VSS
VSS
VSS
Kinetis K65 Sub-Family, Rev. 2, 05/2015
77
Freescale Semiconductor, Inc.
Pinout
169
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
H6
VDD
PTC4/
LLWU_P8
VDD
VDD
B11
DISABLED
DISABLED
CMP0_IN0
CMP0_IN1
PTC4/
LLWU_P8
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART1_TX
FTM0_CH3
I2S0_RXD0
FB_AD11/
SDRAM_A19
CMP1_OUT
CMP0_OUT
I2S0_MCLK
A11
A10
B10
C10
C9
PTC5/
LLWU_P9
PTC5/
LLWU_P9
LPTMR0_
ALT2
FB_AD10/
SDRAM_A18
FTM0_CH2
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN1
PTC6/
LLWU_P10
PDB0_
EXTRG
I2S0_RX_
BCLK
FB_AD9/
SDRAM_A17
PTC7
PTC8
PTC9
PTC10
PTC7
PTC8
PTC9
PTC10
USB0_SOF_
OUT
I2S0_RX_FS
FB_AD8/
SDRAM_A16
ADC1_SE4b/
CMP0_IN2
ADC1_SE4b/
CMP0_IN2
FTM3_CH4
FTM3_CH5
FTM3_CH6
FTM3_CH7
I2S0_MCLK
FB_AD7/
SDRAM_A15
ADC1_SE5b/
CMP0_IN3
ADC1_SE5b/
CMP0_IN3
I2S0_RX_
BCLK
FB_AD6/
SDRAM_A14
FTM2_FLT0
FTM3_FLT0
A8
ADC1_SE6b
ADC1_SE7b
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
ADC1_SE6b
I2C1_SCL
I2C1_SDA
I2S0_RX_FS
FB_AD5/
SDRAM_A13
A9
PTC11/
LLWU_P11
ADC1_SE7b
PTC11/
LLWU_P11
I2S0_RXD1
FB_RW_b
B9
PTC12
PTC13
PTC14
PTC15
PTC16
PTC12
PTC13
PTC14
PTC15
PTC16
UART4_RTS_ FTM_CLKIN0
b
FB_AD27/
SDRAM_D27
TPM_CLKIN0
TPM_CLKIN1
B8
UART4_CTS_ FTM_CLKIN1
b
FB_AD26/
SDRAM_D26
C8
UART4_RX
FB_AD25/
SDRAM_D25
D8
UART4_TX
FB_AD24/
SDRAM_D24
E8
CAN1_RX
CAN1_TX
UART3_RX
UART3_TX
ENET0_
1588_TMR0
FB_CS5_b/
FB_TSIZ1/
FB_BE23_
16_BLS15_8_
b/
SDRAM_
DQM2
E7
PTC17
DISABLED
PTC17
ENET0_
1588_TMR1
FB_CS4_b/
FB_TSIZ0/
FB_BE31_
24_BLS7_0_
b/
SDRAM_
DQM3
D7
C7
PTC18
PTC19
DISABLED
DISABLED
PTC18
PTC19
UART3_RTS_ ENET0_
FB_TBST_b/
FB_CS2_b/
FB_BE15_8_
BLS23_16_b/
SDRAM_
b
1588_TMR2
DQM1
UART3_CTS_ ENET0_
FB_CS3_b/
FB_BE7_0_
BLS31_24_b/
FB_TA_b
b
1588_TMR3
78
Freescale Semiconductor, Inc.
Kinetis K65 Sub-Family, Rev. 2, 05/2015
Pinout
169
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
SDRAM_
DQM0
B7
A7
E6
D6
C6
B6
A6
PTC24
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
PTC24
LPUART0_TX
LPUART0_RX
FB_A5/
SDRAM_D5
PTC25
PTC26
PTC27
PTC28
PTC29
PTC25
PTC26
PTC27
PTC28
PTC29
FB_A4/
SDRAM_D4
LPUART0_
CTS_b
ENET0_
1588_TMR0
FB_A3/
SDRAM_D3
LPUART0_
RTS_b
ENET0_
1588_TMR1
FB_A2/
SDRAM_D2
I2C3_SDA
I2C3_SCL
SPI0_PCS0
ENET0_
1588_TMR2
FB_A1/
SDRAM_D1
ENET0_
1588_TMR3
FB_A0/
SDRAM_D0
PTD0/
LLWU_P12
PTD0/
LLWU_P12
UART2_RTS_ FTM3_CH0
b
FB_ALE/
FB_CS1_b/
FB_TS_b
A5
A4
B4
B5
C4
PTD1
ADC0_SE5b
DISABLED
DISABLED
DISABLED
ADC0_SE6b
ADC0_SE5b
PTD1
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART2_CTS_ FTM3_CH1
b
FB_CS0_b
PTD2/
LLWU_P13
PTD2/
LLWU_P13
UART2_RX
FTM3_CH2
FB_AD4/
SDRAM_A12
I2C0_SCL
I2C0_SDA
SPI1_PCS0
PTD3
PTD3
UART2_TX
FTM3_CH3
FB_AD3/
SDRAM_A11
PTD4/
LLWU_P14
PTD4/
LLWU_P14
SPI0_PCS1
SPI0_PCS2
UART0_RTS_ FTM0_CH4
b
FB_AD2/
SDRAM_A10
EWM_IN
PTD5
ADC0_SE6b
ADC0_SE7b
PTD5
UART0_CTS_ FTM0_CH5
b/
UART0_COL_
b
FB_AD1/
SDRAM_A9
EWM_OUT_b SPI1_SCK
C5
PTD6/
LLWU_P15
ADC0_SE7b
PTD6/
LLWU_P15
SPI0_PCS3
UART0_RX
FTM0_CH6
FTM0_CH7
FB_AD0
FTM0_FLT0
SPI1_SOUT
SPI1_SIN
J8
H7
E5
D5
VSS
VSS
VSS
VDD
VDD
PTD7
VDD
DISABLED
DISABLED
PTD7
CMT_IRO
I2C0_SCL
UART0_TX
SDRAM_CKE FTM0_FLT1
LPUART0_RX FB_A16
PTD8/
PTD8/
LLWU_P24
LLWU_P24
D4
D3
PTD9
DISABLED
DISABLED
PTD9
I2C0_SDA
LPUART0_TX FB_A17
PTD10
PTD10
LPUART0_
RTS_b
FB_A18
C2
PTD11/
LLWU_P25
DISABLED
PTD11/
LLWU_P25
SPI2_PCS0
SDHC0_
CLKIN
LPUART0_
CTS_b
FB_A19
B2
B3
A2
A3
PTD12
PTD13
PTD14
PTD15
DISABLED
DISABLED
DISABLED
DISABLED
PTD12
PTD13
PTD14
PTD15
SPI2_SCK
SPI2_SOUT
SPI2_SIN
FTM3_FLT0
SDHC0_D4
SDHC0_D5
SDHC0_D6
SDHC0_D7
FB_A20
FB_A21
FB_A22
FB_A23
SPI2_PCS1
Kinetis K65 Sub-Family, Rev. 2, 05/2015
79
Freescale Semiconductor, Inc.
Pinout
169
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
J7
NC
NC
NC
NC
NC
NC
K2
5.2 Recommended connection for unused analog and digital
pins
Table 57 shows the recommended connections for analog interface pins if those analog
interfaces are not used in the customer's application
Table 57. Recommended connection for unused analog interfaces
Pin Type
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
GPIO/Analog
K65
Short recommendation
Float
Detailed recommendation
Analog input - Float
ADCx/CMPx
VREF_OUT
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Analog output - Float
DAC0_OUT, DAC1_OUT
RTC_WAKEUP_B
XTAL32
Analog output - Float
Analog output - Float
Analog output - Float
EXTAL32
Analog input - Float
PTA18/EXTAL0
PTA19/XTAL0
PTx/ADCx
Analog input - Float
GPIO/Analog
Analog output - Float
GPIO/Analog
Float (default is analog input)
Float (default is analog input)
Float (default is analog input)
GPIO/Analog
PTx/CMPx
GPIO/Analog
PTx/TSIOx
GPIO/Digital
PTA0/JTAG_TCLK
Float (default is JTAG with
pulldown)
GPIO/Digital
GPIO/Digital
GPIO/Digital
GPIO/Digital
PTA1/JTAG_TDI
PTA2/JTAG_TDO
PTA3/JTAG_TMS
PTA4/NMI_b
Float
Float
Float
Float (default is JTAG with
pullup)
Float (default is JTAG with
pullup)
Float (default is JTAG with
pullup)
10kΩ pullup or disable and
float
Pull high or disable in PCR &
FOPT and float
GPIO/Digital
USB
PTx
Float
Float
Float
Float (default is disabled)
USB0_DP
USB0_DM
VREG_OUT
Float
Float
USB
USB
Tie to input and ground
through 10kΩ
Tie to input and ground
through 10kΩ
USB
VREG_IN0
Tie to output and ground
through 10kΩ
Tie to output and ground
through 10kΩ
Table continues on the next page...
80
Kinetis K65 Sub-Family, Rev. 2, 05/2015
Freescale Semiconductor, Inc.
Pinout
Table 57. Recommended connection for unused analog interfaces (continued)
Pin Type
K65
Short recommendation
Detailed recommendation
USB
VREG_IN1
Tie to output and ground
through 10kΩ
Tie to output and ground
through 10kΩ
USB
USB1_VSS
USB1_DP
USB1_DM
USB1_VBUS
VBAT
Always connect to VSS
Always connect to VSS
USB
Float
Float
Float
Float
Float
Float
Float
Float
USB
USB
VBAT
VDDA
VDDA
Always connect to VDD
potential
Always connect to VDD
potential
VREFH
VREFL
VSSA
VREFH
VREFL
VSSA
Always connect to VDD
potential
Always connect to VDD
potential
Always connect to VSS
potential
Always connect to VSS
potential
Always connect to VSS
potential
Always connect to VSS
potential
5.3 K65 Pinouts
The below figure shows the pinout diagram for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see the previous section.
Kinetis K65 Sub-Family, Rev. 2, 05/2015
81
Freescale Semiconductor, Inc.
Ordering parts
1
2
3
4
5
6
7
8
9
10
11
12
13
PTD2/
LLWU_P13
PTC3/
LLWU_P7
A
B
C
D
E
F
PTE0
PTD14
PTD15
PTD1
PTD0/
LLWU_P12
PTC25
PTC10
PTC11/
PTC6/
PTC5/
PTC2
A
B
C
D
E
F
LLWU_P11 LLWU_P10 LLWU_P9
PTE1/
LLWU_P0
PTD12
PTD11/
PTD13
VSS
PTD3
PTD5
PTD9
PTE8
PTD4/
LLWU_P14
PTC29
PTC28
PTC27
PTC26
PTE18/
PTC24
PTC19
PTC18
PTC17
PTE19
VDD
PTC13
PTC14
PTC15
PTC16
PTB16
VSS
PTC12
PTC9
PTB21
PTB15
PTB9
PTC7
PTC8
PTB20
PTB14
PTB8
PTB3
PTA30
PTA26
PTA9
PTC4/
PTC1/
LLWU_P8 LLWU_P6
PTC0
PTB22
PTB17
PTB11
PTB5
PTE2/
LLWU_P1 LLWU_P25
PTD6/
LLWU_P15
VSS
PTB23
PTB18
PTB12
PTB6
PTE3
PTE5
PTD10
PTE7
PTE9/
PTD8/
LLWU_P24
PTB19
PTB13
PTB7
PTE4/
LLWU_P2 LLWU_P16
PTE6/
PTD7
USB0_DM VREG_IN0
PTE10/
PTE17/
LLWU_P17 LLWU_P18 LLWU_P19 LLWU_P20
G
H
J
USB0_DP VREG_OUT
USB1_DM VREG_IN1
VSS
PTE11
PTE12
VSSA
VDD
VDD
VDD
VDD
PTB10
PTB4
PTB2
PTB1
PTB0/
LLWU_P5
G
H
J
PTE16
VDD
VSS
PTA29
PTA25
PTA24
PTA28
PTA17
PTA15
PTA12
VSS
PTA27
PTA16
USB1_DP USB1_VBUS VDDA
TAMPER7 TAMPER6
TAMPER3 TAMPER5
NC
VSS
PTA31
PTA8
K
L
USB1_VSS
ADC1_DP1
ADC1_DM1
NC
VREFH
VREFL
PTE25/
LLWU_P21
PTE26
PTE27
PTA3
PTA14
K
L
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC0_DM0/
ADC1_DM3
TAMPER1 TAMPER2 TAMPER4
PTE24
PTE28
PTA4/
LLWU_P3
PTA7
PTA13/
LLWU_P4
RESET_b
PTA19
ADC1_SE16/
CMP2_IN2/
DAC0_OUT/ TAMPER0/
VBAT
ADC0_DP0/
ADC1_DP3
M
N
PTA2
PTA6
PTA11/
LLWU_P23
M
N
CMP1_IN3/
RTC_
WAKEUP_B
ADC0_SE22 ADC0_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
ADC1_DM0/
ADC0_DM3
ADC1_DP0/
ADC0_DP3
XTAL32
5
EXTAL32
6
VSS
7
PTA0
8
PTA1
9
PTA5
10
PTA10/
LLWU_P22
VDD
12
PTA18
13
1
2
3
4
11
Figure 37. K65 169 MAPBGA Pinout Diagram
6 Ordering parts
82
Kinetis K65 Sub-Family, Rev. 2, 05/2015
Freescale Semiconductor, Inc.
Part identification
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable
part numbers for this device, go to freescale.com and perform a part number search for
the following device numbers: PK65 and MK65
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
Kinetis family
• M = Fully qualified, general market flow
• P = Prequalification
K##
A
• K65
• K66
Key attribute
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
FFF
Program flash memory size
• 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 768 = 768 KB
Table continues on the next page...
Kinetis K65 Sub-Family, Rev. 2, 05/2015
83
Freescale Semiconductor, Inc.
Terminology and guidelines
Field
Description
Values
• 1M0 = 1 MB
• 2M0 = 2 MB
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
• C = –40 to 85
PP
• FM = 32 QFN (5 mm x 5 mm)
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
• MI= 169 MAPBGA (9 mm x 9 mm)
• AC= 169 WLCSP (5.6 mm x 5.5 mm)
CC
Maximum CPU frequency (MHz)
• 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz
• 16 = 168 MHz
• 18 = 180 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
7.4 Example
This is an example part number:
MK65FN2M0VMI18
8 Terminology and guidelines
8.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
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Terminology and guidelines
8.1.1 Example
This is an example of an operating requirement:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
8.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of
values for a technical characteristic that are guaranteed during operation if you meet
the operating requirements and any other specified conditions.
8.2.1 Example
This is an example of an operating behavior:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
8.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that
are guaranteed, regardless of whether you meet the operating requirements.
8.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
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Terminology and guidelines
8.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
8.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
8.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
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Terminology and guidelines
8.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
8.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
8.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
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Terminology and guidelines
8.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
8.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
8.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
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Revision History
Unit
Symbol
Description
Ambient temperature
3.3 V supply voltage
Value
TA
25
°C
V
VDD
3.3
9 Revision History
The following table provides a revision history for this document.
Table 58. Revision History
Rev. No.
Date
Substantial Changes
Initial Release
0
1
02/2015
04/2015
• Editorial change
• Updated OTG/EH and BC rev. 1.2 specification references in USB Full Speed
Transceiver and High Speed PHY specifications section
• Updated USBDCD electrical specifications table
• Updated the typical values and maximum values of specs in Power consumption
operating behaviors table
• Removed PSTOP2 current from Power consumption operating behaviors table
• Updated the values of DS5 and DS7 in Master mode DSPI timing (full voltage
range) table
• Updated the footnote and description of VDIO, VAIO and ID in Voltage and current
operating ratings table
• Updated the values and description of specs in Voltage and current operating
requirements table
• Updated the leakage current specs in Voltage and current operating behaviors table
• Added Notes column in Thermal operating requirements
• Updated the values of 48MHz IRC in Low power mode peripheral adders table
• Added new footnotes for IINRUSH in USB VREG electrical specifications table to
better document operation.
• Updated the figures "SDRAM write timing diagram" and SDRAM read timing
diagram" in the section "SDRAM controller specifications."
• Updated the pinout table, and pinout diagrams in the section "Pinouts."
2
05/2015
• Added new footnotes for IINRUSH in USB VREG electrical specifications table to
better document operation.
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Information in this document is provided solely to enable system and
software implementers to use Freescale products. There are no express
or implied copyright licenses granted hereunder to design or fabricate
any integrated circuits based on the information in this document.
Freescale reserves the right to make changes without further notice to
any products herein.
How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support
Freescale makes no warranty, representation, or guarantee regarding
the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages.
“Typical” parameters that may be provided in Freescale data sheets
and/or specifications can and do vary in different applications, and
actual performance may vary over time. All operating parameters,
including “typicals,” must be validated for each customer application by
customer's technical experts. Freescale does not convey any license
under its patent rights nor the rights of others. Freescale sells products
pursuant to standard terms and conditions of sale, which can be found
at the following address: freescale.com/SalesTermsandConditions.
Freescale, Freescale logo, and Kinetis are trademarks of Freescale
Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or
service names are the property of their respective owners. ARM and
Cortex are registered trademarks of ARM Limited. All rights reserved.
© 2013–2015 Freescale Semiconductor, Inc.
Document Number K65P169M180SF5V2
Revision 2, 05/2015
相关型号：
MK65FX1M0CAC18R
Kinetis K 32-bit MCU, ARM Cortex-M4 core, 1 MB Flash, 180MHz, Ethernet, WLCSP 169
NXP
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