MK68564_技术文档

MK68564

SERIAL INPUT OUTPUT

.

COMPATIBLE WITH MK68000 CPU

COMPATIBLE WITH MK68000 SERIES DMA’s

TWO INDEPENDENT FULL-DUPLEX CHAN-

NELS

TWO INDEPENDENT BAUD-RATE GENER-

ATORS

.

Crystal oscillator input

Single-phase TTL clock input

DIRECTLY ADDRESSABLE REGISTERS

(all control registers are read/write)

DATA RATE IN SYNCHRONOUS OR ASYN-

CHRONOUS MODES

-

1

-

.

PDIP48

(Plastic Package)

.

0-1.25M bits/second with 5.0MHz system

clock rate

-

.

SELF-TEST CAPABILITY

RECEIVE DATA REGISTERS ARE QUADRU-

PLY BUFFERED ; TRANSMIT REGISTERS

ARE DOUBLY BUFFERED

DAISY-CHAIN PRIORITY INTERRUPT LOGIC

PROVIDESAUTOMATIC INTERRUPT VECTO-

RING WITHOUT EXTERNAL LOGIC

MODEM STATUS CAN BE MONITORED

PLCC52

(Chip Carrier)

.

DESCRIPTION

Separate modem controls for each channel

ASYNCHRONOUS FEATURES

-

The MK68564 SIO (Serial Input Output) is a dual-

channel, multi-function peripheral circuit, designed

to satisfy a wide variety of serial data communica-

tions requirements in microcomputer systems. Its

basicfunction is a serial-to-parallel, parallel-to-serial

converter/controller ; however within that role, it is

systems software configurable sothat its ”persona-

lity” may be optimized for any given serial data

communications application.

.

5, 6, 7, or 8 bits/character

1, 11/2, or 2 stop bits

Even, odd, or no parity

x1, x16, x32, and x64 clock modes

Break generation and detection

Parity, overrun, and framing error detection

-

.

BYTE SYNCHRONOUS FEATURES

Internal or external character synchronization

One or two sync characters in separate regis-

ters

-

The MK68564 is capable of handling asynchronous

protocols, synchronous byte-oriented protocols

(such as IBMBisync), and synchronous bit-oriented

protocols (such as HDLC and IBM SDLC). This ver-

satile device can also be used to support virtually

any serial protocol for applications other than data

communications (cassette or floppy disk interface,

for example).

-

Automatic sync character insertion

CDC-16 or CRC-CCITT block check genera-

tion and checking

-

BIT SYNCHRONOUS FEATURES

Abort sequence generation and detection

Automatic zero insertion and deletion

Automatic flag insertion between messages

Address field recognition

I-field residue handling

Valid receive messages protected from over-

run

-

The MK68564 can generate and check CRC codes

in any synchronous mode and may be programmed

to check data integrity in various modes. The device

also has facilities for modem controls in each chan-

nel. In applications where these controls are not

needed,the modem controls may be used forgene-

ral-purpose I/O.

-

CRC-16 or CRC-CCITT block check genera-

tion and checking

-

1/46

January 1989

MK68564

SIO PIN DESCRIPTION

GND :

V_CC

Ground

:

+ 5 Volts (± 5%)

CS :

Chip Select (input, active low). CS is used to select the MK68564 SIO for accesses to

the internal registers. CS and IACK must not be asserted at the same time.

R/W :

Read/write (input). R/W is the signal from the bus master, indicating wether the current

bus cycle is a Read (high) or Write (low) cycle.

DTACK :

Data Transfer Acknowledge (output, active low, three stateable). DTACK is used to

signal the bus master that data is ready or that data has been accepted by the

MK68564 SIO.

A1-A5 :

D0-D7

Address Bus (inputs). The address bus is used to select one of the internal registers

during a read or write cycle.

Data Bus (bidirectional, threee-stateable). The data bus is used to transfer data to or

from the internal registers during a read or write cycle. It is also used to pass a vector

during an interrupt acknowledge cycle.

CLK :

Clock (input). This input is used to provide the internal timing for the MK68564 SIO.

RESET :

Device Reset (input, active low). RESET disables both receivers and transmitters, forces

TxDA and TxDB to a marking condition, forces the modem controls high and disables

all interrupts. With the exception of the status registers, data registers, and the vector

register, all internal registers are cleared. The vector register is reset to ”0FH”.

INTR :

IACK :

Interrupt Request (output, active low, open drain). INTR is asserted when the MK68564

SIO is requesting an interrupt. INTR is negated during an interrupt acknowledge cycle

or by clearing the pending interrupt(s) through software.

Interrupt acknowledge (input, active low). IACK is used to signal the MK68564 SIO that

the CPU is acknowledging an interrupt. CS and IACK must not be asserted at the same

time.

IEI :

Interrupt Enable In (input, active low). IEI is used to signal the MK68564 SIO that no

higher priority device is requesting interrupt service.

IEO :

Interrupt Enable Out (output, active low). IEO is used to signal lower priority peripherals

that neither the MK68564 SIO nor another higher priority peripheral is requesting

interrupt service.

XTAL1, XTAL2 :

Baud Rate Generator inputs. A crystal may be connected between XTAL1 and XTAL2,

or XTAL1 may be driven with a TTL level clock. When using a crystal, external

capacitors must be connectd. When driving XTAL1 with a TTL level clock, XTAL2 must

be allowed to float.

RxRDYA, RxRDYB:

TxRDYA, TxRDYB :

CTSA, CTSB :

Receiver Ready (outputs, active low). Programmable DMA output for the receiver. The

RxRDY pins pulse low when a character is available in the receive buffer.

Transmitter Ready (outputs, active low). Programmable DMA output for the transmitter.

The TxRDY pins pulse low when the transmit buffer is empty.

Clear to Send (inputs, active low). If Tx Auto Enables is selected, these inputs enable

the transmitter of their respective channels. If Tx Auto Enables is not selected, these

inputs may be used as general purpose input pins. The inputs are Scmit-trigger

buffered to allow slow rise-time input signals.

DCDA, DCDB :

Data Carrier Detect (inputs, active low). If Rx Auto Enables is selected, these inputs

enable the receiver of their respective channels. If Rx Auto Enables is not selected,

these inputs may be used as general purpose input pins. The inputs are Schmit-trigger

buffered to allow slow rise-time input signals.

RxDA, RxDB :

TxDA, TxDB :

Receive Data (inputs, active high). Serial data input to the receiver.

Transmit Data (outputs, active high). Serial data output of the transmitter.

2/46

MK68564

SIO PIN DESCRIPTION (continued)

RxCA, RxCB :

TxCA, TxCB :

RTSA, RTSB :

Receiver Clocks (input/output). Programmable pin, receive clock input, or baud rate

generator output. The inputs are Schmit-trigger buffered to allow slow rise-time input

signals.

Transmitter Clocks (input/output). Programmable pin, transmit clock input, or baud rate

generator output. The inputs are Schmit-trigger buffered to allow slow rise-time input

signals.

Request to Send (outputs, active low). These outputs follow the inverted state

programmed into the RTS bit. When the RTS bit is reset in the asynchronous mode, the

output will not change until the character in the transmitter is completely shifted out.

These pins may be used as general purpose outputs.

DTRA, DTRB :

Data Terminal Ready (outputs, Active low). These outputs follow the inverted state

programmed into the DTR bit. These pins may also be used as general purpose

outputs.

SYNCA, SYNCB :

Synchronization (input/output, active low). The SYNC pin is an output when Monosync,

Bisync, or SDLC mode is programmed. It is asserted when a sync/flag character is

detected by the receiver. The SYNC pin is a general purpose input in the Asynchronous

mode and an input to the receiver in the External Sync Mode.

Figure 1a : Dual In Line Pin Configuration.

Figure 1b : Chip Carrier Pin Configuration.

3/46

MK68564

SIO SYSTEM INTERFACE

INTERRUPT SEQUENCE

The SIO is designed to operate as an independent,

interrupting peripheral, or, when interconnected

with other components, an interrupt priority daisy

chain can be formed.

INTRODUCTION

The MK68564 SIO is designed for simple and effi-

cient interface to a MK68000 CPU system. All data

transfers between the SIO and the CPU are asyn-

chronous to the system clock. The SIO system

timing is derived from the chip select input (CS) du-

ring normal read and write sequences, and from the

interrupt acknowledge input (IACK) during an ex-

ception processing sequence. CS is a function of

address decode and (normally) lower data strobe

(LDS). IACK is afunction oftheinterrupt levelon ad-

dress lines A1, A2, and A3, an interrupt acknow-

ledge function code (FC0-FC2), and LDS.

Independent Operation. Independent operation

requires that the interrupt enable in pin (IEI) be

connected to ground. The SIO starts the interrupt

sequence bydriving the interrupt requestpin (INTR)

low. The CPU responds to the interrupt by starting

an interrupt acknowledge cycle, in which the SIO

IACK pin is driven low. The highest priority interrupt

request intheSIO,atthetimeIACKgoeslow, places

itsvectoron the data bus pins. The SIO releases the

INTRpinanddrivesDTACK low.WhentheCPUhas

acquired the vector, the IACK signal is driven high.

The SIO responds by driving DTACK to a high level

and then three-stating DTACK and D0-D7. If more

than one interrupt request is pending at the start of

an interrupt acknowledge sequence, the SIO will

drive the INTR pin low following the completion of

the interrupt acknowledge cycle. This sequence will

continue until all pending interrupts are cleared. If

the SIO is not requesting an interrupt when IACK

goes low,the SIO will notrespond totheIACKsignal

; DTACK and the data bus will remain three-stated.

Note : CS and IACK can never be asserted at the

same time.

Note : Unused inputs should be pulled up or down,

but never left floating.

READ SEQUENCE

The SIOwill begin a read cycleif, on thefalling edge

of CS, the read-write (R/W) pin is high. The SIO will

respond by decoding the address bus (A1-A5) for

the register selected, by placing the contents of that

register on thedatabuspins (D0-D7), and by driving

the data transfer acknowledge (DTACK) pin low. If

the register selected is not implemented on the SIO,

the data bus pins will be driven high, and then

DTACK will be asserted. When the CPU has acqui-

red the data, the CS signal is driven high, at which

time the SIO will drive DTACK high and then three-

state DTACK and D0-D7.

Daisy Chain Operation. Theinterrupt priority chain

is formed by connecting the interrupt enable out pin

(IEO) of a higher priority part to IEI of the next lower

priority part. The highest priority part in the chain

should have IEI tied to ground. The Daisy Chaining

capability (figures 2 and 3) requires that all parts in

a chain have a common IACK signal. When the

common IACK goes low, all parts freeze and priori-

tize interrupts in parallel. Then priority is passed

down the chain, via IEI and IEO, until a part which

has a pending interrupt, once IEI goes low, passes

a vector, does not propagate IEO, and generates

DTACK.

WRITE SEQUENCE

The SIOwillbegin awrite cycleif, onthefalling edge

of CS, the R/W pin is low. The SIO will respond by

latching the data bus, by decoding the address bus

for the register selected, by loading the register with

the contents of the data bus, and by driving DTACK

low. When the CPU has finished the cycle, the CS

input is driven high. At this time, the SIO will drive

DTACK high and will then three-state DTACK. If the

register selected is not implemented on the SIO, the

normal write sequence will proceed, but the data

bus contents will not be stored.

The state of the IEI pin does not affect the SIO in-

terrupt control logic. The SIOcan generate an inter-

rupt request any time its interrupts are enabled. The

IEO pin is normally high ; it will only go low during

an IACK cycleifIEI is low andno interrupt is pending

in the SIO. The IEO pin willbe forced high whenever

IACK or IEI goes high.

4/46

MK68564

Figure 2 : Conceptual Circuit of the MK68564 SIO Daisy Chaining Logic.

V000376

Figure 3 : Daisy Chaining.

V000377

Figure 4 : DMA Interface Timing.

V000378

5/46

MK68564

DMA INTERFACE

ARCHITECTURE

The MK68564 SIO contains two independent, full-

duplex channels. Each channel contains a transmit-

ter, receiver, modem control logic, interrupt control

logic, a baud rate generator, ten Read/Write regis-

ters, and two read only status registers. Each chan-

nel can communicate with the bus master using pol-

ling, interrupts, DMA, or any combination of these

three techniques. Each channel also has the ability

to connect thetransmitter output intothereceiver wi-

thout disturbing any external hardware.

The SIO is designed to interface to the 68000 family

DMA’s as a 68000 compatible device, using the cy-

cle steal mode. The SIO provides four outputs

(TxRDYA, RxRDYA, TxRDYB, RxRDYB) for re-

questing servicefrom theDMA.The SIOissues are-

questforservice bypulsing the RDYpinlowfor three

clock (CLK) cycles(see figure 4). TxRDY(when en-

abled) will be active when the transmit buffer be-

comesempty. RxRDY(when enabled) will be active

when a character is available in the receive buffer.

If Receive Interrupt On First Character Only is en-

abledduring aDMA operation and aspecial receive

condition is detected, the RxRDY pin will not be-

come active. Instead, a special receive condition in-

terrupt will be generated by the channel.

Register Set. The register set is the heart of each

channel. A channel is configured for different

communication protocols and interface options by

programming the registers. Table 1 lists all the re-

gisters available in the SIO and their addresses.

Data Register. The Data Register is composed of

two separate registers : a write only register, which

is the Transmit Buffer, and a read only register,

which is the Receive Buffer. The Receive Buffer is

also the top register of a three register stack called

the receive data FIFO.

RESET

There are two ways of resetting the SIO : an indivi-

dual, programmable channel reset and an external

hardware reset.

The individual channel reset is generated by writing

”18H” to the Command Register for the channel se-

lected. All outputs associated with the channel are

resethigh, TxC and RxC areinputs, SYNC isan out-

put, and TxD is forced marking. All R/W registers for

the channel are reset to ”00H”, except thevector re-

gister and the data register, which are not affected.

Vector Register. The Vector Register is different

from the other 24 registers, because it may be ac-

cessed through either Channel A or Channel B du-

ring a R/W cycle. During an Interrupt Acknowledge

cycle, the contents of the Vector Register are pas-

sedto theCPUto be usedas apointer toaninterrupt

serviceroutine. IftheStatus AffectsVector bit isLow

in the Interrupt Control Register, any data written to

the Vector Register will be returned unmodified du-

ring a Read Cycleor an IACK cycle. If the Status Af-

fects Vector bit is High, the lower three bits of the

vectorreturned during aRead orIACKcyclearemo-

dified to reflect the highest priority interrupt pending

in the SIO at that time. The upper five bits written to

theVector Register areunaffected. Afterahardware

reset only, this register contains a ”0FH” value,

which is the MK68000’s uninitialized interrupt vector

assignment.

Readonly status register 1isreset to”01H” (All Sent

set). Break/Abort, Interrupt Pending, and Rx Char-

acter Available bits in read only status register 0 are

reset ; Underrun/EOM, Hunt/Sync, and Tx Buffer

Empty are set ; CTS and DCD bits are set to the in-

verted state of their respective input pins. Any inter-

ruptspending for the channel are reset (any pending

interrupts in the other channel will not be affected).

An externalhardware reset occurswhen the RESET

pin is driven low for at least one clock (CLK) cycle.

Both channels are reset as listed above, and the

vector register is reset to ”0FH”.

6/46

MK68564

Figure 5 : Register Bit Functions.

7/46

MK68564

SIO INTERNAL REGISTERS

The MK68564 SIO has 25 internal registers. Each channel has ten R/W registers and tworead only registers

associated with it. The vector register may be accessed through either channel.

Table 1 : Register Map.

Address

Access

Abbreviation

Channel

Register Name

5

4

3

2

1

Read/

write

Read

Only

A

Command Register

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

CMDREG

MODECTL

INTCTL

Mode Control Register

Interrupt Control Register

Sync Word Register 1

Sync Word Register 2

Receiver Control Register

Transmitter Control Register

Status Register 0

A

SYNC 1

SYNC 2

RCVCTL

XMTCTL

STAT 0

A

X

STAT 1

A

Status Register 1

DATARG

TCREG

A

Data Register

X

A

Time Constant Register

Baud Rate Generator Control Reg

Interrupt Vector Register (note 2)

(note 1)

BRGCTL

VECTRG

A

A/B

A

(note 1)

A

(note 1)

CMDREG

MODECTL

INTCTL

B

Command Register

Mode Control Register

Interrupt Control Register

Sync Word Register 1

Sync Word Register 2

Receiver Control Register

Transmitter Control Register

Status Register 0

B

SYNC 1

SYNC 2

RCVCTL

XMTCTL

STAT 0

B

X

STAT 1

B

Status Register 1

DATARG

TCREG

B

Data Register

X

Time Constant Register

Baud Rate Generator Control Reg

Interrupt Vector Register (note 2)

(note 1)

B

BRGCTL

VECTRG

B

A/B

B

(note 1)

B

(note 1)

Notes : 1. Not Used, Read as ”FFH”.

2. Only One Vector Register, Accessible through Either Channel.

8/46

MK68564

Figure 6 : Transmit and Receive Data Paths.

V000379

9/46

MK68564

DATA PATH

zero deletion when indicated. Upon receiving five

contiguous ones, the sixth bit is inspected. If the

sixth bit is a 0, it is deleted from the data stream. If

the sixth bit is a 1, the seventh bit is inspected. If the

seventh bit is a 0, a Flag sequence has been recei-

ved ; if the seventh bit is a 1,an Abort sequence has

been received.

The transmit and receive data paths for each chan-

nel are shown in figure 6. The receiver has three

8-bit buffer registers in a FIFO arrangement (to pro-

vide a 3-byte delay) in addition to the 8-bit receive

shift register. This arrangement creates additional

time for the CPU to service an interrupt at the begin-

ning of a block of high-speed data. The receiver er-

ror FIFO stores parity and framing errors and other

types of status information for each of the three

bytes in the receive data FIFO. The receive error FI-

FO is loaded at the same time as the receive data

FIFO. The contents of the receive error are read

through the upper four bits in Status Register 1.

Incoming data is routed through one of several

paths, depending onthemodeand characterlength.

In the Asynchronous modes, serial data is entered

into the 3-bit buffer, if it has a character length of se-

ven or eight bits, or the data is entered into the 8-bit

receive shift register, if it has a length of five or six

bits.

The reformatted data from the receive sync register

enters the 3-bit buffer and is transferred to the re-

ceiveshift register. Note that the SDLCreceive ope-

ration also begins in the Hunt Phase, during which

timethe SIO tries to match theassembled character

in the receive sync register with the flag pattern in

Sync Word Register 2. Once the first flag character

is recognized, all subsequent data isrouted through

the path described above, regardless of character

length.

Although the same CRC checker is used for both

SDLC and synchronous data, the path taken for

each mode is different. In Bisync protocol, the byte-

oriented operation requires that the CPU decide

whether or not to include the data character in the

CRC calculation. To allow the CPU ample time to

make this decision, the SIO provides an 8-bit delay

before the data enters the CRC checker. In the

SDLC mode, no delay is provided, since CRCis cal-

culated on all data between theopening and closing

flags.

In the Synchronous mode, the data path is determi-

ned by the phase of the receive process currently in

operation. A Synchronous Receive operation be-

gins with the receiver in the Hunt phase, during

which time the receiver searches the incoming data

stream for a bit pattern that matches the prepro-

grammed sync characters (or flags in the SDLC

mode). If the device is programmed for Monosync

Hunt, a match is made with a single sync character

stored in Sync Word Register 2. In Bisync Hunt, a

match is made with the dual sync characters stored

in Sync Word Registers 1 and 2. In either case, the

incoming data passes through the receive sync re-

gister and is compared against the programmed

sync characters in SyncWord Registers 1 and 2.

The transmitter has an 8-bit transmit data register,

which is loaded from the internal bus, and a 20-bit

transmit shift register, which can be loaded from

Sync Word Register 1, Sync Word Register 2, and

the transmit data register. Sync Word Registers 1

and 2 contain sync characters in the Monosync, Bi-

sync,or External Sync modes, or address field (one

character long) and flag, respectively, in the SDLC

mode. During Synchronous modes, information

contained in Sync Word Registers 1 and 2 is loaded

intothe transmit shift register at the beginning of the

message and, as a time filler, in the middle of the

message if a Transmit Underrun condition occurs.

In SDLCmode, theflags areloaded intothe transmit

shift register at the beginning and end of the mes-

sage.

In the Monosync mode, a match between the sync

character programmed into Sync Word Register 2

and the character assembled in thereceive sync re-

gister establishes synchronization.

In the Bysync mode, incoming data is shifted to the

receive shift register, while the next eight bits of the

message are assembled in the receive sync regis-

ter. The match between the assembled character in

the sync register and the programmed character in

Sync Word Register 2, and between the character

in the shift register and the programmed character

in Sync Word Register 1 establishes synchroniza-

tion. Once synchronization is established, incoming

data bypasses the receive sync register and directly

enters the 3-bit buffer.

Asynchronous data in the transmit shift register is

formattedwith startand stopbits, and it isshiftedout

to thetransmit multiplexer at the selected clockrate.

Synchronous (Monosync, Bisync, or External Sync)

data is shifted out to the transmit multiplexer and al-

so the CRC generator at the x1 clock rate.

SDLC/HDLC data is shifted out through the zero in-

sertion logic, which is disabled while flags are being

sent. Forallotherfields (address, control, and frame

check), a0isinserted followingfive contiguous ones

In the SDLC mode, all incoming data passes

throughthereceive sync register,which continuous-

ly monitors the receive data stream and performs

10/46

MK68564

in the data stream. Note that the CRC generator re-

sult (frame check) for SDLC data is also routed

through the zero insertion logic.

canbecome empty. When enabled, the receiver can

interrupt the CPU in one of three ways :

Interrupt On First Character Only

Interrupt On All Receive Characters

Interrupt On A Special Receive Condition.

I/O CAPABILITIES

The SIO offers the choice of Polling, Interrupt (vec-

tored or non-vectored), and DMATransfer modesto

transfer data, status, and control information to and

from the CPU or other bus master.

Interrupt On First Character Only.This mode is

normally used to start a software Polling loop or a

DMA transfer routine using the RxRDY pin. In this

mode, the SIO generates an interrupt on the first

character received after this mode is selected and,

thereafter, only generates an interrupt if a Special

Receive Condition occurs. The Special Receive

Conditions that can cause an interrupt in this mode

are : Rx Overrun Error, Framing Error (in Asynchro-

nous modes), and End Of Frame (in SDLC mode).

This mode is reinitialized by the Enable Interrupt On

Next Rx Character command. If a Special Receive

Condition interrupt occurs in this interrupt mode, the

data with the special condition is held in the receive

data FIFO until an Error Reset Command is issued.

Polling. The Polled mode avoids interrupts. Status

Registers 0 and 1 are updated at appropriate times

for each function being performed (for example,

CRC Error status valid at the end of the message).

All the interrupt modes of the SIO must be

disabled to operate the device in a polled environ-

ment.

While initsPolling sequence, theCPUexamines the

status contained in Status Register 0 for each chan-

nel. The state of the status bits in Status Register 0

servesas an acknowledge to thePoll inquiry. Status

bits D0and D2 indicatethat a receive ortransmit da-

ta transfer is needed. The rest of the status bits in

Status Register 0 indicate special statusconditions.

The receiver error condition bits in Status Register

1 donothave to be read until the RxCharacter Avai-

lable status bit in Status Register 0 is set to a one.

InterruptOnAll Receive Characters. Inthismode,

an interrupt is generated whenever thereceive data

FIFO contains a character or a Special Receive

Condition occurs. The Special Receive Conditions

that can cause an interrupt in this mode are : Rx O-

verrun Error, Framing Error (in Asynchronous

modes), End of Frame (in SDLC mode), and Parity

Error (if selected).

Interrupts. The SIO offers an elaborate interrupt

scheme to provide fast interrupt response in real-

time applications. The interrupt vector points to an

interrupt service routine in the memory. To service

operations inboth channels and to eliminate the ne-

cessity of writing a status analysis routine (as requi-

red fora polling scheme), the SIO can modify the in-

terrupt vector soitpoints to one of eight interrupt ser-

viceroutines. This is done under program control by

setting the Status Affects Vector bit in the Interrupt

Control Register ofchannel Aor channel B,to aone.

When this bit is set, the interrupt vector is modified

according to the assigned priority of the various in-

terrupting conditions.

Interrupt On A Special Receive Condition. The

Special Receive Condition interrupt is not, as such,

a separate interrupt mode. Before a Special Re-

ceiveCondition can cause aninterrupt, either theIn-

terrupt On First Character Only or Interrupt On All

Receive Characters mode must be selected. The

Special Receive Condition interrupt will modify the

receive interrupt vectorif Status AffectsVector isen-

abled. The Special Receive Condition status is dis-

played in the upper four bits of Status Register 1.

Two of the conditions causing a special receive in-

terrupt arelatched when they occur;they are: Parity

Error and Rx Overrun Error. These status bits may

only be reset by an Error Reset command. When ei-

ther of these conditions occur, a read of Status Re-

gister 1 will reflect any errors in the current word in

the receive buffer plus any parity or overrun errors

since the last Error Reset command was issued.

Note : If the Status Affects Vector bit is set in either

channel, the vector is modified for both channels.

This is the only control bit that operates in this man-

ner in the SIO.

Transmit interrupts, Receive interrupts, and Exter-

nal/Status interrupts are the sources of interrupts.

Each interrupt source is enabled under program

control with Channel A having a higher priority than

Channel B, and with Receiver, Transmitter, and Ex-

ternal/Status interrupts prioritized in thatorder within

each channel. When the Transmit interrupt is en-

abled, the CPU is interrupted by the transmit buffer

becoming empty. This implies that the transmitter

must have had a data character written into it so t

External/Status Interrupts. The main function of

the External/Status interrupt is to monitor the signal

transitions of the CTS, DCD, and SYNC pins ; how-

ever, an External/Status interrupt is also caused by

a Transmit Underrun condition orby the detection of

a Break (Asynchronous mode) or Abort (SDLC

mode)sequence in thereceived data stream. When

any one of the above conditions occur, the exter-

11/46

MK68564

nal/status logiclatches the current stateof all fivein-

put conditions, and generates an interrupt. To reini-

tialize the external/status logic to detect another

transition, a Reset External/Status Interrupts

command must be issued. The Break/Abort condi-

tionallows the SIO togenerate aninterrupt when the

Break/Abort sequence is detected and terminated.

This feature facilitates the proper termination of the

current message, correct initialization of the next

message, and the accurate timing of the Break/A-

bort condition in external logic.

SELF TEST

When the Loop Mode bit is set in theCommand Re-

gister,thereceiver shiftclockinputpin (RxC) and the

receiver data input pin (RxD) are electrically dis-

connected from the internal logic. The transmit data

output pin (TxD) is connected to the internal

receiver data logic, and the transmit shift clock pin

(TxC)isconnected to theinternal receiver shiftclock

logic. All other features of the SIO are unaffected.

BAUD RATE GENERATORS

Each channel in the SIO contains a programmable

baud rate generator (BRG). Each BRG consists of

an 8-bit time constant register, an 8-bit down coun-

ter, a control register, and a flip-flop on the output to

provide a square wave signal out. In addition to the

flip-flop on the output, there is also a flip-flop on the

input clock; therefore, themaximum outputfrequen-

cy of theBRG isone-forth of theinput clock frequen-

cy. This maximum output frequency occurs when

divide by four mode is selected, and the time

constant register is loaded with the minimum count

of ”01H”. The equation to determine the output fre-

quency is :

DMA Transfer

The SIOprovides two output signals per channel for

connection to a DMA controller ; they are TxRDY

and RxRDY. The outputs are enabled under soft-

ware control by writing to the Interrupt Control Re-

gister. Both outputs will pulse Low for three system

clock cycles when their input conditions are active.

TxRDY will be active when the Transmit Buffer

becomesempty. RxRDY will be active when achar-

acter is available in the Receive Buffer. If a Special

Receive Condition occurs when Interrupt On First

Character Only mode is selected, a receiver inter-

rupt will be generated and RxRDY will not become

active. This will automatically inform the CPU of a

discrepancy in the data transfer.

Output

Input Frequency

=

Frequency (divide by selected) X (time constant

value in decimal)

Figure 7 : Interrupt Structure.

V000380

12/46

MK68564

For example, when the time constant register is loa-

ded with ”01H” and divide by four is selected, one

output clock will occur for every four input clocks. If

the time constant value loaded is ”00H” (256 deci-

mal) instead of ”01H” and divide by 64 is selected,

one output clock will occur for every 16384 input

clocks. Note that the minimum count value is ”01H”

(1 decimal), and the maximum count value is ”00H”

(256 decimal).

To set up the SIO for Asynchronous operation, the

following registers need to be initialized : Mode

Control Register, Interrupt Control Register, Recei-

ver Control Register, and Transmitter Control

Register. The Mode Control Register must be

programmed before the other registers to assure

proper operation of the SIO. The following registers

are used to transfer data or to communicate status

between the SIO and the CPU or other bus master

when operating in Asynchronous modes

Command Register, Status Register 0, Status Re-

gister 1, Data Register, and the Vector Register.

:

The output of the baud rate generator may be pro-

grammed to drive the transmitter (BRG output on

TxC), the receiver (BRG output on RxC), both (BRG

output on TxC and RxC), or neither (TxC and RxC

are inputs). After a reset, the baud rate generator is

disabled, divide by four is selected, and TxC and

RxC are inputs.

Table 2 : Time-Constant Values.

Rate

Time Constant Divide By

Error

19200

9600

7200

4800

3600

2400

2000

1800

1200

6 0 0

4 8

9 6

128

192

256

2 4

2 9

3 2

4 8

9 6

4

64

The baud rate generator should be disabled before

the CPU writes to the time constant register. This is

necessary because no attempt was made to syn-

chronize the loading of anew time constant with the

clock used to drive the BRG.

69 %

Figure 8 indicates the externalcomponents needed

to connect a crystal oscillator to the SIO XTAL in-

puts.The allowed crystalparameters are alsolisted.

3 0 0

192

For a 3.6864MHz input signal to the baud rate ge-

nerator, thetime constants, listed in table 2, are loa-

ded to obtain the desired baud rates (in x1 clock

mode).

Figure 8 :

SIO External Oscillator Components.

ASYNCHRONOUS OPERATION

INTRODUCTION

Many types of Asynchronous operations are perfor-

med by the MK68564 SIO. Figure 9 represents aty-

pical Asynchronous message format and some of

the options available on the SIO. The transmit pro-

cess inserts start, stop, and parity bits to a variable

data format and supplies a serial data stream to the

Transmit Data output (TxD). The receiver takes the

data from the Receive Data input (RxD) and strips

away expected start and stop bits at a programmed

clockrate. Itprovides error checking for overrun, pa-

rity, and carrier-loss errors, and, if desired, provides

interrupts for these conditions.

CRYSTAL PARAMETERS :

ParallelResonance, FundamentalMode AT Cut

Rs â 150Ω (Fr = 2.8 - 5.0MHz)

Rs â 300Ω (Fr = 2.0 - 2.7MHz)

CI = 18pf ; Cm = 0.02pF ; Ch = 5pF ; Lm = 96MHz

Fr (typ) = 2.457MHz

13/46

MK68564

Figure 9 : Asynchronous Message Format.

V000382

The SIO provides five I/O lines that maybe used for

modemcontrol, for external interrupts, oras general

purpose I/O. The Request To Send (RTS) and Data

Terminal Ready (DTR) pins are outputs that follow

the inverted state of their respective bits in the

Transmitter Control Register. The RTS pin can also

be usedto signal theend of amessage inAsynchro-

nous modes, as explained below in the transmitter

section. The Data Carrier Detect (DCD), Clear To

Send (CTS), and SYNC pins are inputs to the SIO

in Asynchronous modes. DCD and CTS can be u-

sed as auto enables to the receiver and transmitter,

respectively, or if External/Status Interrupts are en-

abled all three input pins will be monitored for a

change of status. If these inputs change fora period

of time greater than the minimum specified pulse

width, an interrupt will be generated.

Transmit Characteristics. The SIO automatically

inserts astartbit, the programmed parity bit (odd, e-

ven, or no parity), and the programmed number of

stopbits tothe data character to be transmitted. The

transmitter can transmit from one to eight data bits

per character. All characters are transmitted least-

significant bit first. When the character length pro-

grammed is six or seven bits, the unused bits of the

transmit buffer are automatically ignored. When a

character length of five bits or less is programmed,

the data loaded into the transmit buffer must be for-

matted as described in the Transmitter Control Re-

gister part of theRegister Description section. Serial

data is shifted out of the TxD pin on the falling edge

of the Transmit Clock (TxC) at a rate equal to 1,

1/16th, 1/32nd, or 1/64th of TxC.

Data Transfer. TheSIO will signal the CPU orother

bus master with a transmit interrupt request and set

the Tx Buffer Empty bit in Status Register 0, every

time the contents of the transmit buffer are loaded

into the transmit shift register. The interrupt request

will be cleared when a new character is loaded into

the transmit buffer, or a Reset Tx Interrupt Pending

command (Command 5) is issued. If Command 5 is

issued, the transmit buffer will have to be loaded be-

fore any additional transmit interrupt requests are

generated. The Tx Buffer Empty bit is reset when a

new character is loaded into the transmit buffer.

In the following discussion, all interrupt modes are

assumed enabled.

ASYNCHRONOUS TRANSMIT

Start of Transmission. The SIO will start transmit-

ting data when the Transmit Enable bit is set to a

one, and acharacter has been loaded intothe trans-

mit buffer. If the TxAuto Enables bit is set, the SIO

willwait for a Low on the Clear ToSend input (CTS)

before starting data transmission. The Tx Auto En-

ables feature allows the programmer to send the

first data character of the message to the SIO wi-

thout waiting for CTS to go Low. In all cases, the

Transmit Enable bit mustbe set before transmission

can begin. The transitions on the CTS pin will gene-

rate External/Status interrupt requests and also

latch up the external/status logic. The external/sta-

tus logic should be rearmed by issuing a Reset Ex-

ternal/Status Interrupts command.

The All Sent bit in Status Register 1 is used to indi-

cate when all data in the shift register has been

transmitted, and thetransmitbufferisempty. This bit

is Low, while the transmitter is sending characters,

and itwillgoHigh one bittimeafterthetransmit clock

that clocks out the last stop bit of the character on

the TxD pin. No interrupts are generated by the All

Sent bit transitions. The Request To Send (RTS) bit

14/46

MK68564

in the Transmitter Control Register may also be u-

sed to signal the end of transmission. If this bit is set

to aone,its associated output pin (RTS)willgo Low.

When this bit is reset to a zero, the RTS pin will go

High one bit time after the transmit clock that clocks

out thelaststop bit, onlyifthetransmit buffer isemp-

ty.

Character Available bit is reset to a zero when the

receive buffer is read.

Aftera character is received, itis checked forthe fol-

lowing error conditions :

Parity Error. Ifparity is enabled, the Parity Error bit

in Status Register 1 is setto a one whenever thepa-

rity bit of the received character does not match the

programmed parity. Once this bit is set, it remains

set (latched), until an Error Reset command

(Command 6) is issued. A Special Receive Condi-

tioninterrupt is generated when thisbitisset,if parity

is programmed as a Special Receive Condition.

The Transmit Data output (TxD) is held marking

(High) after a reset or when the transmitter has no

data to send. Under program control, the Send

Break command can be issued to hold TxD spacing

(Low) until the command is cleared, even if the

transmitter is not enabled.

Framing Error. The CRC/Framing Error bit in Sta-

tus Register 1 is set to a one, if the character is as-

sembled withoutastopbit (a Low level detected ins-

teadofastopbit). Thisbit isset only forthecharacter

on which the framing error occurred ; it is updated

at everycharacter time. Detection of aframing error

adds an additional one-half of a bit time to the char-

acter time, so the framing error is not interpreted as

a new startbit. ASpecial ReceiveCondition interrupt

is generated when this bit is set..

ASYNCHRONOUS RECEIVE

Asynchronous operation begins when the Receiver

Enable bit in the Receiver Control Register is set to

a one. If the Rx Auto Enables bit isalso set, the Data

Carrier Detect (DCD) input pin must be Low as well.

The receiver will start assembling a character as

soon as a valid start bit is detected, if a clock mode

other than x1 is selected. A valid start bit is a High-

to-Low transition on the Receive Data input (RxD)

with the Low time lasting at least one-half bit time.

The High-to-Low transition startsan internal counter

and, at mid-bit time, the counter output is used to

sample the input signal to detect if it is still Low.

When this condition is satisfied, the following data

bits are sampled at mid-bit timeuntil theentirechar-

acter is assembled. The start bit detection logic is

then rearmed to detect the next High-to-Low trans-

ition. If thex1 clock mode isselected, the start bitde-

tection logic is disabled, and bit synchronization

must be accomplished externally. Receive data is

sampled on the rising edge of the Receiver Clock

(RxC).

Overrun Error. If four or more characters are recei-

ved before the CPU (or other bus master) reads the

receive buffer, the fourth character assembled will

replace the third character in the receive data FIFO.

If morethan four characters have beenreceived,the

last character assembled will replace the third char-

acter in the data FIFO. The character that has been

written over is flagged with an overrun error in the

error FIFO.

When this character is shifted to the top of the re-

ceive data FIFO, the Receive Overrun Error bit in

Status Register 1 is set to a one ; the error bit is lat-

ched in the status register, and a Special Receive

Condition interrupt is generated. Like Parity Error,

this bit can only be reset by an Error Reset

Command.

The receiver may be programmed to assemble five

to eight data bits, plus a parity bit, into a character.

The character is right-justified in the shift register

and thentransferredtothe receive dataFIFO. All da-

ta transfers to the FIFO are in eight-bit groups. Ifthe

character length assembled is less than eight bits,

the receiver inserts ones in the unused bits. If parity

is enabled, the parity bit is transferred with the char-

acter, unless eight bits per character is program-

med, inwhich case, the parity bit is stripped from the

character before transfer.

Break Condition. A break character is defined as

a start bit, an all zero data word, and a zero in place

of the stop bit. When a break character is detected

in the receive data stream, the Break/Abort bit in

Status Register 0 is set to a one, and an Exter-

nal/Status interrupt is requested. This interrupt is

then followed by a Framing Error interrupt request

when the CRC/Framing Error bit in Status Register

1 is set. A Reset External/Status Interrupts

command (Command 2) should be issued to reini-

tialize the break detection interrupt logic. The recei-

ver will monitor the data stream input for the termi-

nation of the break sequence. When this condition

is detected, the Break/Abort bit will be reset, if

A Receiver Interrupt request isgenerated everytime

a character is shifted to the top of the receive data

FIFO, if Interrupt On All Receive Characters mode

is selected. The Rx Character Available bit in Status

Register 0is also set to aone every time acharacter

is shifted tothe top of thereceive data FIFO. The Rx

15/46

MK68564

Command 2 has been issued, and another Exter-

nal/Status interrupt request will be generated. This

interrupt should also be handled by issuing

Command 2 to reinitialize the external/status logic.

At the end of the break sequence, asinglenull char-

acter will be left in the receive data FIFO. This char-

acter should be read and discarded.

mode), the transmitter transmits the sync character

in Sync Word Register 1.The receiver compares the

single sync character with the programmed sync

character stored in Sync Word Register 2. A match

implies character synchronization and enables data

transfer. The SYNC pin is used as an output in this

mode and is active for the part of the receive clock

that detects the sync character.

Because Parity Error and Receive Overrun Error

flags are latched, the error status that is read from

Status Register 1 reflects an error in the current

word in the receive data FIFO, plus any parity or o-

verrun errors received since the last Error Reset

command. To keep correspondence between the

state of the error FIFO and the contents of the re-

ceive data FIFO, Status Register 1 should be read

before the receive buffer. If the status is read after

the data and more than one character is stacked in

the data FIFO during the read of the receive buffer,

the status flags read will be for the next word. Keep

in mind that whena character is shiftedup to the top

of the data FIFO (the receive buffer), its error flags

are shifted into Status Register 1

BISYNC. IntheBisync mode (16-bit syncmode), the

transmitter transmits the sync character in Sync

Word Register 1 followed by the sync character in

Sync Word Register 2. The receiver compares the

two contiguous sync characters with the program-

med synccharacters stored inSync Word Registers

1 and 2. A match implies character synchronization

and enables data transfer. TheSYNCpin is used as

an output in this mode and is active for the part of

the receive clock that detects the sync characters.

External Sync. In the External Sync mode, the

transmitter transmits the sync character in Sync

Word Register 1. Character synchronization for the

receiver is established externally. The SYNC pin is

an input that indicates that external character syn-

chronization has been achieved. After the sync pat-

tern is detected, the external logic must wait for two

fullReceive Clock cycles toactivate the SYNC input

pin(seefigure 11). TheSYNCinput pinmust be held

Low until character synchronization is lost. Charac-

ter assembly begins on the rising edge of the Re-

ceive Clock that precedes the falling edge of the

SYNC input pin.

.An exception to the normal flow of data through the

receive data FIFO occurs when the Receive Inter-

rupt On First Character Only mode is selected. A

Special Receive Condition interrupt in this mode

holds the error data, and the character itself (even

if read from the data FIFO) until the Error Reset

command (command 6)isissued. This prevents fur-

ther data from becoming available in the receiver,

until Command 6 is issued, and allows CPU inter-

vention on the character with the error even if DMA

or block transfer techniques are being used.

In all cases, afterareset (hardware or software), the

receiver is in the Hunt phase, during which time the

SIO looks for character synchronization. The Hunt

phase can begin only when the receiver is enabled,

and data transfer can begin only when character

synchronization has been achieved. If character

synchronization islost, theHunt phase canbere-en-

tered by setting the Enter Hunt Mode bit in the Re-

ceiver Control Register. In the transmit mode, the

transmitter always sends the programmed number

of syncbits (8 or 16), regardless of the bits perchar-

acter programmed.

In theMonosync, Bisync, and External Sync modes,

assembly of received data continues until the SIO is

reset, or until the receiver is disabled (by command

or theDCD pin inthe RxAuto Enables mode),or un-

til the CPU sets the Enter Hunt Mode bit.

SYNCHRONOUS OPERATION

INTRODUCTION

Before describing byte-oriented, synchronous

transmission and reception, the three typesof char-

acter synchronization - Monosync, Bysync, and Ex-

ternal Sync - require some explanation. These

modes use the x1 clock for both Transmit and Re-

ceiveoperations. Datais sampled onthe rising edge

of the Receive Clock input (RxC). Transmitter data

transitions occur on the falling edge of the Transmit

Clock input (TxC).

The differences between Monosync, Bisync, and

External Sync are in the manner in which initial re-

ceive character synchronization is achieved. The

mode of operation must be selected before sync

characters are loaded, because the registers are u-

sed differently in the various modes. Figure 10

showsthe formats for all three synchronous modes.

After initial synchronization has been achieved, the

operation of the Monosync, Bisync, and External

Sync modes is quite similar. Any differences are

specified in the following text.

To set up the SIO for Synchronous operations, the

following registers need to be initialized : Mode

MONOSYNC. In the Monosync mode (8-bit sync

16/46

MK68564

Control Register, Interrupt Control Register, Recei-

ver Control Register, Transmitter Control Register,

Sync Word 1, and Sync Word 2. The Mode Control

Register must be programmed before other regis-

ters to assure proper operation of the SIO. The fol-

lowing registers are used to transfer data or

communicate status between the SIO and the CPU

or other bus master : Command Register, Status

Register 0, Status Register 1, Data Register, and

the Vector Register.

odd-even or no parity, x1 clock mode, 8- or 16-bit

sync character(s), CRC polynomial, Transmit En-

ables, interrupt modes, and transmit character

length. If Parity is enabled, the transmitter will only

add a parity bit to a character that is loaded into the

transmit buffer ; it will not add a parity bit to theauto-

matically inserted sync character(s) or the CRC

characters.

One of two polynomials may be used with Synchro-

nous modes, CRC-16(X¹⁶+ X¹⁵+ X²+1)orSDLC-

CRC (X¹⁶+ X¹²+ X⁵+ 1). For either polynomial

(SDLC mode not selected), the CRC generator and

checker are reset to all zeros. Both the receiver and

transmitter use the same polynomial.

The SIO provides four I/O lines in Synchronous

modes that may be used for modem control, for ex-

ternalinterrupts, or as general purpose I/O.The Re-

quest To Send (RTS) and Data Terminal Ready

(DTR) pins are outputs that follow the inverted state

of their respective bits in the Transmit Control Re-

gister. The Data Carrier Detect (DCD) and Clear To

Send (CTS) pins areinputs that canbe used as auto

enables to the receiver and transmitter, respective-

ly. If External/Status Interrupts are enabled, the

DCD and CTS pins will be monitored for a change

of status. If these inputs change for a period of time

greater than the minimum specified pulse width, an

interrupt will be generated.

After reset (hardware or software), or when the

transmitter is not enabled, the Transmit Data (TxD)

output pin is held High (marking). Under program

control, theSend Breakbit intheTransmitterControl

Register can be set to a one, forcing the TxD output

pin to a Low level (spacing), even if the transmitter

is notenabled. Thespacing condition willpersist un-

til the Send Break bit is reset to a zero. A program-

med break iseffectiveas soon asit iswritteninto the

Transmit Control Register ; any characters in the

transmit buffer and transmit shift register are lost.

In the following discussion, all interrupt modes are

assumed enabled.

If thetransmit buffer isempty whentheTransmit En-

able bit is set to a one, the transmitter will start sen-

ding 8- or 16-bit sync characters. Continuous syncs

will be transmitted on the TxD output pin, as long as

no data is loaded into the transmit buffer. Note, if a

SYNCHRONOUS TRANSMIT

Initialization. Byte-oriented transmitter programs

are usually initialized with the following parameters :

Figure 10 : Synchronous Formats.

V000383

17/46

MK68564

character is loaded into the transmit buffer before

enabling the transmitter, that character will be sent

in place of the sync character(s).

character length is six or seven bits, the unused bits

in the transmit buffer are ignored. If a word length of

five bits per character or less is selected, the data

loadedinto the transmit buffer must be formatted as

described inthe Transmit Control register partof the

Register Description section.

Start of Transmission. Transmission will begin

with the loading of the first data character into the

transmit buffer, if the transmitter is already enabled.

For CRC to be calculated correctly on each mes-

sage, the CRC generator must be reset to all zeros

before the first data character is loaded into the

transmit buffer. This is accomplished by issuing a

Reset Tx CRC Generator command in the

Command Register.

The number of bits per character to be transmitted

can be changed on the fly. Any data written to the

transmit buffer, after the bits per character field is

changed, are affected by the change. The same is

true of any characters in the buffer at the time the

bits per character field is changed. The change in

the number of bits per character does not affect the

character in the process of being shifted out.

Synchronous Transmit Characteristics. In all

Synchronous modes, characters are sent with the

least-significant bits first. All data isshifted out of the

Transmit Data pin (TxD) on the falling edge of the

Transmit Clock (TxC). The transmitter can transmit

from one to eight data bits per character. This re-

quires right-hand justification of data written to the

transmit buffer, if the selected word length is less

thaneight bits percharacter. When theprogrammed

A transmitted message can be terminated by CRC

and sync characters, by sync characters only, or by

pad characters (replacing the sync character(s) in

the Sync Word Registers with pad characters). How

a message is terminated is controlled by the Tx Un-

derrun/EOM latch in Status Register 0.

Figure 11a : External Sync Timing.

V000384

Figure 11b : Simple External Sync Delay.

V000385

18/46

MK68564

Data Transfer. A Transmit Interrupt is generated

each time the transmit buffer becomes empty. The

interrupt may be satisfied either by writing another

character into the transmit buffer or by resetting the

Transmit Interrupt Pending latch with a Reset Tx In-

terrupt Pending command. Ifthe interrupt issatisfied

with this command, and nothing more is written into

the transmit buffer, there canbe no further Transmit

Interrupts due to a Buffer Empty condition, because

it is the process of the buffer becoming empty that

causes the interrupts. This situation does cause a

Transmit Underrun condition when the data in the

shift register is shifted out.

the transmitter has no data to send. A Transmit Un-

derrun condition will cause an External/Status Inter-

rupt to be generated whenever the Transmit Under-

run/EOM Latch is set.

For sync character insertion only, at the termination

of amessage, a TransmitInterrupt isgenerated only

after the first automatically inserted sync character

is loaded into the transmit shift register. The status

bits in Status Register 0 indicate that the Transmit

Underrun/EOM Latch and the Tx Buffer Empty bit

are set.

For CRC insertion, followed by sync characters, at

the termination of a message, the Transmit Under-

run/EOM Latch is set, and the Tx Buffer Empty bit

is reset while the CRC characters are being sent.

When the CRC characters are completely transmit-

ted, the Tx Buffer Empty status bit is set, and a

Transmit Interrupt is generated, indicating to the

CPU that another message can begin. This Trans-

mit Interrupt occurs when the first sync character

following the CRC characters is loaded into the

transmit shift register. If no more messages are to

be transmitted, theprogram canterminate transmis-

sion by disabling the transmitter.

Another way of detecting when the transmitter re-

quiresserviceistopoll theTxBufferEmpty bit inSta-

tus Register 0. This bit is set to a one every time the

data in the transmit buffer is downloaded into the

transmit shift register. When data is written to the

transmit buffer, this bit is reset to zero.

The SIO has all the signals and controls necessary

to implement a DMA transfer routine for the trans-

mitter. The routine may be configured to enable the

DMA controller, after the first character is written to

the transmit buffer, and then using the TxRDY out-

put pin to signal the DMA that the transmitter re-

quires service. If a data character is not loaded into

the transmit buffer by the time the transmit shift re-

gister is empty, the SIO enters the Transmit Under-

run condition.

CRC Generation. Setting the Tx CRC Enable bit in

the Transmit Control Register initiates CRC accu-

mulation when the program sends the first data

character to the SIO. To ensure CRC is calculated

correctly oneach message, theReset Tx CRCGen-

erator command should be issued before the first

data character of the message is sent to the SIO.

Transmit Underrun/End of Message. When the

transmitter has no further data to transmit, the SIO

inserts filler characters to maintain synchronization.

The SIO has twoprogrammable optionsforhandling

this situation : sync characters can be inserted, or

the CRC characters generated so far can be sent,

followed by sync characters. These options are con-

trolled by the state of the Transmit Underrun/EOM

Latch in Status Register 0.

The Tx CRC Enable bit can be changed on the fly

at any point in the message to include or exclude a

particular data character from CRC accumulation.

The Tx CRC Enable bit should be in the desired

state when the data character is loaded from the

transmit data buffer into the transmit shift register.

To ensure this bit is in the proper state, the Tx CRC

Enable bit should beloaded before sending thedata

character to the SIO.

Following a hardware or software reset, the Trans-

mit Underrun/EOM Latch is set to aone. This allows

sync characters to beinserted when there is nodata

to send. CRC is not calculated on the automatically

inserted sync characters. To allow CRC

characters to be sent when the transmitter has no

data,the Transmit Underrun/EOM Latchmust bere-

set to zero. This latch is reset by issuing a Reset Tx

Underrun/EOM Latch command in the Command

Register. Following the CRC characters, the SIO

sends sync characters to terminate the message.

Transmit Termination. The SIO is equipped with a

special termination feature that maintains datainte-

grity and validity. Ifthe transmitter is disabled (by re-

setting the Transmit Enable bit or using the Tx Auto

Enable signal) while a data or sync character is

being transmitted, the character is transmitted as u-

sual but is followed by amarking line insteadof sync

or CRC characters. When the transmitter is disa-

bled,acharacter inthetransmit buffer remains inthe

buffer. If the transmitter is disabled while CRC char-

acters arebeing transmitted, the16-bit transmission

is completed, but the remaining bits of the CRC

characters are replaced by sync characters.

There is no restriction as to when, in the message,

the Transmit Underrun/EOM Latch canbereset, but

once the reset command is issued, the 16-bit CRC

is sent and followed by sync characters the firsttime

19/46

MK68564

Bisync Protocol Transmission. In aBisync Proto-

col operation, once synchronization is achieved be-

tween the transmitter and receiver, fill characters

are inserted to maintain that synchronization when

the transmitter has no more data to send. The diffe-

rent options available intheSIO are described in the

Transmit Underrun/End Of Messagepartof thissec-

tion. If pad characters are to be sentin placeof sync

characters following the transmission of the CRC,

the program can set the SIO transmitter to eight bits

per character and then load ”FFH” to the transmit

buffer while the CRC characters are being sent. Al-

ternatively, thesync characters in Sync Word Regis-

ters 1 and 2 can be redefined to be pad characters

during this time. The following example is included

to clarify this point :

dingaDLE character into Sync Word Register 1and

a SYNC character into Sync Word Register 2.

The SIO always transmits two sync characters (16

bits) in Bisync mode. If additional sync characters

are to be transmitted before a message, the CPU

can delayloading data tothetransmit bufferuntil the

required number of syncs have been sent. No CRC

calculations are done on any automatically inserted

sync characters. An alternate method of sending

additional sync characters is to load the sync char-

acters into the transmit buffer, in which case the

transmitter will treat the characters as data. The Tx

CRC Enable bit should not be set, until true data is

going to be loaded into the buffer, to avoid perfor-

ming CRC calculations on the additional sync char-

acters.

The SIO interrupts theCPUwithaTransmit Interrupt

when the Tx Buffer Empty bit is set.

SYNCHRONOUS RECEIVE

Initialization. Byte-oriented receive programs are

usually initialized with the following parameters :

odd-even ornoparity, x1 clockmode(necessary be-

cause of the start bit detection logic), 8- or 16-bit

sync character(s), CRC polynomial, Receiver En-

ables, interrupt modes, and receive character

length. Care must be taken if Parity is enabled. The

receiver will usually detect a Parity Error on all sync

characters, after synchronization is achieved, and

on the CRC characters.

The CPU recognizes that the last character (ETX) of

the message has already been sent to the SIO

transmit buffer by examining the internal program

status.

To force the SIO to send CRC, the CPU issues the

Reset Tx Underrun/EOM Latch command and

clears the current Transmit Interrupt with the Reset

Tx Interrupt Pending command. Resetting the inter-

rupt with this command prevents the SIO from re-

questing more data. The SIO then begins to send

CRC (because the transmitter is in an underrun

condition) and sets the Transmit Underrun/EOM

Latch, which causes an External/Status Interrupt.

Receiver Hunt Mode. Afterthe SIO is initialized for

a Synchronous receive operation, the receiver is in

the Huntphase. During theHunt phase, thereceiver

does a bit-by-bit comparison of the incoming data

stream and the sync character(s) stored inthe Sync

Word Register 2 (for Monosync mode) and Sync

Word Registers 1 and 2 (for Bisync mode). When a

matchoccurs, theHunt phaseis terminated, and the

following data bits are assembled into the program-

med character length and loaded into the receive

data FIFO.

The CPU satisfies the External/Status Interrupt by

loading pad characters into the transmit buffer and

clears the interrupt by issuing the Reset Exter-

nal/Status Interrupt command.

The pad character will follow the CRC characters in

this sequence, instead of the usual sync characters.

A Transmit Interrupt is generated when the pad

character is loaded into the transmit shift register.

Receive Characteristics. The receivermay bepro-

grammed to assemble five to eight data bits into a

character. The character is right-justified in the shift

register and transferred tothe receive data FIFO. All

data transfers to the FIFO are in 8-bit groups. When

the programmed character length is less than eight

bits, the most significant bit(s) transferred with a

characterwill betheleast significant bit(s)of the next

character. The programmed character length may

be changed on the fly during a message ; however,

care must be taken to assure that the change is ef-

fective before the number of bits specified for the

character length have been assembled.

From this point on, the CPU can send more pad

characters or sync characters.

The transparent mode of operation in Bisync Proto-

col is made possible with the SIO’sability to change

the Tx CRC Enable bit at any time during program

sequencing and with the additional capability of in-

serting 16-bit sync characters. Exclusion of DLE

(Data Link Escape) characters from CRC calcula-

tion can be achieved by disabling CRC calculations

immediately preceding the DLE character transfer

to the transmit buffer. In the case of a transmit un-

derrun condition in the transparent mode, a pair of

DLE-SYN characters is sent. The SIO can be pro-

grammed to send the DLE-SYNC sequence by loa-

When the Sync Character Load Inhibit bit in the Re-

ceiver Control Register is set, all characters in the

20/46

MK68564

receive data stream that match the byte loaded into

Sync Word Register 1 will be inhibited from loading

into the receive data FIFO. The comparison be-

tween Sync Word Register 1 and the incoming data

occursat a character boundary time. This is an 8-bit

comparison, regardless of thebitsper character pro-

grammed. CRCcalculations will be performed on all

bytes, even if the characters are not transferred to

the receive data FIFO, as long as the Rx CRC En-

able bit is set.

rity error status bits in Status Register 1 are latched

when they occur ; they will remain latched until an

Error Reset command is issued. As long as either

one of these bits is set, a Special Receive Condition

Interrupt will be generated at every character avai-

lable time. Since these two status bits are latched,

the error status in Status Register 1, when read, will

reflect an error inthecurrent wordinthereceivebuff-

er, in addition to any Parity or Overrun errors recei-

ved since the last Error Reset command.

Data Transfer and Status Monitiring. After char-

acter synchronization is achieved, the assembled

characters are transferred to the receive data FIFO,

and the status information for each character is

transferred to the receive error FIFO. The following

fourmodes are available to transferthe received da-

ta and its associated status to the CPU.

CRC Error Checking and Receiver Message Ter-

mination. A CRC error check on the received

message can be performed on a per character

basis under program control. The Rx CRC En-

able bit must set/reset by the program before

the next character is transferred from the receive

shift register to the receive data FIFO. This ensures

proper inclusion or exclusion of data characters in

the CRC check.

No ReceiveInterrupts Enabled. Thismode isused

eitherfor polling operations or foroff-line conditions.

When transferring data, using a polling routine, the

Rx Character Available bit in Status Register 0

should be checked to determine if a receive charac-

ter is available for transfer. Only when a character

is available should the receive buffer and Status Re-

gister 1 be read. The Rx Character Available bit is

set when a character is loaded to the top of the re-

ceive data FIFO. This bit is reset during aread of the

receive buffer.

There is an 8-bit delaybetween the timeacharacter

is transferred to the receive data FIFO and the time

the samecharacter startsto enter theCRCchecker.

Anadditional 8-bit times areneeded toperform CRC

calculations on the character. Due to this serial na-

ture of CRC calculations, the Receive Clock (RxC)

must cycle16 times after thesecond CRC character

has been loaded into the receive data FIFO or

20 times (the previous 16 plus 3-bit buffer delay

and 1-bit input delay) after the last bit is at the

RxD input, before CRC calculation is complete.

The CRC Framing Error bit in Status Register 1

will contain the comparison results of the CRC

checker. The comparison results should be zero,

indicating error-free transmission. The results in the

status bit are valid only at the end of CRC cal-

culation. If the result is examined before this time, it

usually indicates an error (the bit is High). The

comparison is made at each character available

time and is valid until the character is read from the

receive data FIFO.

Interrupt On First Character Only. This interrupt

mode is normally used to start a DMA transfer rou-

tine or, in some cases, a polling loop. The SIO will

generate an interrupt thefirsttimeacharacter is shif-

ted to the top of the receive data FIFO after this

mode is selected or reinitialized. An interrupt will be

generated thereafter only if a Special Receive

Condition is detected. This mode is reinitialized with

the Enable Interrupt On Next Receive Character

command. Parity Errors do not cause interrupts in

this mode ; however, a Receive Overrun Error will.

Interrupt On Every Character. Thisinterrupt mode

willgenerate aReceiver Interrupt every time a char-

acter is shifted to the top of the receive data FIFO.

A Special Receive Condition interrupt on aparity er-

ror is optional in this mode.

SDLC/HDLC OPERATION

INTRODUCTION

The MK68564 SIO iscapable of handling both High-

level Synchronous Data Link Control (HDLC) and

IBM Synchronous Data Link Control (SDLC) proto-

cols. In the following discussion, only SDLC is ref-

erenced because of the high degree of similarity

between SDLC and HDLC.

Special Receive Condition Interrupt. The special

condition interrupt modeis not an interrupt mode as

such, but works in conjunction with Interrupt On E-

very Character or Interrupt On First Character Only

modes. When the Status Affects Vector bit in either

channel is set, a Special Receive condition will mo-

dify the Receive Interrupt vector to signal the CPU

of the special condition. Receive Overrun Error and

ParityError are the onlySpecial Receive Conditions

in Synchronous receive mode. The overrun and pa-

The SDLC mode is considerably different from

Monosync and Bisync protocols, because it is bit o-

riented rather than character oriented. Bit orienta-

tionmakes SDLCa flexible protocolintermsof mes-

21/46

MK68564

Figure 12 : Transmit/Receive SDLC/HDLC Message Format.

V000386

sage length and bit patterns. The SIO has several

built-in features to handle variable message length.

Detailed information concerning SDLC protocol can

be found inliterature on thissubject, suchasIBMdo-

cument GA27-3093.

flag character and must be programmed to

”01111110”.

The SIO provides four I/O lines in SDLC mode that

may be used for modem control, for external inter-

rupts, or as general purpose I/O. The Request To

Send (RTS) and Data Terminal Ready (DTR) pins

are outputs that follow the inverted state of their res-

pective bits in the Transmit Control Register. The

Data Carrier Detect (DCD) and Clear To Send

(CTS) pins are inputs that can be used as auto en-

ablesto the receiver and transmitter, respectively. If

External/Status Interrupts are enabled, the DCD

and CTS pins will be monitored for a change of sta-

tus. If these inputs change for a period of time grea-

ter than the minimum specified pulse width, an in-

terrupt will be generated.

The SDLCmessage, called the frame (figure 12), is

opened and closed by flags, which are similar to the

sync characters used in other Synchronous proto-

cols. The SIO handles the transmission and reco-

gnition ofthe flagcharacters that markthebeginning

and end of the frame. Note that the SIO can receive

shared-zero flags but cannot transmit them. The 8-

bit address field of a SDLC frame contains the se-

condary station address. The SIO receiver has an

Address Search mode, which recognizes the se-

condary station so that it can accept or reject a

frame.

In the following discussion, all interrupt modes are

assumed enabled.

The control field of the SDLC frame is transparent

to the SIO ; it is simply transferred to the CPU. The

SIO handles the Frame Check sequence in a man-

ner that simplifies the program by incorporating fea-

tures such as initializing the CRC generator to all

ones, resetting the CRC checker when the opening

flagisdetected inthereceive mode, and sending the

Frame Check/Flag sequence in the transmit mode.

Controller hardware is simplified by automatic zero

insertion and deletion logic, contained in the SIO.

SDLC TRANSMIT

Initialization. The SIO is initialized for SDLC mode

by selecting these parameters in the Mode Control

Register : x1 Clock Mode, SDLC Mode, and Sync

Modes Enabled. Parity isnormally not used inSDLC

mode, because the transmitter will not add parity to

the flag character or the CRC characters, thus cau-

sing Parity Errors in the receiver. If CRC is to be cal-

culated on the transmitted data, the SDLC-CRC

polynomial must be selected in the Interrupt Control

Register (CRC-16 polynomial in SDLC Mode will

produce unknown results).

To set up the SIO for SDLC operation, the following

registers need to be initialized : Mode Control Re-

gister, Interrupt Control Register, Receiver Control

Register, Transmitter Control Register, Sync Word

Register 1, and Sync Word Register 2. The Mode

Control Register must be programmed before the o-

ther registers to assure proper operation of the SIO.

The following registers are used to transfer data or

communicate status between the SIO and the CPU

or other bus master when operating in SDLC mode

: Command Register, Status Register 0, Status Re-

gister 1, Data Register, and the Vector Register.

After reset (hardware or software), or when the

transmitter is not enabled, the Transmit Data (TxD)

output pin is held High (marking). Under program

control, the Send Break bit in the Transmit Control

Register can be set to a one, forcing the TxD output

to a Lowlevel (spacing), even if thetransmitter isnot

enabled. The spacing condition will persist until the

SendBreak bit isreset to azero. Ifthetransmit buffer

is empty when the Transmit Enable bit is set to a

one, the transmitter will start sending flag charac-

ters.Continuous flagswill be transmitted ontheTxD

Sync Word Register 1 contains the secondary sta-

tion address, and Sync Word Register 2 stores the

22/46

MK68564

output pinas long asno data isloaded into the trans-

mit buffer.

the number of bits per character does not affect the

character in the process of being shifted out. Flag

characters are always eigth bits in length, and CRC

is always 16 bits in length, regardless of the pro-

grammed bits per character. A transmitted frame

can be terminated by CRC and a flag, by a flag only,

or by an abort. This is controlled by the Tx Under-

run/EOM Latch and the Send Abort command.

Note : If a character is loaded into the transmit buf-

fer before enabling the transmitter, that character

will be sent in place of a flag.

An abort sequence may be transmitted at any time

by issuing the Send Abort command (command 1).

This causes at least eight, but less than fourteen,

ones to be sent before the output reverts back to

continuous flags. It is possible that the Abort se-

quence (eight 1’s) could follow up to fivecontinuous

ones (allowed by the zero insertion logic) and, thus,

cause as many as thirteen ones to besent. Any data

beingtransmitted andany data inthe transmit buffer

is lost when an abort is issued.

Data Transfers. A Transmit Interrupt is generated

each time the transmit buffer becomes empty. The

interrupt may be satisfied either by writing another

character into the transmit buffer or by resetting the

Transmit Interrupt Pending latch with aReset Tx In-

terrupt Pending command.Ifthe interrupt is satisfied

with this command, and nothing more is written into

the transmit buffer, there are no further transmitter

interrupts, and a Transmit Underrun condition will

occur when the data in the shift register is shifted

out. When another character is written to thebuffer

and loaded into the shift register, thetransmit buffer

can again become empty and interrupt the CPU.

Following the flags in an SDLC operation, the 8-bit

address field, control field,and information fieldmay

be sent to the SIO, using the Transmit Interrupt

mode.The SIOtransmits the frame checksequence

using the Transmit Underrun feature.

The zero insertion logic in the transmitter will auto-

matically insert a 0 after five continuous ones in the

data stream. This does not apply to flags or aborts.

Start of Transmission. Transmission will begin

withtheloading ofthefirstcharacter intothetransmit

buffer if the transmitter is already enabled. For CRC

to be calculated correctly on each frame, the CRC

generator must be initialized to all ones before the

firstcharacter is loaded. Thisis accomplished by is-

suing a Reset Tx CRC Generator command in the

Command Register. The first non-flag character

transmitted is the address field. The SIO does not

automatically transmit a station address, this is left

to the programmer. The SIO will only transmit flags

and CRC characters automatically.

When the transmitter is first enabled, the transmit

buffer is already empty and obviously cannot then

become empty. Therefore, no transmit interrupt can

occur until after the first data character is written to

the transmit buffer.

SDLC TransmitCharacteristics. Any length SDLC

frame can be transmitted. All characters are trans-

mitted with the least-significant bits first. All data is

shifted out of the Transmit Data pin (TxD) on thefal-

ling edge of the Transmit Clock (TxC). The transmit-

tertransmit from oneto eight data bitsper character.

This requires right-hand justification of data written

to the transmit buffer, if the word length selected is

less than eight bits per character. When the pro-

grammed character length is six or seven bits, the

unused bits in the transmit buffer are ignored. If a

word length of five bits per character or less is se-

lected, the data loaded into the transmit buffer must

be formatted as described in the Transmit Control

Register part of the Register Description section.

Another way of detecting when the transmitter re-

quires serviceistopoll theTx Buffer Empty bitinSta-

tus Register 0. This bit is set to a one every timethe

data in the transmit buffer is downloaded into the

transmit shift register. When data is written to the

transmit buffer, this bit is reset to zero.

The SIO has all the signals and controls necessary

to implement a DMA transfer routine for the trans-

mitter. The routine may be configured to enable the

DMAcontroller, after thefirstcharacter is written into

the transmit buffer, using the TxRDY output pin to

signalthe DMAthat the transmitter requires service.

TheDMAtransfercan beterminated, when the DMA

blockcount is reached, using the Tx Underrun/EOM

interrupt.

The number of bits per character to be transmitted

can be changed on the fly. Any data, written to the

transmit buffer after the bits per character field is

changed, are affected by the change. The same is

true of any characters in the buffer at the time the

bits per character field is changed. The change in

Transmit Underrun/End of Message. SDLC-like

protocols do not have provisions for fill characters

withina message.The SIO, therefore, automatically

terminates an SDLC frame when the transmit data

buffer is empty, and the output shift register has no

23/46

MK68564

more bits tosend. Itdoes thisby firstsending thetwo

bytes of CRC and the following these with one or

more flags. This technique allows very high-speed

transmissionunder DMAorCPU control, without re-

quiring the CPU to respond quickly to the end of

message situation.

flag insertion matches the CRC checker, giving a

false CRC check result.

CRC Generation. The CRC generator must be re-

set to all ones at the beginning of each frame before

CRC accumulation can begin. Actual accumulation

begins onthefirst data character (address field)loa-

ded into the transmit buffer. The Tx CRC Enable bit

in the Transmit Control Register should be set to a

one beforethefirst character isloaded intothetrans-

mit buffer. In SDLC mode, all characters between

the opening and the closing flags are included in

CRC accumulation. The output ofte CRCgenerator

is inverted before it is transmitted.

The action that the SIO takes in the underrun situa-

tion depends on the state of the Transmit Under-

run/EOM status bit in status Register 0. Following a

reset,the Transmit Underrun/EOM bit is set to aone

and preventsthe insertion ofCRC characters during

the timethere is no datato send. Consequently, flag

characters are sent. If the Transmit Underrun/EOM

status bit is zero when the underrun condition oc-

curs, the 16-bit CRC character is sent, followed by

one or more flag characters. The Transmit Under-

run/EOM bit is reset to zero by issuing the Reset Tx

Underrun/EOM Latch command in the Command

Register.

Transmit Termination. The normal sequence at

the end of a frame is

A Transmit Interrupt occurs when thelast data char-

acter written to the transmit buffer is downloaded in-

to the transmit shift register. This interrupt may be

cleared by issuing a Reset Tx Interrupt Pending

command.

The SIObegins tosend aframe when data iswritten

into the transmit buffer. Between the time the first

data byte is written and the end of the message, the

Reset Tx Underrun/EOM Latch command must be

issued. The Transmit Underrun/EOM status bit will

then be in the reset state at the end of the message

(when underrun occurs), and CRC characters will

automatically be sent. The transmission of the first

CRC bit set the Transmit Underrun/EOM status bit

to a one and generates an External/Status interrupt.

Also, while CRC is being sent, the Tx Buffer Empty

bit in Status Register 0 is reset to indicate that the

transmit shift register is full of CRCdata. When CRC

has been completely sent, the Tx Buffer Empty sta-

tus bit is set, and a Transmit Interrupt is generated

to indicate that another message maybegin. This in-

terrupt occurs because CRC has been sent, and a

flag has been loaded into the shift register. If no

more messages are to besent, the program canter-

minate transmission by disabling the transmitter.

An External/Status Interrupt occurswhenthe first bit

of the CRC character is transmitted. This interrupt

condition should first be tested to seeif the interrupt

was caused by the TxUnderrun/EOM bit going High

and thenreset by issuing aResetExternal/Status In-

terrupts command.

A Transmit Interrupt occurs when the first bit of the

flag is transmitted. This interrupt may be cleared by

issuing a Reset Tx Interrupt Pending command, by

loading the first character of the next message, or

by disabling the transmitter.

If the transmitter is disabled while a character is

being sent, that character (data or flag) is sentin the

normal fashion but is followed by a marking line ra-

ther than CRC ormore flagcharacters. If CRCchar-

acters are being sent at the time the transmitter is

disabled, all 16 bits will be transmitted, followed by

a marking line ; however, flags are sent in place of

CRC. A character in the buffer when the transmitter

is disabled remains in the buffer.

Although there isno restriction astowhen the Trans-

mit Underrun/EOM bit can be reset within a mes-

sage, it is usually reset after the first data character

(secondary address field) is sent to the SIO. By re-

setting the status bit early in the message, the CPU

has additional time (16 bits of CRC) to recognize if

an unintentional transmit underrun situation has oc-

cured and to respond with an Abort command. Is-

suingtheAbort command stops the flagsfromgoing

on theline prematurely and eliminates thepossibility

of the receiver accepting the frame as valid data.

Thissituation canhappen if, at thereceiving end, the

data pattern immediately preceding the automatic

SDLC RECEIVE

Initialization. The receiver is enabled only after all

of the receive parameters are initialized. After the

Receiver Enable bit inthe ReceiverControlRegister

is set to a one, the receiver will be in the Hunt phase

and will remain in this phase until the first flag is re-

ceived. While inthe SDLC mode,the receiver never

re-enters the Hunt phase, unless specifically in-

structed to do so by the program or when an Abort

character is detected in the incoming data stream.

24/46

MK68564

Receiver Characteristics. The receiver may be

programmed to assemble five to eight data bits into

a character. The character is right-justified in the

shift register and transferred to the receive data FI-

FO. All data transfers to the FIFOarein8-bit groups.

Whenthecharacter lengthprogrammed islessthan

eight bits, the most significant bit(s) transferred with

a character, will be the least-significant bit(s) of the

next character. The character length programmed

may be changed on the fly during the reception of a

frame ; however, care must be taken to assure that

the change is effective, before the number of bits

specified for the character length has been assem-

bled.

Rx Character Available bit in Status Register 0

shouldbechecked to determine whether or not are-

ceive character is available for transfer. Only when

a character is available should the receive buffer

and Status Register 1 be read. The Rx Character

Available bit is set to a one every time a character

is shifted to the top of the receive data FIFO. This

bit is reset when the receive buffer is read.

Interrupt On First Character Only. This interrupt

mode is normally used to start a DMA transfer rou-

tine, or in some cases, a polling loop. The SIO will

generate an interrupt thefirst timeacharacter isshif-

ted to the top of the receive data FIFO after this

mode is selected or reinitialized. An interrupt will be

generated thereafter only if a Special Receive

Condition is detected. Thismode is reinitialized with

the Enable Interrupt On Next Received Character

command. Parity Errors do not cause interrupts in

this mode, but a Receive Overrun Error or an End

Of Frame condition will.

The address field in the SDLC frame is defined as

an 8-bit field. When the Address Search Mode is se-

lected, the receiver will compare the 8-bit character

following the flag (first non-flag character) against

the address programmed in Sync Word Register 1

or the hardwired global address (11111111). When

the address field of the SDLC frame matches either

address, data transfer will begin with the address

character being loaded into the receive data FIFO.

If the frame address does not match either address,

the receiver will remain idle and continue checking

everyframe received for an address match. The ad-

dress comparison is always done on the first eight

bits following a flag, regardless of the bits per char-

acter programmed.

InterruptOn Every Character. This interrupt mode

will generate a Receiver Interrupt every time a char-

acter is shifted to the top of the receive data FIFO.

A Special Receive Condition interrupt on aParity er-

ror is optional in this mode.

Special Receive Condition Interrupt. The special

condition interrupt mode isnotan interrupt mode, as

such, but works in conjunction with Interrupt On E-

very Character or Interrupt On First Character Only

modes. When the Status Affects Vector bit in either

channel is set, aSpecial Receive Condition will mo-

dify the Receive Interrupt vector to signal the CPU

of the special condition. Receive Overrun Error, Pa-

rityError,andEnd OfFrame aretheSpecial Receive

Conditions in SDLC mode. The Overrun and Parity

error status bits in Status Register 1 are latched

when they occur ; the End Of Frame bit is not lat-

ched. The two bits that are latched will remain lat-

ched and will generate a Special Receive Condition

Interrupt at every character available time until an

Error Reset command is issued. Since the two sta-

tus bits are latched, the error status in Status Regis-

ter 1, when read, will reflect an error in the current

word in the receive buffer, in addition to any Parity

or Overrun errors received since thelastErrorReset

command.

The SIO receiver is capable of matching only one

address character. Once a match occurs, all data is

transferred to thereceive data FIFOat the program-

med bits per character rate. If SDLC extended ad-

dressfield recognition is used (two or more address

characters), the CPU program must be capable of

determining whether or not the frame has a correct

address field. If the correct address fieldis not recei-

ved, the Hunt bit can be set to suspend reception

and start searching for the next frame. The control

field of an SDLC frame is transparent to the SIO ; it

is transferred to the data FIFO as a data character.

All extra zeros, inserted in the data stream by the

transmitter, are automatically deleted in the recei-

ver.

Data Transfer and Status Monitoring. After re-

ceipt of a valid flag, the assembled characters are

transferred to the receive data FIFO, and the status

information for each character is transferred to the

receive error FIFO. The following four modes are

available to transfer the received data and its asso-

ciated status to the CPU.

SDLC Receive CRC Checking. Control of the re-

ceiver CRC checker is automatic. It is reset by the

leading flag, and CRC is calculated up to the final

flag. The byte that has the End Of Frame bit set is

the byte that contains the result of the CRC check.

If the CRC/Framing Error bit is not set (zero), the

CRC indicates a valid received message. A special

check sequence is used for the SDLC check, be-

No Receiver Interrupts Enabled. This mode is u-

sed for polling operations or for off-line conditions.

When transferring data, using a polling routine, the

25/46

MK68564

cause the transmitted CRC character is inverted.

The final check must be 0001110100001111. he 2-

byte CRC check characters should be read and dis-

carded by the CPU, because the last two bits of the

2-byte SDLC CRC check characters are not trans-

ferred to the receive data FIFO due to the internal

timing associated with detecting the closing flag.

used in the programming of the SIO. This register is

reset to ”00H” by a channel or hardware reset. All

bits, except Loop Mode,will be read as zeros during

a read cycle.

D7

D6

D5

D4

D3

D2

D1

D0

CRC CRC CMD CMD CMD

LOOP

MODE

1

0

2

1

0

Unlike Synchronous modes, the logic path in SDLC

modedoes nothave an8-bitdelay betweenthetime

a character is transferred to the receive data FIFO

and the time a character enters the CRC checker.

Thisdelay isnot needed, because in SDLC,all char-

actersbetweentheopening and closing flags are in-

cluded in the CRC calculations. When the second

CRC character (six bits only) is loaded into the re-

ceive buffer, CRC calculation is complete.

D7, D6 : Reset Codes 1 and 0

CRC 1

CRC 0

0

1

0

1

0

1

Null Code (no effect)

Reset Receiver CRC Checker

Reset Transmit CRC Generator

Reset Tx Underrun/End of

Message Latch

SDLC Receive Termination. AnSDLC frameis ter-

minated when the closing flag is detected. The de-

tectionofthe flagsetsthe EndOf Frame bitin Status

Register 1 and generates a Special Receive Condi-

tion Interrupt. In addition to the End Of Frame bit

being set and the results of the CRC check, Status

Register 1 has three bits of Residue code valid at

this time. The Residue bits indicate the boundary

betweentheCRCcheck bits and theI-field bits inthe

frame. A detailed description of the Residue code

bits is given in the Register Description section, un-

der Status Register 1.

Null Code. The null code has no effect on the

MK68564 SIO. It is used when writing to the

Command Register for some reason other than a

CRC Reset.

Reset Receiver CRC Checker. It is necessary in

Synchronous modes (except SDLC) to reset the re-

ceiver CRC circuitry between received messages.

The CRC circuitry may be reset by one of the follo-

wing : disabling the receiver, setting the Enter Hunt

Mode bit in theReceiver Control Register, orissuing

this Reset command. The CRC circuitry is reset

automatically in SDLC mode when the End Of

Frame flagis detected. This Reset command will ini-

tialize the CRC checker circuit to all ones in SDLC

mode and all zeros in the other Synchronous

modes.

Any frame can be prematurely aborted by an Abort

sequence. Aborts are detected if seven or more

continuous ones occur in the received data stream.

This condition will cause an External/Status Inter-

rupt to be generated with the Break/Abort bit in Sta-

tus Register 0 set. After the Reset External/Status

Interrupts command has been issued, a second in-

terrupt will occur when the continuous ones condi-

tion has been cleared. This second interrupt can be

used to distinguish between the Abort and Idle line

conditions.

Reset Transmit CRC Generator. This command

resetsthe CRCgenerator to all ones in SDLC mode

and all zeros in the other Synchronous modes. This

command should be issued after the transmitter is

enabled but before the first character of a message

is loaded in the transmit buffer.

Reset Transmit Underrun/EOM Latch. This

command resets the Underrun/EOM latch in Status

Register 0 if the transmitter is enabled. The Under-

run/EOM latch controls the transmission of CRC at

the endof amessagein Synchronous modes. When

a transmit underrun occurs and this latch is low,

CRC will be appended to the end of the transmis-

sion.

REGISTER DESCRIPTION

The following sections describe the MK68564 SIO

registers. Each register is detailed in terms of bit

configuration, the active states of each bit, their de-

finitions, their functions, and their effects upon the

internal hardware and external pins.

COMMAND REGISTER (CMDREG)

Thisregister contains command and reset functions

26/46

MK68564

D5, D4, D3 : Command Codes

Command CMD2 CMD1 CMD0

Command 5 (Reset Tx Interrupt Pending). When

the Transmit Interrupt Enable mode is selected, the

transmitter requests an interrupt when the transmit

buffer becomes empty. In those cases, where there

are no more characters to be sent (at the end of

message, for example), issuing this command re-

sets thepending transmitinterrupt and prevents any

further transmitter interrupt requests until the next

character has been loaded into the transmit buffer

or until CRC has been completely sent.

0

1

2

0

1

0

1

0

Null Command

(no effect)

Send Abort

(SDLC mode)

Reset External/

Status Interrupts

Channel Reset

Enable Interrupt On

Next Rx Character

Reset Tx Interrupt

Pending

3

4

0

1

0

1

0

5

1

0

1

Command 6 (Error Reset). This command resets

the upper seven bits in Status Register 1. Anytime

a Special Receive Condition exists when Receive

Interrupt On First Character Only mode is selected,

the data with the special condition is held in the re-

ceive data FIFO until this command is issued.

6

7

1

0

1

Error Reset

Null Command

(no effect)

Command 0 (Null). The Null command has no ef-

fect on the MK68564 SIO.

Command 7 (Null). The Null command has no ef-

fect on the MK68564 SIO.

Command 1 (Send Abort). This command is used

in SDLC mode to transmit a sequence of eight to

thirteen ones. This command always empties the

transmit buffer ans sets theTxUnderrun/EOM Latch

in Status Register 0 to a one

D2, D1 : Not Used (read as zeros)

D0 : Loop Mode

When this bit is set to a 1, the transmitter output is

connected to the receiver input and TxC is connec-

ted to the receiver clock. RxC and RxD pins are not

used by the receiver ; they are bypassed internally.

RxC may still be used as the baud rate generator

output in Loop Mode.

Command 2 (Reset External/Status Interrupts). Af-

ter an External/Status interrupt (a change on a mo-

dem line or a Break condition, for example), the up-

per five bits in Status Register 0 are latched. This

command reenables thesebitsand allowsinterrupts

to occur again as a result of a status change. Lat-

ching the status bits captures short pulses, until the

CPU has time to read the change. This command

should be issued prior to enabling External/Status

Interrupts.

MODE CONTROL REGISTER (MODECTL)

The Mode Control Register contains controlbits that

affect both the receiver and the transmitter. This re-

gistermustbeinitialized before loading theInterrupt,

Tx, and Rx Control Registers, and the Sync Word

Registers. This register is reset to ”00H” by a chan-

nel or hardware reset.

Command 3 (Channel Reset). This command di-

sables both the receiver and transmitter, forces TxD

to a marking state (”1”), forces the modem control

signals high, resets any pending interrupts from this

channel, and resets allcontrolregisters. See theRe-

set section in the SIO System Interface Description

for a more detailed list. All control registers for the

channel must be rewritten after a Channel Reset

command.

D7

D6

D5 D4 D3

D2

D1

D0

CLOCK CLOCK SYNC SYNC STOP STOP PARITY PARITY

RATE RATE MODE MODE BITS BITS 0 E/O ON/OFF

1

0

1

0

1

D7, D6 : Clock Rate 1 and 0

Command 4 (Enable Interrupt On Next Rx Charac-

ter).Thiscommandisusedto reactivatetheReceive

Interrupt On First Character Only interrupt mode.

This command is normally issued after the present

message is completed but before the next message

has started to be assembled. The next character to

enter the receive data FIFO after this command is

issued will cause a receiver interrupt request.

These bits specify the multiplier between the input

shift clock rates (TxC x RxC) and data rate. The

same multiplier is used for both the transmitter and

receiver, although the input clock rates may be dif-

ferent. In x16, x32, and x64 clock modes, the recei-

ver start bit detection logic is enabled ; therefore, for

Synchronous modes, the x1 clock rate must be

specified. Any clock rate may be specified for Asyn-

chronous mode ; however, if the x1 clock rate is se-

lected, synchronization between the receive data

and the receive clock must be accomplished exter-

nally.

Note: Ifthe data FIFOhas more than one character

stored when this command is issued, the first pre-

viously stored character will cause the receiver in-

terrupt request.

27/46

MK68564

in the receive data. The received parity bit is trans-

ferred to the CPU as part of the data character, un-

lesseight bits per character is selected inthe Recei-

ver Control Register.

CLOCK CLOCK

RATE 1 RATE 0

Multiple

0

1

x1

x16

Clock Rate = Data Rate

Clock Rate = 16 x Data

Rate

INTERRUPT CONTROL REGISTER

(INTCTL)

This register contains the control bits forthe various

interrupt modes and the DMA handshaking signals.

This register is reset to ”00H” by a channel or hard-

ware reset.

1

0

1

x32

x64

Clock Rate = 32 x Data

Rate

Clock Rate = 64 x Data

Rate

D5, D4 : Sync Modes 1 and 0

These bits select the various options for character

synchronization. These bits are ignored, unless

Sync modes is selected in the Stop Bits filed of this

register.

D 7

D 6

D 5

D 4

D 3

D2

D 1

D0

CRC16/ CTX RX RDY RX INT RX INT STATUS TX INT EXT INT

SDLC RDY ENABLE MODE MODE AFFECTS ENABLE ENABLE

ENABLE

1

0

D7 : CRC-16/SDLC-CRC

SYNC

MODE 1 MODE 0

Thisbitselects theCRC polynomial used byboththe

transmitter and receiver. When set to a one, the

CRC-16 polynomial (x16 + x15 + x2 + 1) is used ;

when reset to a zero, the SDLC-CRC polynomial

(x16 + x12 + x5 + 1) is used. If the SDLC mode is

selected, theCRC generator andchecker arepreset

to all ones and a special check sequence is used.

0

1

0

1

0

8-bit Programmed Sync

16-bit Programmed Sync

SDLC Mode (01111110 flag

pattern)

1

External Sync Mode

D3, D2 : Stop Bits 1 and 0

The SDLC-CRC polynomial must be selected in

SDLC mode. Failure to do so will result in receiver

CRC errors. When a Synchronous mode, other than

SDLC, is selected, the CRC generator and checker

are preset to all zeros (for bothpolynomials). This bit

must be programmed before CRC is enabled in the

receiver and transmitter control registers, to assure

valid CRC generation and checking. This bit is igno-

red in Asynchronous modes.

These bits determine the number of stop bits added

to each Asynchronous character that is transmitted.

The receiver always checks forone stop bit in Asyn-

chronous mode. A special code (00) signifies that a

Synchronous mode isto be selected. 1 1/2 stop bits

is not allowed if x1 clock rate is selected, because it

will lock up the transmitter.

STOP

BIT 1

STOP

BIT 0

D6 : Tx Ready Enable

0

1

0

1

0

1

Sync Modes

When this bit is set to a one, the TxRDY output pin

will pulse Low for three clock cycles (CLK) when the

transmit buffer becomes empty. When this bitis ze-

ro, the TxRDY pin is heldHigh.

1 Stop Bit per Character

11/2 Stop Bits per Character

2 Stop Bits per Character

D1 : Parity Even/Odd

D5 : Rx Ready Enable

If theParity Enable bitisset, this bit determines whe-

ther parity is checked as even or as odd. (1 = even,

0 = odd). This bit is ignored if the Parity Enable bit

is reset.

When this bit is set to a one, the TxRDY output pin

will pulse Low for three clockcycles (CLK) when a

character is available in the receive buffer. If a Spe-

cial Receive Condition is detected when the Re-

ceive Interrupt On FIrst Character Only interrupt

mode is selected, the RxRDY pin will not become

active ; instead, a special Receive Condition inter-

rupt will be generated. When this bit is zero, the

RxRDY pin will be held High

D0 : Parity Enable

If this bit is set to a one, one additional bit position

beyond those specified in the bits/character control

fieldisadded tothetransmitted data andisexpected

28/46

MK68564

D4, D3 : Receive Interrupt Modes 1 and 0

Interrupt On All Receive Characters. This mode

ammows an interrupt for every character received

(or character in the receive data FIFO)and provides

a unique vector (if Status Affects ector is enabled)

when a Special Receive Condition exists. When the

interrupt request is due to a special condition, the

data containing that condition, the data containing

data FIFO.

Together, these two bitsspecify the various charac-

ter-avalaible conditions that will cause interrupt re-

quests. When receiver interrupts are enabled, a

Special Receive Condition can cause an interrupt

request and modify the interrupt vector. Special Re-

ceive conditions are:Rx Overrun Error, Framing Er-

ror (inasync mode), End OfFrame (in SDLC mode),

and Parity Error (when selected). The Rx Overrun

Error and the Parity Error conditions are latched in

Status Register 1when theyoccur ; they arecleared

by an Error Reset command (Command 4) or by a

hardware or channel rest.

D2 : Status Affects Vector

Whenthis bit is zero, the value programmed into the

Vector Register is returned during aread cycleor an

interrupt acknowledge cycle. If the Vector Register

has not been programmed following a hardware re-

set, then ”0FH” is returned.

Rx INT Rx INT

MODE 1 MODE 0

When this bit is a one, the vector returned during a

read cycle or an interrupt acknowledge cycle is va-

riable. The variable fieldreturned depends on the hi-

ghest-priority pending interrupt at the start of the cy-

cle.

0

1

Receive Interrupts Disabled

Receive Interrupt On First

Character Only

1

0

Interrupt On All Receive

Characters-parity

The Status Affects Vector control bits from both

channels arelogical ”or” edtogether ;therefore, if ei-

ther is programmed to a one, its operation affects

both channels. This is the only control bit that func-

tions in this manner on the MK68564.

Error is a Special Receive

Condition

Interrupt On All Receive

Characters-parity

Error is not a Special Receive

Condition

1

V2 V1

0

Interrupt Condition

Receive Interrupts Disabled. This mode prevents

the receiver from generating an interrupt request

and clearsany pending receiver interrupts. Ifa char-

acter is avalaible in the receiver data FIFO, or if a

Special Receive Condition exists before or during

the time receiver interrupts are disabled, and recei-

ver interrupts are then enabled without clearing

these conditions, an interrupt request will immedi-

ately be generated.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Ch B Transmit Buffer Empty

Ch B External/statusChange

Ch B Receive Character Available

Ch B Special Receive Condition*

Ch A Transmit Buffer Empty

Ch A External/statusChange

Ch A Receive Character Available

Ch A Special Receive Condition*

* Special Receive Conditions : Parity Error, Rx Overrun Er-

Receive Interrupt On First Character Only. The

receiver requests an interrupt in this mode on the

first available character (or stored FIFO character),

or on a Special Receive Condition. If a Special Re-

ceive Condition occurs, the data with the special

condition is held inthereceive data FIFO untilan Er-

ror Reset command (Command 6) is issued.

D1 : Transmit Interrupt Enable

When this bit is set to a one, the transmitter will re-

quest an interrupt whenever the transmit buffer be-

comes empty. When this bit is zero, no transmitter

interrupts will be requested.

The receive Interrupt OnFirst Character Only mode

can be re-enabled by the Enable Interrupt On Next

Rx Character command (Command 4). If this inter-

rupt mode was terminated by a Special Receive

Condition, the Error Reset command must be is-

sued,before Command4, for proper operation to re-

sume.

D0 : External/Status Interrupt Enable

When this bit is set to a one, an interrupt will be re-

questedbytheexternal/status logiconanyof thefol-

lowingoccurrences :a transition (high-to-low orlow-

to-high) on the DCD, CTS, or SYNC input pins, a

break/abort condition that has been detected and

29/46

MK68564

terminated, or at the beginning of CRCtransmission

when the Transmit Underrun/EOM latch in Status

Register 0becomes set.When thisbitiszero, noEx-

ternal/Status interrupts will occur.

D7, D6 : Receiver Bits/Character 1 and 0

The state of these two bits determines the number

of bits to be assembled as a character in the recei-

ved serialdata stream. IfParity is enabled, one ad-

ditionalbit willbeadded to each character. The num-

ber of bits per character can be changed while a

character is being assembled but only before the

number of bits currently programmed isreached. All

data is right-justified in the shift register and trans-

ferred to the receive data FIFO in 8-bit groups.

If this bit is set when an External/Status condition is

pending, an interrupt will be requested. It is re-

commended that a ResetExternal/Status Interrupts

command (Command 2 in the Command Register)

be issued prior to enabling External/Status inter-

rupts.

In Asynchronous mode, transfers are made at char-

acter boundaries, and all unused bits of character

are set to a one. In Synchronous modes and SDLC

mode, an 8-bit segment of the serial data stream is

transferred to the data FIFOwhenthe internal coun-

ter reaches the number of bits per character pro-

grammed. For less than eight bits per character, no

parity, the MSB bit(s) of the first transfer will be the

LSB bit(s) of the next transfer.

SYNC WORD REGISTER 1 (SYNC 1)

This register is programmed to contain the transmit

synccharacter inthe Monosync mode, thefirst eight

bits of the 16-bit sync character in the Bysinc mode,

or the transmit sync character in the External Sync

mode. This register is not used in Asynchronous

mode. In the SDLC mode, this register is program-

med to contain the secondary address field used to

compare against the address field of the SDLC

frame. The SIO does not automatically transmit the

station address at the beginning of a response

frame. This register is reset to ”00H” by a channel

or hardware reset.

RX BITS RX BITS Bits/character Bits/character

CHAR 1 CHAR 0

(no parity)

(parity)

0

1

0

1

0

1

5

6

7

8

6

7

8

9

D7

D6

D5

D4

D3

D2

D1

D0

SYNC/ SYNC/ SYNC/ SYNC/ SYNC/ SYNC/ SYNC/ SYNC/

SDLC7 SDLC6 SDLC5 SDLC4 SDLC3 SDLC2 SDLC1 SDLC0

D5 : Receiver Auto Enables

When this bit is set to a one, and the Receiver Ena-

ble bit is also set, a Low on the DCD input pin be-

comes the enable for the receiver. When this bit is

zero, the DCD pin is simply an input to the SIO, and

its status is displayed in Status Register 0.

SYNC WORD REGISTER 2 (SYNC 2)

This register is programmed to contain the receive

sync character inthe Monosync mode, the last eight

bits of the 16-bit sync character in the Bisync mode,

or a flag character (01111110) in the SDLC mode.

This register is not used in the External Sync mode

and the Asynchronous mode. This register is reset

to ”00H” by a channel or hardware reset.

D4 : Enter Hunt Mode

This bit, when written to a one, rearms the receiver

synchronization logic and forces the comparison of

the received bit stream to the ontents of Sync Word

Register 1and/or Sync Word Register 2, depending

upon which Synchronous mode is selected, until bit

synchronization is achieved. The SIO automatically

enters the Hunt mode after a channel or hardware

reset, after an Abort condition is detected, or when

the receiver is disabled. When the Hunt mode is en-

tered, the Hunt/Sync bit in Status Register 0 is set

to a one. When synchronization is achieved, the

Hunt/Sync bit is reset toa zero. IfExternal/Status in-

terrupts are enabled, an interrupt request will be ge-

nerated on both transitions of the Hunt/Sync bit. En-

ter Hunt Mode has no affect in Asynchronous

modes. Thisbitisnotlatchedand will always beread

as a zero.

D7

D6

D5

D4

D3

D2

D1

D0

SYNC/ SYNC/ SYNC/ SYNC/ SYNC/ SYNC/ SYNC/ SYNC/

SDLC SDLC SDLC SDLC SDLC SDLC SDLC SDLC 8

15

14

13

12

11

10

9

RECEIVER CONTROL REGISTER

(RCVCTL)

This register contains the control bits and parame-

ters for the receiver logic. This register is reset to

”00H” by a channel or hardware reset.

D 7

D 6

D5

D 4

D3

D2

D1

D 0

RX BITS RX BITS RX AUTO HUNT RX CRC ADDR. STRIP

RX

CHAR 1 CHAR 0 ENAB.

MODE ENAB. SEARCH SYNC ENABLE

30/46

MK68564

D3 : Receiver CRC Enable

data FIFO, and no receiver interrupt will be genera-

ted for the character.

This bit, when set to a one in a Synchronous mode

other than SDLC, is used to initiate CRC calculation

at thebeginning of the last byte transferred from the

receiver shift register to the receive data FIFO. This

operation occurs independently of the number of

bytes in the receive data FIFO. As long as this bit is

set, CRC will be calculated on all characters recei-

ved (data or sync). When a particular byte is to be

excluded from CRCcalculation, thisbitshould be re-

set to a zero before the next byte is transferred to

the receive data FIFO. If this feature is used, care-

must be taken to ensure that eight bits percharacter

are selected in the reciever because of an inherent

eight-bit delay from the receiver shift register to the

CRC checker.

D0 : Receiver Enable

When this bit is set to a one, receiver operation be-

gins if Rx Auto Enables mode is not selected. This

bit should be set only after all receiver parameters

are established, and the receiver is completely ini-

tialized. When thisbit iszero, thereceiver isdisabled

; the receiver CRC checker isreset, and thereceiver

is in the Hunt mode.

TRANSMITTER CONTROL REGISTER

(XMTCTL)

This register contains the control bits and parame-

ters for the transmitter logic. This register is reset to

”00H” by a channel or hardware reset.

When this bit is set to a one in SDLC mode, the SIO

will calculate CRC on all bits between the opening

and closing flags. Thereisnodelay fromthereceiver

shift register to the CRC checker in SDLC mode.

This bit is ignored in Asynchronous modes.

D7

D6

D5

D4

D3

D2

D1

D0

TX

BITS

TX

BITS

TX

AUTO

SEND

BREAK

TX

CRC

ENABLE

DTR

RTS

TX

ENABLE

CHAR 1 CHAR 0 ENABLES

D2 : Address Search Mode

D7, D6 Transmit Bits/Character 1 and 0

Setting this bit to a one in SDLC mode forces the

comparison of the first non-flag character of aframe

with the address programmed in Sync Word Regis-

ter 1 or the global address (11111111). If a match

does not occur, the frame is ignored, and the recei-

ver remains idle until the next frame is detected. No

receiver interrupts can occur in this mode, unless

there is an address match. This bit is ignored in all

modes except SDLC.

The state of these two bits determine the number of

bits in each byte transferred fromthe transmit buffer

to the transmit shift register. All data written to the

transmit buffer must be right-justified with the least-

significant bits first. The Five Or Less mode allows

transmission of one to five bits per character ; how-

ever, the CPU should format the data characters as

shown. If Parity is enabled, one additional bit per

character will be transmitted.

D1 : Sync Character Load Inhibit

TX BITS/ TX BITS/

CHAR 1 CHAR 0

Bits/character

(no parity)

When this bit is set to a one in any Synchronous

mode except SDLC, the SIO compares the byte in

Sync Word Register 1 with the byteabout to be loa-

ded into the receiver data FIFO. If the two bytes are

equal, the load is inhibited, and noreceiver interrupt

willbe generated by this character. CRC calculation

is performed on all bytes, whether they are loaded

into the data FIFO or not, when the receiver CRC is

enabled. Note that the register used in the compa-

rison contains the transmit sync character in Mono-

sync and External sync modes. Thisbit is ignored in

SDLC mode because all flag characters are auto-

matically striped in this mode without performing

CRC calculations on them.

0

1

0

1

0

1

Five or Less

6

7

8

D 7 D6 D5 D 4 D 3 D 2 D 1 D 0

Five or Less

1

0

D

Sends One Data Bit

Sends Two Data

Bits

Sends Three Data

Bits

Sends Four Data

Bits

Sends Five Data

Bits

1

0

1

0

D

If thisbit is set toa one inAsynchronous modes, any

character received matching the contents of Sync

Word Register 1 will not be loaded into the receive

D

31/46

MK68564

D5 : Transmit Auto Enables

transmit sync or flag characters in Synchronous

modes, thisbit hastobeset whenthe transmitbuffer

is empty. Data or sync characters in the process of

being transmitted are completely sent if this bit is re-

set to zero after transmission has started. If this bit

is reset during the transmission of a CRC character,

sync or flag characters are sent instead of the CRC

character.

When this bit is set to a one, and the Transmit Ena-

ble bitis alsoset, a Low on the CTSinput pinwill en-

able the transmitter. When this bit is zero, the CTS

pin is simply an input to the SIO,and itsstatus is dis-

played in Status Register 0.

D4 : Send Break

When set to a one, this bit immediately forces the

Transmit Data output pin (TxD) to a spacing condi-

tion (continuous 0’s), regardless of any data being

transmitted at the time. This bit functions, whether

the transmitter is enabled or not. When this bit is re-

set to zero, the transmitter will continue to send the

contents of the transmit shift register. The shift re-

gistermaycontainsynccharacters, data characters,

or all ones.

STATUS REGISTER 0 (STAT 0)

READ ONLY

This register contains the status of the receive and

transmit buffers and the status bits for the five

sources of External/Status interrupts.

D7

D6

D5

D4

D3

D2

D1

D0

BREAK/ UNDERRUN CTS HUNT/ DCD TX BUFR INTERPT

RX

ABORT

/EOM

SYNC

EMPTY PENDING CHAR

AVAIL

D3 : Transmitter CRC Enable

D7 : Break/Abort

This bit determines if CRC calculations are perfor-

med on a transmitted data character. If this bit is a

one at the time a character is loaded from the trans-

mit buffer to the transmit shift register, CRC is cal-

culated on the character. CRC is not calculated on

any automatically inserted sync characters. CRC is

notautomatically appended totheendof amessage

unless this bit is set, and the Transmit Under-

run/EOM status bitinStatus Register 0isreset when

a Transmit Underrun condition occurs. If this bit is a

zero when a character is loaded from the transmit

buffer into the transmit shift register, no CRC calcu-

lations are performed on the character. This bit is i-

gnored in Asynchronous modes.

This bit is reset by a channel or hardware reset. In

Asynchronous modes, this bit is set when a Break

sequence (null character plus framing error) is de-

tectedin thereceived datastream. An External/Sta-

tus interrupt, if enabled, is generated when Break is

detected. The interrupt service routine must issue a

Reset

External/Status

Interrupt

command

(Command 2) to the SIO, so the break detection lo-

gic can recognize the termination of the Break se-

quence.

The Break/Abort bit is reset to a zero when the ter-

mination of the Break sequence isdetected inthe in-

coming data stream. The termination of the Break

sequence also causes the generation of an Exter-

nal/Status interrupt. Command 2 must be issued to

enable the break detection logic to look for the next

Breaksequence. Asingle extraneous null character

is present in the receiver after the termination of a

break ; it should be read and discarded.

D2 : Data Terminal Ready (DTR)

This is the control bit for the DTR output pin. When

this bit is set to a one, the DTR pin goes Low: when

this bit is reset to a zero, the DTR pin goes High.

D1 : Request To Send (RTS)

In SDLC mode, this bit is set by the detection of an

Abort sequence (seven or more ones) in the recei-

ved data stream. The External/Status Interrupt is

handled the same way as in the case of a Break se-

quence. The Break/Abort bit is not used in the other

Synchronous modes.

This is the controlbit for the RTS output pin. In Syn-

chronous modes, when this bit is set to a one, the

RTS pin goes Low ; when this bit is reset to a zero,

the RTS pin goes High. In Asynchronous modes,

when this bit is set, the RTS pin goes Low ; when

this bit is reset, the RTS pin will go High only after

all the bits of the character are transmitted, and the

transmit buffer is empty.

D6 : Transit Underrun/EOM

This bit is set to aone following a hardware or chan-

nel reset, when the transmitter is disabled or when

a Send Abort command (Command 1) is issued.

This bit canonly be reset by the Reset Transmit Un-

derrun/EOM Latch command in the Command Re-

gister. This bit is used to control the transmission of

D0 : Transmitter Enable

Data is not transmitted until this bit is set to a one,

until the Send Break bit is reset and, if Tx Auto En-

ables mode is selected, until theCTS pin is Low. To

32/46

MK68564

CRC at the end of a message in Synchronous

modes. When a transmit underrun condition occurs

and this bit is low. CRC will be appended to the end

of the transmission, and this bit will be set. Only the

0-to-1transition of thisbit causes an External/Status

interrupt, when enabled. Thisbit is not used in Asyn-

chronous modes.

causes the DCD bit to be latched and generates an

External/Status interrupt request, if ena-bled. To

read the current state of the DCD pin, this bit must

be read immediately following aReset External/Sta-

tus Interrupts command (command 2).

D2 : Transmit Buffer Empty

This bit is set to a one, when the transmit buffer be-

comes empty, and when the last CRC bit is trans-

mitted in Synchronous or SDLC modes. This bit is

reset when the transmit buffer is loaded or while the

CRC character is being sent in Synchronous or

SDLC modes. This bit is set to a one following a

hardware or channel reset.

D5 : Clear To Send (CTS)

This bit indicates the inverted state of the CTSinput

pin at the time of the last change of any of the five

External/Status bits. Any transition of the CTS input

causes the CTS bit to be latched and generates an

External/Status interrupt request, if enabled. To

read the current state of the CTS pin, this bit must

be read immediately following aReset External/Sta-

tus Interrupts command (command 2).

D1 : Interrupt Pending

Any interrupt condition, pending in the interrupt

control logic for this channel, will set this bit toa one.

This bit isresetto zero by a hardware channel reset,

or when all the interrupt conditions are cleared.

D4 : Hunt/Sync

In Asynchronous modes, this bit indicates the inver-

ted state of the SYNC input pin at the timeof the last

change of any of the five External/Status bits. Any

transition of the SYNC input causes the Hunt/Sync

bit to be latched and generates an External/Status

interrupt request, if enabled. To read the current

state of the SYNC pin, this bit must be read imme-

diately following a Reset External/Status Interrupt

command (command 2).

D0 : Receive Character Available

This bit is set to a one when a character becomes

available in the receive data FIFO. This bit is reset

to zero when the receive data FIFO (receive buffer)

is read, or by a hardware or channel reset.

STATUS REGISTER 1 (STAT 1)

READ ONLY

In External sync mode, the SYNC pin is used by ex-

ternal logic to signal character synchronization is a-

chieved, the SYNC pin is driven Low on the second

rising edge of the Receive Clock (RxC) on which the

last bit of the sync character wasreceived. Once the

SYNCpin is Low, it should be heldLow until the end

of the message and the driven back High. Both

transitions on the SYNC pin cause External/Status

interrupt requests, if enabled. The inverted state of

the SYNC pin is indicated by this bit.

Thisregister contains theSpecial Receive Condition

statusbitsand theResidue codesfortheI-field inthe

SDLCreceive mode. The All Sent bit issetHigh, and

all other bits areresetto aLow by achannel orhard-

D7

D6 D5

D4

D3

D2

D1

D0

END OF

CRC/

RX

PARITY RESIDUE RESIDUE RESIDUE

CODE 2 CODE 1 CODE

ALL

FRAME FRAME OVER- ERROR

0

SENT

ERROR

RUN

ERR

In Monosync, Bisync, and SDLC modes, this bit in-

dicates when the receiver is in the Hunt mode. This

bit is set to a one following a hardware irchannel re-

set, after the Enter Hunt Mode bit is written High,

when the receiver is disabled, or when an Abort se-

quence (SDLC mode) is detected. This bit will re-

main in this state until character synchronization is

achieved. External/Status interrupt requests will be

generated on both transitions of the Hunt/Sync bit.

ware reset.

D7 : End Of Frame (SDLC)

This bit is used only in SDLC mode. When set to a

one, this bit indicates that a valid closing flag has

been received and that the CRC/Framing Error bit

and Residue codes are valid. If receiver interrupts

are enabled, a Special Receive Condition interrupt

will also be generated. This bit can be reset by is-

suing an Error Reset command (command 6). This

bit is also updated by the first character of the follo-

wing frame. This bit is a zero in all modes except for

D3 : Data Carrier Detect (DCD)

Thisbit indicates the inverted state of the DCD input

pin at the time of the last change of any of the five

External/Status bits. Any transition of theDCD input

33/46

MK68564

SDLC.

sidualI-field read intheprevious bytes.These codes

are meaningful only for the transfer in which the End

Of Frame bit is set.This field is set to 000 by achan-

nel or hardware reset and can leave this state only

if SDLC mode is selected, and a character is recei-

ved.

D6 : CRC/Framing Error

In Asynchronous modes, if a Framing Error occurs,

this bit is set to a one for the receive character in

which theframing error occurred. Whenthisbit is set

to a one, a Special Receive Condition interrupt will

be requested, if receiver interrupts are enabled.

I-Field

Bits

I-Field

Bits

In Second

Residue Residue Residue

Code 2 Code 1 Code 0

In

Detectionof aFraming Error adds anadditional one-

half bit time to the character time, so that the Fra-

ming Error is not interpreted as a new start bit.

Previous Previous

Byte

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

In Synchronous and SDLC modes, this bit indicates

the result of comparing the received CRC value to

the appropriate check value. A zero indicates that a

match has occurred. This bit is usually set since

most bit combinations result in anon-zero CRC, ex-

cept for a correctly completed message. Receiver

interrupts are not requested by the CRC Error bit.

I-Fiel Bits are Right-justified in all Cases.

The CRC/Framing bit is not latched in any receiver

mode. It is always updated when the next character

is received. An Error Reset command (command 6)

will always reset this bit to zero.

FOR EIGHT BITS PER CHARACTER

Ifareceivecharacter length, different fromeight bits,

is used for the I-field, a table similar to the previous

one maybe constructed for each different character

D5 : Receive Overrun Error

This bit indicates that the receive data FIFO has o-

verflowed. Only the character that has been written

over is flagged with this error. When the character

is read, the error condition is latched until reset by

the Error Reset command (command 6). If receiver

interrupts are enabled, the overrun character and all

subsequent characters received, until the Error Re-

set command is issued, will generate a Special Re-

ceive Condition interrupt request.

Bits Per Character Residue Residue Residue

Code 2 Code 1 Code 0

8 Bits Per Character

7 Bits Per Character

6 Bits Per Character

5 Bits Per Character

0

1

0

1

0

1

0

1

length. For no residue (that is, the last character

boundary coincides with the boundary of the I-field

and CRC field), the Residue codes are as follows :

D4 : Parity Error

D0 : All Sent

When parity is enabled, this bit is set to a one for

those characters whose parity does not match the

programmed sense (even/odd). This bit is latched

so that once an error occurs, it remains set until the

ErrorReset command (command 6) is issued. If pa-

rity is a Special Receive Condition, a Parity isa Spe-

cial Receive Condition, a Parity Error will cause a

Special Receive Condition interrupt request on the

character containing theerror and onall subsequent

characters until the Error Resetcommand isissued.

This bit is only active in Asynchronous modes ; it is

always High in Synchronous or SDLC modes. This

bitisLowwhile thetransmitter issending characters :

it will go High only after all the bits of the character

are transmitted, and the transmit buffer is empty.

DATA REGISTER (DATARG)

The Data Register is actually two separate regis-

ters ; a write only register that is the Transmit Buffer,

and a read only register that is the Receiver Buffer.

TheReceiver Buffer isalso thetop register of athree

D3, D2, D1 : Residue Codes 2, 1, and 0

D 7

D 6

D5

D 4

D 3

D 2

D 1

D 0

In thosecases of theSDLCreceive mode, where the

I-field is not an integral multiple of the character

length, these three bits indicate the length of the re-

DATA DATA DATA DATA DATA DATA DATA DATA

7

6

5

4

3

2

1

0

34/46

MK68564

register stack called thereceive data FIFO. TheDa-

ta Register is not affected by a channel or hardware

reset.

TxC pin is an input, and an external source must

supplythetransmitter clock. Thetransmit clockis al-

ways the signal on the TxC pin.

TIME CONSTANT REGISTER (TCREG)

D1 : Divide By 64/4

This register contains the time constant used by the

down counter in the baud rate generator. The time

constant may be changed at any time, but the new

valuedoes not take effectuntil thenexttimethetime

constant is loaded into the down counter. It is re-

commended that the BRG be disabled before wri-

ting to this register, as no attempt was made to

This bit specifies the minimum BRG input clock cy-

cles to output clock cycle. This minimum occurs

when the Time Constant Register is loaded with a

”01H” value. When this bit is set to a one, 64 input

clocksare required foreveryoutput clock.When this

bit is a zero, four input clocks are required for every

output clock.

D7

D6

D5

D4

D3

D2

D1

D0

D0 : Baud Rate Generator Enable

TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0

This bitcontrols the operation of thebaud rate gene-

rator.When thisbit is set to a one, the BRG will start

counting down from the value left in the down coun-

ter when this bit was last reset to zero. If the Time

ConstantRegister is loadedwhilethis bit isreset, the

new time constant value is loaded immediately into

the down counter. The baud rate generator is disa-

bled from counting when this bit is reset.

synchronize the loading of a new time constant with

the clock used to drive the BRG. This register is re-

set to ”00H” by a channel or hardware reset.

BAUD RATE GENERATOR CONTROL RE-

GISTER (BRGCTL)

This register contains the control bits used to pro-

D7 D6 D5 D4

D3

D2

D1

D0

INTERRUPT VECTOR REGISTER

(VECTRG)

RxC

TxC

DIVIDE

BRG

INT/EXT INT/EXT BY 64/4 ENABLE

This register is used to hold a vector that is passed

to the CPU during an interrupt acknowledge cycle.

This register can also be accessed through a

read/write cycle. IftheStatus AffectsVector bit inthe

Interrupt Control Register is disabled, the value pro-

grammed into the Vector Register will be passed to

the CPU during an interrupt acknowledge cycle or

a read cycle. If the Status Affects Vector bit in either

channel is enabled, the lower three bits of this regis-

ter are modified, according to the table listed in the

Interrupt Control Register description. With Status

Affects Vector on, and no interrupt pending in the

SIO, the lower three bits will be read as 011. Only

gram the baud rate generator and to select the BRG

output mode. This register is reset to ”00H” by a

channel or hardware reset.

D7, D6, D5, D4 : Not Used (read as zeros)

D3 : Receiver Clock, Internal/External

This bit determines the direction of the RxC pin.

Whenthis bit is setto aone,theRxC pinis theoutput

of the baud rate generator. If this bit is a zero, the

RxC pin is an input, and an external source must

supply the receiver clock. The receiver clock is al-

ways the signal on the RxC pin, except in Loop

Mode,when thetransmitterclock is connected inter-

nally to the receiver clock.

D 7

D 6

D5

D 4

D 3

D 2

D 1

D 0

V7

V6

V5

V4

V3

V2

*

V1

*

V0

*

D2 : Transmitter Clock, Internal/External

o_{* Variable if Status Affects Vectors is Enabled.}

n

e Vector Register exists in the SIO, but it canbe ac-

This bit determines the direction of the TxC pin.

Whenthis bitis set to aone, theTxCpinisthe output

of the baud rate generator. If this bit is a zero, the

35/46

MK68564

MK68564 ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

– 25 to 100

– 65 to 150

– 3 to 7

1.5

Unit

°C

V

Temperature Under Bias

Storage Temperature

Voltage on Any Pin with Respect to Ground

Power Dissipation

W

Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress

rating only functional operation of the device at these or any other condition above those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliabi-

DC ELECTRICAL CHARACTERISTICS

(V_CC= 5.0V ± 5%, T_A= 0 to 70°C)

Symbol

V_IH

Parameter

Input High Voltage ; all Inputs

Min.

Max.

Unit.

V

V_SS+ 2.0

V_CC

V_IL

Input Low Voltage ; all Inputs

V_SS– 0.3 V_SS+ 0.8

V

I_{L L}

Power Supply Current ; Outputs Open

Input Leakage Current (V_IN= 0 to 5.25)

Three-state Input Current DTACK, D0-D7, SYNC, TxC, RxC

190

mA

µA

I_IN

± 10

I_TSI

20

± 10

µA

0 < V_IN< V_CC

,

INTR

V_OH

Output High Voltage

(I_LOAD= – 400 µA, V_CC= MIN) DTACK, D0-D7

(I_LOAD= – 150 µA, V_CC= MIN) All Other Outputs

(except XTAL2 & INTR)*

V_SS+ 2.4

V

V_OL

Output Low Voltage

(I_LOAD= 5.3mA, V_CC= MIN) INTR, DTACK, D0-D7

(I_LOAD= 2.4mA, V_CC= MIN) All Other Outputs

(except XTAL2)*

0.05

CAPACITANCE

T_A= 25°C, F = 1MHz Unmeasured Pins Returned to Ground.

Symbol

Parameter

Test Conditions

Max.

Unit.

C_IN

Input Capacitance CS, IACK

All Others

15

10

pF

Unmeasured Pins Returned to

Ground

C_OUT

Tri-state Output Capacitance

10

pF

36/46

MK68564

AC ELECTRICAL CHARACTERISTICS

(V_CC= 5.0 VDC ± 5%, GND = 0 VDC, T_A= 0 to 70°C)

4.0 MHz

5.0 MHz

Number

Parameter

Unit

Notes

Min.

Max.

Min.

Max.

1

2

CLK Period

250

105

1000

200

80

1000

ns

CLK Width High

CLK Width Low

CLK Fall Time

CLK Rise Time

3

80

4

30

5

6

CS Low to CLK High (setup time)

A1-A5 Valid to CS Low (setup time)

DATA Valid to CS Low (write cycle)

CS Width High

0

1

7

8

0

9

50

0

50

0

10

11

DTACK Low to A1-A5 Invalid (hold time)

DTACK Low to DATA Invalid

(write cycle hold time)

0

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

CS High to DTACK High (delay)

CLK High to DTACK Low

55

50

ns

320

295

R/W Valid to CS Low (setup time)

DTACK Low to R/W Invalid (hold time)

CLK Low to DATA Out

0

450

105

450

100

CS High to DATA Out Invalid (hold time)

CS High to DTACK High Impedance

DTACK Low to CS High

0

11

0

DATA Valid to DTACK Low

IACK Width High

70

50

0

70

50

0

1

2

IACK Low to CLK High (setup time)

CLK Low to INTR Disabled

CLK Low to DATA Out

410

330

410

330

DTACK Low to IACK, IEI, High

IACK High to DTACK High

IACK High to DTACK High Impedence

IACK High to DATA Out Invalid (hold time)

DATA Valid to DTACK Low

CLK Low to IEO Low

0

55

50

105

100

0

195

2

3

4

5

220

140

190

200

220

140

190

200

IEI Low to IEO Low

IEI High to IEO High

IACK High to IEO High

IACK High to INTR Low

IEI Low to CLK Low (setup time)

IEI Low to INTR Disabled

10

55

10

55

425

225

425

225

6

IEI Low to DATA Out Valid

DATA Out Valid to DTACK Low

IACK High to DATA Out High Impedence

120

90

37/46

MK68564

AC ELECTRICAL CHARACTERISTICS (continued)

(V_CC= 5.0 VDC ± 5%, GND = 0 VDC, T_A= 0 to 70°C)

4.0 MHz

5.0 MHz

Number

Parameter

Unit

Notes

Min.

Max.

Min.

Max.

40

41

42

43

44

CS HIGH TO DATA Out High Impedence

CS or IACK High to CLK Low

120

90

ns

100

7

TxRDY or RxRDY Width Low

3

CLK’s

ns

8, 10

CLK High TxRDY or RxRDY Low

CLK High to TxRDY or RxRDY High

300

ns

IACK High to CS Low or CS High to IACK Low

(not shown)

50

ns

1

9

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

CTS, DCD, SYNC Pulse Width High

CTS, DCD, SYNC Pulse Width Low

TxC Period

200

1000

180

200

800

180

ns

DC

300

9

DC

300

9

ns

TxC Width Low

ns

TxC Width High

ns

TxC Low to TxD Delay (X1 Mode)

TxC Low to INTR Low Delay

RxC Period

ns

5

1000

180

0

5

CLK’s

ns

10

9

DC

800

180

0

DC

RxC Width Low

ns

RxC Width High

ns

RxD to RxC High Setup Time (X1 mode)

RxC High to RxD Hold Time (X1 mode)

RxC High to INTR Low Delay

RxC High to SYNC Low Delay (output modes)

RESET Low

ns

140

10

140

10

4

ns

13

7

13

7

CLK’s

CLK

ns

10

4

1

XTAL 1 Width High (TTL in)

XTAL 1 Width Low (TTL in)

XTAL 1 Period (TTL in)

XTAL 1 Period (crystal in)

100

250

80

200

ns

2000

1000

2000

1000

ns

Notes : 1. This specification only applies if the SIO has completed all operations initiated by the previous bus cycle, when CS

or IACK was asserted. Following a read, write, or interrupt acknoledge cycle, all operations are complete within two

CLK cycles after the rising edge of CS or IACK. If CS or IACK is asserted prior to the completion of the internal

operations, the new bus cycle will be postponed.

2. If IEI meets the setup time to the falling edge of CLK, 1 1/2 cycles following the clocking in of IACK.

3. No internal interrupt request pending at the start of an interrupt acknoledge cycle.

4. Time starts when first signal goes invalid (high).

5. If an internal interrupt is pending at the end of the interrupt acknoledge cycle.

6. If Note 2 timing is not met.

7. If this spec is met, the delay listed in Note 1 will be one CLK cycle instead of two.

8. Ready signals will be negated asynchronous to the CLK, if the condition causing the assertion of the signals is

cleared.

9. If RxC and TxC are asynchronous to the System Clock, the maximum clock rate into RxC and TxC should be no

more than one-fifth the System Clock rate. If RxC and TxC are synchronized to the falling edge of the System

Clock, the maximum clock rate into RxC and TxC can be one-fourth the System Clock rate.

10. System Clock.

11. Due to the dynamic nature of the internal data bus, if CS is held low for more than a few hundred milliseconds the

38/46

MK68564

Figure 13 : Output Test Load.

Figure 14 : INTR Test Load.

For all Outputs Except

DTACK, D0-D7

INTR, XTAL2

C_L= 130pf

R_L= 16KΩ

R₁= 450Ω

DTACK, D0-D7

C_L= 130pf

R_L= 6KΩ

for

Note : XTAL2 Output Test Load is a Crystal.

R₁= 200Ω

Figure 15 :

Read Cycle.

Note : Waveform Measurement for all Inputs and Outputs are Specified at Logic High = 2.0 Volts, Logic Low = 0.8 Volts.

39/46

MK68564

Figure 16 : Write Cycle.

V000390