MK66FX1M0VMD18_技术文档

NXP Semiconductors

Data Sheet: Technical Data

K66P144M180SF5V2

Rev. 4, 04/2017

Kinetis K66 Sub-Family

MK66FN2M0VMD18

180 MHz ARM® Cortex®-M4F Microcontroller.

MK66FX1M0VMD18

MK66FN2M0VLQ18

MK66FX1M0VLQ18

The K66 sub-family members provide greater performance,

memory options up to 2 MB total flash and 256 KB of SRAM, as

well as higher peripheral integration with features such as Dual

USB and a 10/100 Mbit/s Ethernet MAC. These devices maintain

hardware and software compatibility with the existing Kinetis

family. This product also offers:

• Integration of a High Speed USB Physical Transceiver

• Greater performance flexibility with a High Speed Run

mode

• Smarter peripherals with operation in Stop modes

144 MAPBGA (MD)

13 mm x 13 mm Pitch 1 20 mm x 20 mm Pitch

mm 0.5 mm

144 LQFP (LQ)

Performance

• Up to 180 MHz ARM Cortex-M4 based core with DSP

instructions and Single Precision Floating Point unit

Memories and memory expansion

• Up to 2 MB program flash memory on non-

FlexMemory devices with 256 KB RAM

• Up to 1 MB program flash memory and 256 KB of

FlexNVM on FlexMemory devices

• 4 KB FlexRAM on FlexMemory devices

• FlexBus external bus interface and SDRAM controller

System and Clocks

• Multiple low-power modes to provide power

optimization based on application requirements

• Memory protection unit with multi-master protection

• 3 to 32 MHz main crystal oscillator

Analog modules

• 32 kHz low power crystal oscillator

• 48 MHz internal reference

• Two 16-bit SAR ADCs and two 12-bit DAC

• Four analog comparators (CMP) containing a 6-bit

DAC and programmable reference input

• Voltage reference 1.2V

Security

• Hardware random-number generator

• Supports DES, AES, SHA accelerator (CAU)

• Multiple levels of embedded flash security

Communication interfaces

• Ethernet controller with MII and RMII interface to

external PHY and hardware IEEE 1588 capability

• USB high-/full-/low-speed On-the-Go with on-chip

high speed transceiver

• USB full-/low-speed OTG with on-chip transceiver

• Two CAN, three SPI and four I2C modules

• Low Power Universal Asynchronous Receiver/

Transmitter 0 (LPUART0) and five standard UARTs

• Secure Digital Host Controller (SDHC)

• I2S module

Timers

• Four Periodic interrupt timers

• 16-bit low-power timer

• Two 16-bit low-power timer PWM modules

• Two 8-channel motor control/general purpose/PWM

timers

• Two 2-ch quad decoder/general purpose timers

• Real-time clock

Human-machine interface

Operating Characteristics

• Low-power hardware touch sensor interface (TSI)

• General-purpose input/output

• Voltage/Flash write voltage range:1.71 to 3.6 V

• Temperature range (ambient): -40 to 105°C

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Ordering Information 1

Memory

Part Number

Maximum number of I\O's

Flash

SRAM

MK66FN2M0VMD18

MK66FX1M0VMD18

MK66FN2M0VLQ18

MK66FX1M0VLQ18

2 MB

1.25 MB

2 MB

256 KB

100

1.25 MB

1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search.

Related Resources

Type

Selector

Description

Resource

Solution Advisor

The NXP Solution Advisor is a web-based tool that features interactive

application wizards and a dynamic product selector.

Guide

Reference

Manual

The Reference Manual contains a comprehensive description of the

structure and function (operation) of a device.

K66P144M180SF5RMV2¹

This document.

Data Sheet

The Data Sheet includes electrical characteristics and signal

connections.

Chip Errata

The chip mask set Errata provides additional or corrective information for Kinetis_K_0N65N ¹

a particular device mask set.

Package

drawing

Package dimensions are provided in package drawings.

• MAPBGA 144-pin :

98ASA00222D¹

• LQFP 144-pin:

98ASS23177W¹

1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.

2

Kinetis K66 Sub-Family, Rev. 4, 04/2017

NXP Semiconductors

Kinetis K66 Sub-Family

ARM^®Cortex^®-M4

Core

System

Memories and Memory Interfaces

Clocks

Internal

and external

watchdogs

Program

flash

Phase-

locked loop

RAM

Debug

Memory

protection

Frequency-

locked loop

FlexMemory

DSP

Cache

interfaces

Serial

Low/high

frequency

oscillators

Interrupt

Floating-

point unit

External

bus

programming

DMA

controller

interface

Internal

reference

clocks

Low-leakage

wakeup

SDRAM

controller

Security

and Integrity

Communication Interfaces

Human-Machine

Interface (HMI)

Analog

Timers

I²C

x4

16-bit ADC

x2

I²S

x1

Timers

x4 (20ch)

CRC

GPIO

Xtrinsic

touch-sensing

interface

Random

number

generator

Carrier

modulator

transmitter

Analog

comparator

x4

UART

x5

Secure

Digital

Hardware

encryption

Programmable

delay block

SPI

x3

USB LS/FS

OTG

controller

with

6-bit DAC

x4

Periodic

interrupt

timers

CAN

x2

12-bit DAC

x2

transceiver

Voltage

reference

USB LS/FS/HS

OTG

controller

with

Low power

timer

IEEE 1588

Ethernet

Independent

real-time

clock

transceiver

LPUART

USB DCD/

USBHSDCD

IEEE 1588

Timers

USB voltage

regulator

Low power

TPM x 2 (4ch)

Figure 1. K66 Block Diagram

Kinetis K66 Sub-Family, Rev. 4, 04/2017

3

NXP Semiconductors

Table of Contents

1 Ratings....................................................................................5

3.7 Timers..............................................................................54

3.8 Communication interfaces............................................... 54

1.1 Thermal handling ratings................................................. 5

1.2 Moisture handling ratings................................................ 5

1.3 ESD handling ratings.......................................................5

1.4 Voltage and current operating ratings............................. 5

2 General................................................................................... 6

2.1 AC electrical characteristics.............................................6

2.2 Nonswitching electrical specifications..............................7

3.8.1

3.8.2

Ethernet switching specifications...................... 55

USB Voltage Regulator Electrical

Specifications....................................................58

USB Full Speed Transceiver and High Speed

PHY specifications............................................ 59

USB DCD electrical specifications.................... 60

CAN switching specifications............................ 60

DSPI switching specifications (limited voltage

range)................................................................60

DSPI switching specifications (full voltage

3.8.3

3.8.4

3.8.5

3.8.6

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.2.7

2.2.8

Voltage and current operating requirements.....7

LVD and POR operating requirements............. 8

Voltage and current operating behaviors.......... 9

Power mode transition operating behaviors......10

Power consumption operating behaviors..........12

EMC radiated emissions operating behaviors...16

Designing with radiated emissions in mind....... 17

Capacitance attributes...................................... 17

3.8.7

range)................................................................62

Inter-Integrated Circuit Interface (I2C) timing....64

UART switching specifications..........................65

3.8.8

3.8.9

3.8.10 Low Power UART switching specifications....... 65

3.8.11 SDHC specifications......................................... 66

3.8.12 I2S switching specifications.............................. 67

3.9 Human-machine interfaces (HMI)....................................73

2.3 Switching specifications...................................................17

2.3.1

2.3.2

Device clock specifications............................... 17

General switching specifications.......................18

2.4 Thermal specifications.....................................................19

3.9.1

TSI electrical specifications...............................73

2.4.1

2.4.2

Thermal operating requirements.......................19

Thermal attributes............................................. 19

4 Dimensions............................................................................. 73

4.1 Obtaining package dimensions....................................... 73

5 Pinout......................................................................................74

5.1 K66 Signal Multiplexing and Pin Assignments.................74

5.2 Recommended connection for unused analog and

3 Peripheral operating requirements and behaviors.................. 21

3.1 Core modules.................................................................. 21

3.1.1

3.1.2

Debug trace timing specifications..................... 21

JTAG electricals................................................21

digital pins........................................................................81

5.3 K66 Pinouts..................................................................... 82

6 Ordering parts......................................................................... 84

6.1 Determining valid orderable parts....................................84

7 Part identification.....................................................................85

7.1 Description.......................................................................85

7.2 Format............................................................................. 85

7.3 Fields............................................................................... 85

7.4 Example...........................................................................86

8 Terminology and guidelines.................................................... 86

8.1 Definitions........................................................................86

8.2 Examples.........................................................................87

8.3 Typical-value conditions.................................................. 87

8.4 Relationship between ratings and operating

3.2 System modules.............................................................. 24

3.3 Clock modules................................................................. 24

3.3.1

3.3.2

3.3.3

3.3.4

MCG specifications........................................... 24

IRC48M specifications...................................... 27

Oscillator electrical specifications..................... 28

32 kHz oscillator electrical characteristics.........31

3.4 Memories and memory interfaces................................... 31

3.4.1

3.4.2

3.4.3

3.4.4

Flash (FTFE) electrical specifications............... 31

EzPort switching specifications.........................36

Flexbus switching specifications....................... 37

SDRAM controller specifications.......................40

3.5 Security and integrity modules........................................ 43

3.6 Analog............................................................................. 43

3.6.1

3.6.2

3.6.3

3.6.4

ADC electrical specifications.............................43

CMP and 6-bit DAC electrical specifications.....48

12-bit DAC electrical characteristics................. 50

Voltage reference electrical specifications........53

requirements....................................................................88

8.5 Guidelines for ratings and operating requirements..........88

9 Revision History...................................................................... 89

4

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NXP Semiconductors

Ratings

1 Ratings

1.1 Thermal handling ratings

Symbol

T_STG

Description

Min.

–55

—

Max.

150

Unit

°C

Notes

Storage temperature

Solder temperature, lead-free

1

2

T_SDR

260

°C

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Symbol

Description

Min.

Max.

Unit

Notes

MSL

Moisture sensitivity level

—

3

—

1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.3 ESD handling ratings

Symbol

V_HBM

Description

Min.

-2000

-500

Max.

+2000

+500

Unit

V

Notes

Electrostatic discharge voltage, human body model

1

2

V_CDM

Electrostatic discharge voltage, charged-device

model

V

I_LAT

Latch-up current at ambient temperature of 105°C

-100

+100

mA

3

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human

Body Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

1.4 Voltage and current operating ratings

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NXP Semiconductors

General

Symbol

Description

Min.

–0.3

—

Max.

3.8

Unit

V

V_DD

I_DD

Digital supply voltage

Digital supply current

300

mA

V

V_DIO

Digital¹input voltage,including RESET_b

Analog¹input voltage, including EXTAL32 and XTAL32

Maximum current single pin limit (digital output pins)

Analog supply voltage

–0.3

–25

V_DD+ 0.3

25

V_AIO

V

I_D

mA

V

V_DDA

V_DD– 0.3

–0.3

V_DD+ 0.3

3.63

V_{USB0_DP}

V_{USB1_DP}

V_{USB0_DM}

V_{USB1_DM}

USB0_DP input voltage

V

USB1_DP input voltage

3.63

V

USB0_DM input voltage

3.63

V

USB1_DM input voltage

3.63

V

V_{USB1_VBUS}USB1_VBUS detect voltage

6.0

V

VREG_IN0, USB regulator input

VREG_IN1

6.0

V

V_BAT

RTC battery supply voltage

–0.3

3.8

V

1. Digital pins have a general purpose I/O port assigned (e.g. PTA0). Analog pins do not have an associated general

purpose I/O port.

2 General

2.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

High

Low

V_IH

80%

50%

20%

Input Signal

Midpoint1

V_IL

Fall Time

Rise Time

The midpoint is V_IL+ (V_IH- V_IL) / 2

Figure 2. Input signal measurement reference

All digital I/O switching characteristics assume:

1. output pins

6

Kinetis K66 Sub-Family, Rev. 4, 04/2017

NXP Semiconductors

General

• have C_L=30pF loads,

• are slew rate disabled, and

• are normal drive strength

2. input pins

• have their passive filter disabled (PORTx_PCRn[PFE]=0)

2.2 Nonswitching electrical specifications

2.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

Symbol

V_DD

Description

Min.

1.71

–0.1

1.71

Max.

3.6

0.1

3.6

Unit

V

Notes

Supply voltage

V_DDA

Analog supply voltage

V

V_DD– V_DDAV_DD-to-V_DDAdifferential voltage

V_SS– V_SSAV_SS-to-V_SSAdifferential voltage

V

V_BAT

V_IH

RTC battery supply voltage

Input high voltage

V

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.71 V ≤ V_DD≤ 2.7 V

0.7 × V_DD

—

V

0.75 × V_DD

V_IL

Input low voltage

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.71 V ≤ V_DD≤ 2.7 V

—

0.35 × V_DD

0.3 × V_DD

V

V_HYS

I_ICDIO

Input hysteresis

Digital¹input pin negative DC injection current

(except RTC_WAKEUP pins) — single pin

0.06 × V_DD

-5

—

V

2

mA

• V_IN< V_SS-0.3V

I_ICAIO

Analog¹input pin DC injection current — single pin

• V_IN< V_SS-0.3V (Negative current injection)

mA

-5

—

I_ICcont

Contiguous pin DC injection current —regional limit,

includes sum of negative injection currents of 16

contiguous pin

-25

mA

• Negative current injection

V_ODPU

V_RAM

Pseudo Open drain pullup voltage level

V_DDvoltage required to retain RAM

V_DD

1.2

V_DD

—

V

3

V_RFVBATV_BATvoltage required to retain the VBAT register file V_{POR_VBAT}

—

Kinetis K66 Sub-Family, Rev. 4, 04/2017

7

NXP Semiconductors

General

1. Digital pins have a general purpose I/O port assigned (e.g. PTA0). Analog pins do not have an associated general

purpose I/O port.

2. All digital and analog I/O pins are internally clamped to V_SSthrough an ESD protection diode. There is no diode

connection to V_DD. If V_INis less than VSS-0.3V, a current limiting resistor is required. The minimum negative DC

injection current limiting resistor value is calculated as R=(-0.3-V_IN)/|I_ICDIO| or R=(-0.3-V_IN)/|I_ICAIO|. The actual resistor

should be an order of magnitude higher to tolerate transient voltages.

3. Open drain outputs must be pulled to VDD.

2.2.2 LVD and POR operating requirements

Table 2. V_DDsupply LVD and POR operating requirements

Symbol Description

Min.

0.8

Typ.

1.1

Max.

1.5

Unit

V

Notes

V_POR

Falling VDD POR detect voltage

V_LVDH

Falling low-voltage detect threshold — high

range (LVDV=01)

2.48

2.56

2.64

V

Low-voltage warning thresholds — high range

• Level 1 falling (LVWV=00)

1

V_LVW1H

V_LVW2H

V_LVW3H

V_LVW4H

2.62

2.72

2.82

2.92

2.70

2.80

2.90

3.00

2.78

2.88

2.98

3.08

V

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

V_HYSH

V_LVDL

Low-voltage inhibit reset/recover hysteresis —

high range

—

80

—

mV

V

Falling low-voltage detect threshold — low

range (LVDV=00)

1.54

1.60

1.66

Low-voltage warning thresholds — low range

• Level 1 falling (LVWV=00)

1

V_LVW1L

V_LVW2L

V_LVW3L

V_LVW4L

1.74

1.84

1.94

2.04

1.80

1.90

2.00

2.10

1.86

1.96

2.06

2.16

V

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

V_HYSL

Low-voltage inhibit reset/recover hysteresis —

low range

—

60

—

mV

V_BG

t_LPO

Bandgap voltage reference

0.97

900

1.00

1.03

V

Internal low power oscillator period — factory

trimmed

1000

1100

μs

1. Rising threshold is the sum of falling threshold and hysteresis voltage

Table 3. VBAT power operating requirements

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_{POR_VBAT}Falling VBAT supply POR detect voltage

0.8

1.1

1.5

V

8

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NXP Semiconductors

General

2.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

V_OH

Output high voltage — normal drive pad

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= -10mA

• 1.71 V ≤V_DD≤ 2.7 V, I_OH= -5mA

V_DD– 0.5

—

V

Output high voltage — High drive pad

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= -20mA

V_DD– 0.5

—

V

• 1.71 V ≤ V_DD≤ 2.7 V, I_OH= -10mA V_DD– 0.5

I_OHT

Output high current total for all ports

—

100

mA

V

V_{OH_RTC_WAKEUP}Output high voltage— normal drive pad

• 2.7 V ≤ V_BAT≤ 3.6 V, I_OH= -5 mA

V_BAT– 0.5

—

V

• 1.71 V ≤ V_BAT≤ 2.7 V, I_OH= -2.5

mA

I_{OH_RTC_WAKEUP}Output high current total for

RTC_WAKEUP pins

—

100

mA

V_OL

Output low voltage — normal drive pad

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 10 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OL= 5 mA

—

0.5

V

Output low voltage — high drive pad

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 20 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OL= 10 mA

—

0.5

V

I_OLT

Output low current total for all ports

—

100

mA

V

V_{OL_RTC_WAKEUP}Output low voltage— normal drive pad

• 2.7 V ≤ V_BAT≤ 3.6 V, I_OL= 5 mA

—

0.5

V

• 1.71 V ≤ V_BAT≤ 2.7 V, I_OL= 2.5mA

I_{OL_RTC_WAKEUP}Output low current total for

RTC_WAKEUPpins

—

100

0.5

mA

µA

I_IN

Input leakage current, analog and digital

0.002

1

pins

• V_SS≤ V_IN≤ V_DD

I_{OZ_RTC_WAKEUP}Hi-Z (off-state) leakage current (per

RTC_WAKEUP pin)

—

0.25

µA

R_PU

R_PD

Internal pullup resistors

20

—

50

kΩ

2

3

Internal pulldown resistors

1. Measured at VDD=3.6V

2. Measured at V_DDsupply voltage = V_DDmin and Vinput = V_SS

Kinetis K66 Sub-Family, Rev. 4, 04/2017

9

NXP Semiconductors

General

3. Measured at V_DDsupply voltage = V_DDmin and Vinput = V_DD

2.2.4 Power mode transition operating behaviors

All specifications except t_POR, and VLLSx –> RUN recovery times in the following

table assume this clock configuration:

• CPU and system clocks = 100MHz

• Bus clock = 50MHz

• FlexBus clock = 50 MHz

• Flash clock = 25 MHz

• MCG mode=FEI

Table 5. Power mode transition operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

t_POR

After a POR event, amount of time from the point V_DD

reaches 1.71 V to execution of the first instruction

across the operating temperature range of the chip.

—

300

µs

—

172

94

µs

• VLLS0 –> RUN

• VLLS1 –> RUN

• VLLS2 –> RUN

• VLLS3 –> RUN

• LLS2 –> RUN

• LLS3 –> RUN

• VLPS –> RUN

• STOP –> RUN

94

5.8

5.4

Table 6. Low power mode peripheral adders — typical value

Symbol

Description

Temperature (°C)

Unit

-40

25

50

70

85

105

I_IREFSTEN4MHz4 MHz internal reference clock (IRC) adder.

Measured by entering STOP or VLPS mode

with 4 MHz IRC enabled.

56

µA

Table continues on the next page...

10

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NXP Semiconductors

General

Table 6. Low power mode peripheral adders — typical value (continued)

Symbol

Description

Temperature (°C)

Unit

-40

25

50

70

85

105

I_IREFSTEN32KH32 kHz internal reference clock (IRC) adder.

52

µA

Measured by entering STOP mode with the

z

32 kHz IRC enabled.

I_EREFSTEN4MHExternal 4 MHz crystal clock adder. Measured 206

228

237

245

251

258

uA

nA

by entering STOP or VLPS mode with the

z

crystal enabled.

I_EREFSTEN32KExternal 32 kHz crystal clock adder by means

of the OSC0_CR[EREFSTEN and

Hz

EREFSTEN] bits. Measured by entering all

modes with the crystal enabled.

440

490

510

511

22

490

560

520

22

540

560

545

22

560

556

22

570

610

563

22

580

680

576

22

VLLS1

VLLS3

LLS2

LLS3

VLPS

STOP

I_48MIRC

I_CMP

48MHz IRC

µA

CMP peripheral adder measured by placing

the device in VLLS1 mode with CMP enabled

using the 6-bit DAC and a single external

input for compare. Includes 6-bit DAC power

consumption.

I_RTC

RTC peripheral adder measured by placing

the device in VLLS1 mode with external 32

kHz crystal enabled by means of the

RTC_CR[OSCE] bit and the RTC ALARM set

for 1 minute. Includes ERCLK32K (32 kHz

external crystal) power consumption.

432

357

388

475

532

810

nA

µA

I_UART

UART peripheral adder measured by placing

the device in STOP or VLPS mode with

selected clock source waiting for RX data at

115200 baud rate. Includes selected clock

source power consumption.

66

MCGIRCLK (4 MHz internal reference clock)

OSCERCLK (4 MHz external crystal)

214

45

234

45

246

45

254

45

260

45

268

45

I_BG

Bandgap adder when BGEN bit is set and

device is placed in VLPx, LLS, or VLLSx

mode.

µA

I_ADC

ADC peripheral adder combining the

366

measured values at V_DDand V_DDAby placing

the device in STOP or VLPS mode. ADC is

configured for low power mode using the

internal clock and continuous conversions.

Kinetis K66 Sub-Family, Rev. 4, 04/2017

11

NXP Semiconductors

General

2.2.5 Power consumption operating behaviors

NOTE

The maximum values represent characterized results

equivalent to the mean plus three times the standard deviation

(mean + 3 sigma)

Table 7. Power consumption operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_DDA

Analog supply current

—

See note

mA

1

2

I_{DD_RUN}Run mode current — all peripheral clocks

disabled, code executing from flash

—

32.3

32.4

71.03

71.81

mA

• @ 1.8V

• @ 3.0V

I_{DD_RUN}Run mode current — all peripheral clocks

enabled, code executing from flash

3, 4

—

50.5

89.58

mA

• @ 1.8V

• @ 3.0V

—

50.6

69.7

55.95

99.85

mA

• @ 25°C

• @ 105°C

I_{DD_RUNC}Run mode current in compute operation - 120

5

6

—

28.5

67.74

mA

MHz core / 24 MHz flash / bus clock disabled,

O

code of while(1) loop executing from flash

• at 3.0 V

I_{DD_HSRUN}Run mode current — all peripheral clocks

disabled, code executing from flash

—

47.2

47.3

91.25

91.62

mA

• @ 1.8V

• @ 3.0V

I_{DD_HSRUN}Run mode current — all peripheral clocks

enabled, code executing from flash

7, 4

—

71.4

103.58

mA

• @ 1.8V

• @ 3.0V

71.5

93.3

79.13

mA

—

• @ 25°C

115.08

• @ 105°C

I_{DD_HSRUN}HSRun mode current in compute operation – 168

—

42.9

16.9

91.97

45.2

mA

5

8

MHz core/ 28 MHz flash / bus clock disabled,

CO

code of while(1) loop executing from flash at 3.0V

I_{DD_WAIT}Wait mode high frequency current at 3.0 V — all

peripheral clocks disabled

—

Table continues on the next page...

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NXP Semiconductors

General

Table 7. Power consumption operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_{DD_WAIT}Wait mode reduced frequency current at 3.0 V —

all peripheral clocks enabled

—

35

62.81

mA

8

I_{DD_VLPR}Very-low-power run mode current at 3.0 V — all

peripheral clocks disabled

—

1.1

2

9.56

9.88

mA

9

I_{DD_VLPR}Very-low-power run mode current at 3.0 V — all

peripheral clocks enabled

10

11

I_{DD_VLPRC}Very-low-power run mode current in compute

—

986

9.47

μA

operation - 4 MHz core / 1 MHz flash / bus clock

O

disabled, LPTMR running with 4 MHz internal

reference clock

• at 3.0 V

I_{DD_VLPW}Very-low-power wait mode current at 3.0 V — all

peripheral clocks disabled

—

0.690

1.5

9.25

mA

12

I_{DD_VLPW}Very-low-power wait mode current at 3.0 V — all

peripheral clocks enabled

10.00

I_{DD_STOP}Stop mode current at 3.0 V

—

0.791

3.8

2.39

6.91

mA

• @ –40 to 25°C

• @ 70°C

13.2

18.91

• @ 105°C

I_{DD_VLPS}Very-low-power stop mode current at 3.0 V

—

202

1400

5100

353.77

2464.54

8949.06

μA

• @ –40 to 25°C

• @ 70°C

• @ 105°C

I_{DD_LLS3}Low leakage stop mode current at 3.0 V

• @ –40 to 25°C

—

9.0

76.3

402

16.5

88.63

656.08

μA

• @ 70°C

• @ 105°C

I_{DD_LLS2}Low leakage stop mode current at 3.0 V

—

5.7

9.7

μA

• @ –40 to 25°C

• @ 70°C

—

41.3

229

55.80

• @ 105°C

276.81

μA

I_{DD_VLLS3}Very low-leakage stop mode 3 current at 3.0 V

—

5.5

46.3

249

7.31

58.33

380.77

μA

• @ –40 to 25°C

• @ 70°C

• @ 105°C

I_{DD_VLLS2}Very low-leakage stop mode 2 current at 3.0 V

—

2.7

3.24

18.72

84.77

μA

• @ –40 to 25°C

• @ 70°C

13.1

76.6

• @ 105°C

Table continues on the next page...

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13

NXP Semiconductors

General

Table 7. Power consumption operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_{DD_VLLS1}Very low-leakage stop mode 1 current at 3.0 V

—

0.847

6.5

1.48

11.31

81.78

μA

• @ –40 to 25°C

• @ 70°C

46.7

• @ 105°C

I_{DD_VLLS0}Very low-leakage stop mode 0 current at 3.0 V

with POR detect circuit enabled

—

0.551

6.3

.65

7.12

53.68

μA

• @ –40 to 25°C

• @ 70°C

49.6

• @ 105°C

I_{DD_VLLS0}Very low-leakage stop mode 0 current at 3.0 V

with POR detect circuit disabled

—

0.254

6.3

0.445

10.99

85.27

μA

• @ –40 to 25°C

• @ 70°C

48.7

• @ 105°C

I_{DD_VBAT}Average current with RTC and 32kHz disabled at

3.0 V

—

0.19

0.49

2.2

0.22

0.64

3.2

μA

• @ –40 to 25°C

• @ 70°C

• @ 105°C

I_{DD_VBAT}Average current when CPU is not accessing RTC

registers

13

• @ 1.8V

0.68

1.2

—

0.8

1.56

5.3

• @ –40 to 25°C

• @ 70°C

μA

3.6

• @ 105°C

• @ 3.0V

• @ –40 to 25°C

• @ 70°C

0.81

1.45

4.3

—

0.96

1.89

6.33

μA

• @ 105°C

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See

each module's specification for its supply current.

2. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE

mode. All peripheral clocks disabled.

3. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE

mode. All peripheral clocks enabled.

4. Max values are measured with CPU executing DSP instructions.

5. MCG configured for PEE mode.

6. 168 MHz core and system clock, 56 MHz bus and FlexBus clock, and 28 MHz flash clock. MCG configured for PEE

mode. All peripheral clocks disabled.

7. 168 MHz core and system clock, 56 MHz bus and FlexBus clock, and 28 MHz flash clock. MCG configured for PEE

mode. All peripheral clocks enabled.

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General

8. 120 MHz core and system clock, 60MHz bus clock, and FlexBus. MCG configured for PEE mode.

9. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral

clocks disabled. Code executing from flash.

10. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral

clocks enabled but peripherals are not in active operation. Code executing from flash.

11. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high,

optimized for balanced.

12. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral

clocks disabled.

13. Includes 32kHz oscillator current and RTC operation.

2.2.5.1 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

• USB regulator disabled

• No GPIOs toggled

• Code execution from flash with cache enabled

• For the ALLOFF curve, all peripheral clocks are disabled except FTFE

Figure 3. Run mode supply current vs. core frequency

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NXP Semiconductors

General

Figure 4. VLPR mode supply current vs. core frequency

2.2.6 EMC radiated emissions operating behaviors

Table 8. EMC radiated emissions operating behaviors

Symbol

Description

Frequency

band

Typ.

Unit

Notes

(MHz)

V_RE1

V_RE2

Radiated emissions voltage, band 1

Radiated emissions voltage, band 2

Radiated emissions voltage, band 3

Radiated emissions voltage, band 4

IEC level

0.15–50

50–150

23

27

28

14

K

dBμV

—

1, 2

V_RE3

150–500

500–1000

0.15–1000

V_RE4

V_{RE_IEC}

2, 3

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement

of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and

Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.

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General

The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,

from among the measured orientations in each frequency range.

2. V_DD= 3.3 V, T_A= 25 °C, f_OSC= 12 MHz (crystal), f_SYS= MHz, f_BUS= MHz

3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and

Wideband TEM Cell Method

2.2.7 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions.

1. Go to nxp.com

2. Perform a keyword search for “EMC design.”

2.2.8 Capacitance attributes

Table 9. Capacitance attributes

Symbol

C_{IN_A}

Description

Min.

—

Max.

Unit

pF

Input capacitance: analog pins

Input capacitance: digital pins

7

C_{IN_D}

—

pF

2.3 Switching specifications

2.3.1 Device clock specifications

Table 10. Device clock specifications

Symbol

f_SYS

Description

Min.

Max.

Unit

Notes

High Speed run mode

System and core clock

—

180

MHz

Normal run mode (and High Speed run mode unless otherwise specified above)

f_SYS

System and core clock

—

120

—

MHz

System and core clock when Full Speed USB in

operation

20

f_{SYS_USBHS}System and core clock when High Speed USB in

operation

100

—

MHz

f_ENET

System and core clock when ethernet in operation

• 10 Mbps

• 100 Mbps

5

—

50

Table continues on the next page...

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NXP Semiconductors

General

Table 10. Device clock specifications (continued)

Symbol

Description

Bus clock

Min.

—

Max.

60

Unit

MHz

Notes

f_BUS

FB_CLK

f_FLASH

FlexBus clock

Flash clock

LPTMR clock

—

60

—

28

f_LPTMR

—

25

VLPR mode¹

f_SYS

f_BUS

System and core clock

Bus clock

—

4

MHz

FB_CLK

f_FLASH

FlexBus clock

4

Flash clock

1

f_ERCLK

f_{LPTMR_pin}

External reference clock

LPTMR clock

16

25

8

f_{FlexCAN_ERCLK}FlexCAN external reference clock

f_{I2S_MCLK}

f_{I2S_BCLK}

I2S master clock

I2S bit clock

12.5

4

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for

any other module.

2.3.2 General switching specifications

These general purpose specifications apply to all signals configured for GPIO, UART,

CAN, CMT, IEEE 1588 timer, timers, and I²C signals.

Table 11. General switching specifications

Symbol

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

1.5

—

Bus clock

cycles

1, 2

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter enabled) — Asynchronous path

100

50

—

ns

3

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter disabled) — Asynchronous path

External reset pulse width (digital glitch filter disabled)

100

2

—

Mode select (EZP_CS) hold time after reset

deassertion

Bus clock

cycles

Port rise and fall time (high drive strength)

• Slew enabled

4

—

25

15

ns

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NXP Semiconductors

Kinetis K66 Sub-Family, Rev. 4, 04/2017

General

Notes

Table 11. General switching specifications (continued)

Symbol

Description

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

• Slew disabled

Min.

Max.

Unit

—

7

ns

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

Port rise and fall time (low drive strength)

• Slew enabled

5

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

—

25

15

ns

• Slew disabled

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

—

7

ns

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses

may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter

pulses can be recognized in that case.

2. The greater synchronous and asynchronous timing must be met.

3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,

and VLLSx modes.

4. 75 pF load

5. 15 pF load

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 12. Thermal operating requirements

Symbol

T_J

Description

Min.

–40

Max.

125

Unit

°C

Notes

Die junction temperature

Ambient temperature

T_A

105

°C

1

1. Maximum T_Acan be exceeded only if the user ensures that T_Jdoes not exceed maximum T_J. The simplest method to

determine T_Jis: T_J= T_A+ R_θJAx chip power dissipation.

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General

2.4.2 Thermal attributes

Board type

Symbol

Description

144 LQFP

144 MAPBGA

Unit

Notes

Single-layer

(1s)

R_θJA

Thermal

45

48

°C/W

1

2

resistance,

junction to

ambient

(natural

convection)

Four-layer

(2s2p)

R_θJA

Thermal

36

30

24

29

38

25

16

resistance,

junction to

ambient

(natural

convection)

Single-layer

(1s)

R_θJMA

R_θJB

Thermal

resistance,

junction to

ambient (200

ft./min. air

speed)

Four-layer

(2s2p)

Thermal

resistance,

junction to

ambient (200

ft./min. air

speed)

—

Thermal

resistance,

junction to

board

—

R_θJC

Thermal

resistance,

junction to case

9

2

9

2

°C/W

3

4

Ψ_JT

Thermal

characterization

parameter,

junction to

package top

outside center

(natural

convection)

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method

Environmental Conditions—Forced Convection (Moving Air).

2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board.

3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

temperature used for the case temperature. The value includes the thermal resistance of the interface material between

the top of the package and the cold plate.

4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

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Peripheral operating requirements and behaviors

3 Peripheral operating requirements and behaviors

3.1 Core modules

3.1.1 Debug trace timing specifications

Table 13. Debug trace operating behaviors

Symbol

T_cyc

T_wl

Description

Min.

Max.

Unit

MHz

ns

Clock period

Frequency dependent

Low pulse width

High pulse width

Clock and data rise time

Clock and data fall time

Data setup

2

—

3

T_wh

T_r

ns

—

1.5

1.0

ns

T_f

3

ns

T_s

—

ns

T_h

Data hold

ns

TRACECLK

T

r

T

f

T

wh

wl

T

cyc

Figure 5. TRACE_CLKOUT specifications

TRACE_CLKOUT

TRACE_D[3:0]

Ts

Th

Ts

Th

Figure 6. Trace data specifications

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Peripheral operating requirements and behaviors

3.1.2 JTAG electricals

Table 14. JTAG limited voltage range electricals

Symbol

Description

Min.

Max.

Unit

V

Operating voltage

2.7

3.6

J1

TCLK frequency of operation

• Boundary Scan

MHz

0

10

25

50

• JTAG and CJTAG

• Serial Wire Debug

J2

J3

TCLK cycle period

TCLK clock pulse width

• Boundary Scan

1/J1

—

ns

50

20

10

—

ns

• JTAG and CJTAG

• Serial Wire Debug

J4

J5

TCLK rise and fall times

—

20

2.0

—

8

3

ns

Boundary scan input data setup time to TCLK rise

Boundary scan input data hold time after TCLK rise

TCLK low to boundary scan output data valid

TCLK low to boundary scan output high-Z

TMS, TDI input data setup time to TCLK rise

TMS, TDI input data hold time after TCLK rise

TCLK low to TDO data valid

—

28

25

—

19

17

—

J6

J7

J8

J9

J10

J11

J12

J13

J14

1

—

100

8

TCLK low to TDO high-Z

TRST assert time

TRST setup time (negation) to TCLK high

Table 15. JTAG full voltage range electricals

Symbol

Description

Min.

Max.

Unit

V

Operating voltage

1.71

3.6

J1

TCLK frequency of operation

• Boundary Scan

MHz

0

10

20

40

• JTAG and CJTAG

• Serial Wire Debug

J2

J3

TCLK cycle period

TCLK clock pulse width

• Boundary Scan

1/J1

—

ns

50

25

—

ns

• JTAG and CJTAG

• Serial Wire Debug

12.5

Table continues on the next page...

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Peripheral operating requirements and behaviors

Table 15. JTAG full voltage range electricals (continued)

Symbol

J4

Description

Min.

Max.

Unit

ns

TCLK rise and fall times

—

3

J5

Boundary scan input data setup time to TCLK rise

Boundary scan input data hold time after TCLK rise

TCLK low to boundary scan output data valid

TCLK low to boundary scan output high-Z

TMS, TDI input data setup time to TCLK rise

TMS, TDI input data hold time after TCLK rise

TCLK low to TDO data valid

20

2.0

—

8

—

J6

J7

30.6

25

J8

J9

—

J10

J11

J12

J13

J14

1.0

—

100

8

—

19.0

17.0

—

TCLK low to TDO high-Z

TRST assert time

TRST setup time (negation) to TCLK high

—

J2

J4

J3

TCLK (input)

J4

Figure 7. Test clock input timing

TCLK

J5

J6

Input data valid

Data inputs

Data outputs

J7

Output data valid

J8

J7

Output data valid

Figure 8. Boundary scan (JTAG) timing

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NXP Semiconductors

Peripheral operating requirements and behaviors

TCLK

TDI/TMS

TDO

J9

J10

Input data valid

J11

Output data valid

J12

J11

TDO

Output data valid

TDO

Figure 9. Test Access Port timing

TCLK

TRST

J14

J13

Figure 10. TRST timing

3.2 System modules

There are no specifications necessary for the device's system modules.

3.3 Clock modules

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Peripheral operating requirements and behaviors

3.3.1 MCG specifications

Table 16. MCG specifications

Symbol Description

Min.

Typ.

Max.

Unit

Notes

f_{ints_ft}

f_{ints_t}

I_ints

Internal reference frequency (slow clock) —

factory trimmed at nominal VDD and 25 °C

—

32.768

—

kHz

Internal reference frequency (slow clock) —

user trimmed

31.25

—

39.0625

kHz

Internal reference (slow clock) current

—

20

—

µA

Δf_{dco_res_t}Resolution of trimmed average DCO output

frequency at fixed voltage and temperature —

using SCTRIM and SCFTRIM

0.3

0.6

%f_dco

1

Δf_{dco_res_t}Resolution of trimmed average DCO output

frequency at fixed voltage and temperature —

using SCTRIM only

—

0.2

0.5

%f_dco

Δf_{dco_t}

Total deviation of trimmed average DCO output

frequency over voltage and temperature

—

0.5

0.3

2

%f_dco

1

Δf_{dco_t}

Total deviation of trimmed average DCO output

frequency over fixed voltage and temperature

range of 0–70°C

1.5

f_{intf_ft}

f_{intf_t}

Internal reference frequency (fast clock) —

factory trimmed at nominal VDD and 25°C

—

3

4

—

5

MHz

Internal reference frequency (fast clock) —

user trimmed at nominal VDD and 25 °C

—

I_intf

Internal reference (fast clock) current

—

25

—

µA

f_{loc_low}

Loss of external clock minimum frequency —

RANGE = 00

(3/5) x

f_{ints_t}

kHz

ext clk freq: above (3/5)f_intnever reset

ext clk freq: between (2/5)fint and (3/5)f_int

maybe reset (phase dependency)

ext clk freq: below (2/5)f_intalways reset

f_{loc_high}Loss of external clock minimum frequency —

RANGE = 01, 10, or 11

(16/5) x

f_{ints_t}

—

kHz

ext clk freq: above (16/5)f_intnever reset

ext clk freq: between (15/5)f_intand (16/5)f_int

maybe reset (phase dependency)

ext clk freq: below (15/5)f_intalways reset

FLL

f_{fll_ref}

FLL reference frequency range

31.25

16.0

—

39.0625

26.66

kHz

f_{dco_ut}

DCO output

Low range

23.04

MHz

2

frequency range

— untrimmed

(DRS=00, DMX32=0)

640 × f_{ints_ut}

Mid range

32.0

46.08

53.32

(DRS=01, DMX32=0)

1280 × f_{ints_ut}

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NXP Semiconductors

Peripheral operating requirements and behaviors

Table 16. MCG specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

Mid-high range

(DRS=10, DMX32=0)

1920 × f_{ints_ut}

48.0

69.12

79.99

High range

64.0

18.3

92.16

26.35

52.70

79.09

105.44

106.65

30.50

60.99

91.53

122.02

(DRS=11, DMX32=0)

2560 × f_{ints_ut}

Low range

(DRS=00, DMX32=1)

732 × f_{ints_ut}

Mid range

36.6

(DRS=01, DMX32=1)

1464 × f_{ints_ut}

Mid-high range

(DRS=10, DMX32=1)

2197 × f_{ints_ut}

54.93

73.23

High range

(DRS=11, DMX32=1)

2929 × f_{ints_ut}

f_dco

DCO output

frequency range

Low range (DRS=00)

640 × f_{fll_ref}

20

40

60

80

—

20.97

41.94

62.91

83.89

23.99

47.97

71.99

95.98

25

50

75

100

—

MHz

ps

3, 4

Mid range (DRS=01)

1280 × f_{fll_ref}

Mid-high range (DRS=10)

1920 × f_{fll_ref}

High range (DRS=11)

2560 × f_{fll_ref}

f_{dco_t_DMX3}DCO output

Low range (DRS=00)

732 × f_{fll_ref}

5, 6

frequency

2

Mid range (DRS=01)

1464 × f_{fll_ref}

—

Mid-high range (DRS=10)

2197 × f_{fll_ref}

—

High range (DRS=11)

2929 × f_{fll_ref}

—

J_{cyc_fll}

FLL period jitter

—

180

150

—

• f_DCO= 48 MHz

• f_DCO= 98 MHz

Table continues on the next page...

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NXP Semiconductors

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Peripheral operating requirements and behaviors

Table 16. MCG specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

t_{fll_acquire}FLL target frequency acquisition time

—

1

ms

7

PLL

f_{pll_ref}

PLL reference frequency range

8

180

90

—

16

360

180

—

MHz

f_{vcoclk_2x}VCO output frequency

f_vcoclk

PLL output frequency

—

MHz

f_{vcoclk_90}PLL quadrature output frequency

I_pll

PLL operating current

8

9

2.8

3.6

mA

• VCO @ 184 MHz (f_{osc_hi_1}= 32 MHz,

f_{pll_ref}= 8 MHz, VDIV multiplier = 23)

I_pll

PLL operating current

—

• VCO @ 360 MHz (f_{osc_hi_1}= 32 MHz,

f_{pll_ref}= 8 MHz, VDIV multiplier = 45)

J_{cyc_pll}

PLL period jitter (RMS)

• f_vco= 180 MHz

—

100

75

—

ps

• f_vco= 360 MHz

J_{acc_pll}

PLL accumulated jitter over 1µs (RMS)

• f_vco= 180 MHz

9

—

600

300

—

ps

• f_vco= 360 MHz

D_unl

Lock exit frequency tolerance

Lock detector detection time

4.47

—

5.97

150 × 10^-6

+ 1075(1/

%

s

t_{pll_lock}

10

f_{pll_ref}

)

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock

mode).

2. This applies when SCTRIM at value (0x80) and SCFTRIM control bit at value (0x0).

3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.

4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency

deviation (Δf_{dco_t}) over voltage and temperature should be considered.

5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.

6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.

7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,

DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

8. Excludes any oscillator currents that are also consuming power while PLL is in operation.

9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of

each PCB and results will vary.

10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL

disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this

specification assumes it is already running.

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3.3.2 IRC48M specifications

Table 17. IRC48M specifications

Symbol

V_DD

Description

Min.

1.71

—

Typ.

—

Max.

3.6

—

Unit

V

Notes

Supply voltage

I_DD48M

f_irc48m

Supply current

520

48

μA

Internal reference frequency

—

MHz

Δf_{irc48m_ol_lv}Open loop total deviation of IRC48M frequency at

1

low voltage (VDD=1.71V-1.89V) over full

—

0.4

0.5

1.0

1.5

%f_irc48m

temperature

• Regulator disable

(USB_CLK_RECOVER_IRC_EN[REG_EN]=0

)

• Regulator enable

(USB_CLK_RECOVER_IRC_EN[REG_EN]=1

)

Δf_{irc48m_ol_hv}Open loop total deviation of IRC48M frequency at

high voltage (VDD=1.89V-3.6V) over 0—70°C

• Regulator enable

1

—

0.2

0.5

%f_irc48m

(USB_CLK_RECOVER_IRC_EN[REG_EN]=1

)

Δf_{irc48m_ol_hv}Open loop total deviation of IRC48M frequency at

high voltage (VDD=1.89V-3.6V) over full

—

0.4

—

1.0

0.1

%f_irc48m

temperature

• Regulator enable

(USB_CLK_RECOVER_IRC_EN[REG_EN]=1

)

Δf_{irc48m_cl}Closed loop total deviation of IRC48M frequency

%f_host

2

3

over voltage and temperature

J_{cyc_irc48m}Period Jitter (RMS)

—

35

2

150

3

ps

μs

t_irc48mst

Startup time

1. The maximum value represents characterized results equivalent to mean plus or minus three times the standard

deviation (mean 3 sigma)

2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It

is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover

function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).

3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the

clock by one of the following settings:

• USB_CLK_RECOVER_IRC_EN[IRC_EN]=1, or

• MCG_C7[OSCSEL]=10, or

• SIM_SOPT2[PLLFLLSEL]=11

3.3.3 Oscillator electrical specifications

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3.3.3.1 Oscillator DC electrical specifications

Table 18. Oscillator DC electrical specifications

Symbol Description

V_DDSupply voltage

Min.

1.71

Typ.

Max.

3.6

Unit

Notes

—

V

I_DDOSCSupply current — low-power mode (HGO=0)

1

• 32 kHz

—

600

200

300

950

1.2

—

nA

μA

mA

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

• 24 MHz

• 32 MHz

1.5

I_DDOSCSupply current — high gain mode (HGO=1)

1

• 32 kHz

—

7.5

500

650

2.5

3.25

4

—

μA

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

μA

mA

• 24 MHz

• 32 MHz

C_x

C_y

R_F

EXTAL load capacitance

XTAL load capacitance

—

2, 3

2, 4

Feedback resistor — low-frequency, low-power

mode (HGO=0)

MΩ

kΩ

Feedback resistor — low-frequency, high-gain

mode (HGO=1)

—

10

—

Feedback resistor — high-frequency, low-

power mode (HGO=0)

Feedback resistor — high-frequency, high-gain

mode (HGO=1)

1

R_S

Series resistor — low-frequency, low-power

mode (HGO=0)

—

Series resistor — low-frequency, high-gain

mode (HGO=1)

200

—

kΩ

Series resistor — high-frequency, low-power

mode (HGO=0)

kΩ

Series resistor — high-frequency, high-gain

mode (HGO=1)

—

0

—

kΩ

V

5

V_pp

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, low-power mode

(HGO=0)

0.6

Table continues on the next page...

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Table 18. Oscillator DC electrical specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

Peak-to-peak amplitude of oscillation (oscillator

—

V_DD

—

V

mode) — low-frequency, high-gain mode

(HGO=1)

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, low-power mode

(HGO=0)

—

0.6

—

V

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, high-gain mode

(HGO=1)

V_DD

1. V_DD=3.3 V, Temperature =25 °C, Internal capacitance = 20 pf

2. See crystal or resonator manufacturer's recommendation

3. C_x,C_ycan be provided by using either the integrated capacitors or by using external components.

4. When low power mode is selected, R_Fis integrated and must not be attached externally.

5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

any other devices.

3.3.3.2 Oscillator frequency specifications

Table 19. Oscillator frequency specifications

Symbol Description

f_{osc_lo}Oscillator crystal or resonator frequency — low-

frequency mode (MCG_C2[RANGE]=00)

Min.

Typ.

Max.

Unit

Notes

32

—

40

kHz

f_{osc_hi_1}Oscillator crystal or resonator frequency — high-

frequency mode (low range)

3

8

—

8

MHz

(MCG_C2[RANGE]=01)

f_{osc_hi_2}Oscillator crystal or resonator frequency — high

frequency mode (high range)

32

(MCG_C2[RANGE]=1x)

f_{ec_extal}Input clock frequency (external clock mode)

t_{dc_extal}Input clock duty cycle (external clock mode)

—

40

—

50

60

—

MHz

%

1, 2

3, 4

t_cst

Crystal startup time — 32 kHz low-frequency,

low-power mode (HGO=0)

750

ms

Crystal startup time — 32 kHz low-frequency,

high-gain mode (HGO=1)

—

250

0.6

—

ms

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), low-power mode

(HGO=0)

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), high-gain mode

(HGO=1)

—

1

—

ms

1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.

2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

3. Proper PC board layout procedures must be followed to achieve specifications.

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4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

register being set.

NOTE

The 32 kHz oscillator works in low power mode by default

and cannot be moved into high power/gain mode.

3.3.4 32 kHz oscillator electrical characteristics

3.3.4.1 32 kHz oscillator DC electrical specifications

Table 20. 32kHz oscillator DC electrical specifications

Symbol

V_BAT

R_F

Description

Min.

1.71

—

Typ.

—

Max.

3.6

—

Unit

V

Supply voltage

Internal feedback resistor

100

5

MΩ

pF

C_para

Parasitical capacitance of EXTAL32 and

XTAL32

—

7

1

V_pp

Peak-to-peak amplitude of oscillation

—

0.6

—

V

1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to

required oscillator components and must not be connected to any other devices.

3.3.4.2 32 kHz oscillator frequency specifications

Table 21. 32 kHz oscillator frequency specifications

Symbol Description

Min.

—

Typ.

32.768

1000

32.768

—

Max.

—

Unit

kHz

ms

Notes

f_{osc_lo}

t_start

Oscillator crystal

Crystal start-up time

—

1

2

f_{ec_extal32}Externally provided input clock frequency

v_{ec_extal32}Externally provided input clock amplitude

—

kHz

mV

700

V_BAT

2, 3

1. Proper PC board layout procedures must be followed to achieve specifications.

2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.

The oscillator remains enabled and XTAL32 must be left unconnected.

3. The parameter specified is a peak-to-peak value and V_IHand V_ILspecifications do not apply. The voltage of the

applied clock must be within the range of V_SSto V_BAT

.

3.4 Memories and memory interfaces

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3.4.1 Flash (FTFE) electrical specifications

This section describes the electrical characteristics of the FTFE module.

3.4.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps are

active and do not include command overhead.

Table 22. NVM program/erase timing specifications

Symbol Description

Min.

—

Typ.

7.5

Max.

18

Unit

μs

Notes

t_hvpgm8

Program Phrase high-voltage time

t_hversscrErase Flash Sector high-voltage time

t_hversblk256kErase Flash Block high-voltage time for 256 KB

t_hversblk512kErase Flash Block high-voltage time for 512 KB

—

13

113

ms

1

—

208

416

1808

3616

—

1. Maximum time based on expectations at cycling end-of-life.

3.4.1.2 Flash timing specifications — commands

Table 23. Flash command timing specifications

Symbol Description

Read 1s Block execution time

Min.

Typ.

Max.

Unit

Notes

t_rd1blk256k

t_rd1blk512k

• 256 KB data flash

—

1.0

1.8

ms

• 512 KB program flash

t_rd1sec4kRead 1s Section execution time (4 KB flash)

—

90

100

95

μs

1

t_pgmchk

t_rdrsrc

Program Check execution time

Read Resource execution time

Program Phrase execution time

Erase Flash Block execution time

• 256 KB data flash

40

t_pgm8

150

2

t_ersblk256k

t_ersblk512k

—

220

435

1850

3700

ms

• 512 KB program flash

t_ersscr

Erase Flash Sector execution time

—

15

5

115

—

ms

2

t_pgmsec1kProgram Section execution time (1 KB flash)

Read 1s All Blocks execution time

t_rd1allx

t_rd1alln

• FlexNVM devices

—

5.9

6.7

ms

• Program flash only devices

t_rdonce

Read Once execution time

—

90

30

—

μs

1

2

t_pgmonceProgram Once execution time

t_ersallErase All Blocks execution time

1750

14,800

ms

Table continues on the next page...

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Table 23. Flash command timing specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

t_vfykey

Verify Backdoor Access Key execution time

—

30

μs

1

Swap Control execution time

• control code 0x01

• control code 0x02

• control code 0x04

• control code 0x08

• control code 0x10

t_swapx01

t_swapx02

t_swapx04

t_swapx08

t_swapx10

—

200

90

—

μs

150

30

90

150

Program Partition for EEPROM execution time

• 32 KB EEPROM backup

t_pgmpart32k

t_pgmpart256k

—

70

78

—

ms

• 256 KB EEPROM backup

Set FlexRAM Function execution time:

• Control Code 0xFF

t_setramff

t_setram32k

t_setram64k

t_setram128k

t_setram256k

—

70

0.8

1.3

2.4

4.5

—

μs

ms

• 32 KB EEPROM backup

• 64 KB EEPROM backup

• 128 KB EEPROM backup

• 256 KB EEPROM backup

1.2

1.9

3.1

5.5

Byte-write to FlexRAM execution time:

• 32 KB EEPROM backup

t_eewr8b32k

t_eewr8b64k

t_eewr8b128k

t_eewr8b256k

—

385

475

1700

2000

2350

3250

μs

• 64 KB EEPROM backup

• 128 KB EEPROM backup

• 256 KB EEPROM backup

650

1000

16-bit write to FlexRAM execution time:

• 32 KB EEPROM backup

t_eewr16b32k

t_eewr16b64k

t_eewr16b128k

t_eewr16b256k

—

385

475

1700

2000

2350

3250

μs

• 64 KB EEPROM backup

• 128 KB EEPROM backup

• 256 KB EEPROM backup

650

1000

t_eewr32bers32-bit write to erased FlexRAM location

execution time

—

360

1500

μs

32-bit write to FlexRAM execution time:

t_eewr32b32k

t_eewr32b64k

t_eewr32b128k

t_eewr32b256k

• 32 KB EEPROM backup

• 64 KB EEPROM backup

• 128 KB EEPROM backup

• 256 KB EEPROM backup

—

630

810

2000

2250

2650

3500

μs

1200

1900

1. Assumes 25MHz or greater flash clock frequency.

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

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3.4.1.3 Flash high voltage current behaviors

Table 24. Flash high voltage current behaviors

Symbol

Description

Min.

Typ.

Max.

Unit

I_{DD_PGM}

Average current adder during high voltage flash

programming operation

—

3.5

7.5

mA

I_{DD_ERS}

Average current adder during high voltage flash

erase operation

—

1.5

4.0

mA

3.4.1.4 Reliability specifications

Table 25. NVM reliability specifications

Symbol Description

Min.

Typ.¹

Max.

Unit

Notes

Program Flash

t_nvmretp10kData retention after up to 10 K cycles

t_nvmretp1kData retention after up to 1 K cycles

n_nvmcycpCycling endurance

5

50

—

years

cycles

20

100

50 K

10 K

2

Data Flash

t_nvmretd10kData retention after up to 10 K cycles

t_nvmretd1kData retention after up to 1 K cycles

n_nvmcycdCycling endurance

5

50

—

years

cycles

20

100

50 K

10 K

FlexRAM as EEPROM

t_nvmretee100Data retention up to 100% of write endurance

t_nvmretee10Data retention up to 10% of write endurance

n_nvmcyceeCycling endurance for EEPROM backup

Write endurance

5

50

—

years

cycles

20

100

50 K

20 K

2

3

n_nvmwree16

n_nvmwree128

n_nvmwree512

n_nvmwree2k

n_nvmwree8k

• EEPROM backup to FlexRAM ratio = 16

• EEPROM backup to FlexRAM ratio = 128

• EEPROM backup to FlexRAM ratio = 512

• EEPROM backup to FlexRAM ratio = 2,048

• EEPROM backup to FlexRAM ratio = 8,192

140 K

1.26 M

5 M

400 K

3.2 M

12.8 M

50 M

—

writes

20 M

80 M

200 M

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a

constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in

Engineering Bulletin EB619.

2. Cycling endurance represents number of program/erase cycles at -40°C ≤ T_j≤ 125°C.

3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the

cycling endurance of the FlexNVM and the allocated EEPROM backup per subsystem. Minimum and typical values

assume all 16-bit or 32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance.

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3.4.1.5 Write endurance to FlexRAM for EEPROM

When the FlexNVM partition code is not set to full data flash, the EEPROM data set

size can be set to any of several non-zero values.

The bytes not assigned to data flash via the FlexNVM partition code are used by the

FTFE to obtain an effective endurance increase for the EEPROM data. The built-in

EEPROM record management system raises the number of program/erase cycles that

can be attained prior to device wear-out by cycling the EEPROM data through a larger

EEPROM NVM storage space.

While different partitions of the FlexNVM are available, the intention is that a single

choice for the FlexNVM partition code and EEPROM data set size is used throughout

the entire lifetime of a given application. The EEPROM endurance equation and graph

shown below assume that only one configuration is ever used.

EEPROM – 2 × EEESPLIT × EEESIZE

Writes_subsystem =

× Write_efficiency × n_nvmcycee

EEESPLIT × EEESIZE

where

• Writes_subsystem — minimum number of writes to each FlexRAM location for

subsystem (each subsystem can have different endurance)

• EEPROM — allocated FlexNVM for each EEPROM subsystem based on

DEPART; entered with the Program Partition command

• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program

Partition command

• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program

Partition command

• Write_efficiency —

• 0.25 for 8-bit writes to FlexRAM

• 0.50 for 16-bit or 32-bit writes to FlexRAM

• n_nvmcycee— EEPROM-backup cycling endurance

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16/32-bit

8-bit

Ratio of EEPROM Backup to FlexRAM

Figure 11. EEPROM backup writes to FlexRAM

3.4.2 EzPort switching specifications

Table 26. EzPort full voltage range switching specifications

Num

Description

Min.

1.71

—

Max.

3.6

Unit

V

Operating voltage

EP1

EZP_CK frequency of operation (all commands except

READ)

f_SYS/2

MHz

EP1a

EP2

EP3

EP4

EP5

EP6

EP7

EP8

EP9

EZP_CK frequency of operation (READ command)

EZP_CS negation to next EZP_CS assertion

EZP_CS input valid to EZP_CK high (setup)

EZP_CK high to EZP_CS input invalid (hold)

EZP_D input valid to EZP_CK high (setup)

EZP_CK high to EZP_D input invalid (hold)

EZP_CK low to EZP_Q output valid

—

f_SYS/8

—

MHz

ns

2 x t_{EZP_CK}

5

—

ns

—

ns

2

—

ns

5

—

ns

—

0

14

—

ns

EZP_CK low to EZP_Q output invalid (hold)

EZP_CS negation to EZP_Q tri-state

ns

—

12

ns

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EZP_CK

EP2

EP3

EP4

EZP_CS

EP9

EP8

EP7

EZP_Q (output)

EZP_D (input)

EP5

EP6

Figure 12. EzPort Timing Diagram

3.4.3 Flexbus switching specifications

All processor bus timings are synchronous; input setup/hold and output delay are

given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK

frequency may be the same as the internal system bus frequency or an integer divider

of that frequency.

The following timing numbers indicate when data is latched or driven onto the

external bus, relative to the Flexbus output clock (FB_CLK). All other timing

relationships can be derived from these values.

Table 27. Flexbus limited voltage range switching specifications

Num

Description

Min.

2.7

Max.

3.6

Unit

V

Notes

Operating voltage

Frequency of operation

Clock period

—

FB_CLK

—

MHz

ns

FB1

FB2

FB3

FB4

FB5

1/FB_CLK

—

Address, data, and control output valid

Address, data, and control output hold

Data and FB_TA input setup

Data and FB_TA input hold

11.8

—

ns

1.0

ns

1

2

11.9

0.0

—

ns

—

ns

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],

FB_ALE, and FB_TS.

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2. Specification is valid for all FB_AD[31:0] and FB_TA.

Table 28. Flexbus full voltage range switching specifications

Num

Description

Min.

1.71

—

Max.

3.6

Unit

V

Notes

Operating voltage

Frequency of operation

Clock period

FB_CLK

—

MHz

ns

FB1

FB2

FB3

FB4

FB5

1/FB_CLK

—

Address, data, and control output valid

Address, data, and control output hold

Data and FB_TA input setup

Data and FB_TA input hold

12.6

—

ns

1.0

ns

1

2

12.5

0

—

ns

—

ns

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,

and FB_TS.

2. Specification is valid for all FB_AD[31:0] and FB_TA.

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Read Timing Parameters

S0

S1

S2

S3

S0

FB1

FB_CLK

FB_A[Y]

FB_D[X]

FB_RW

FB5

FB3

Address

FB4

FB2

Address

Data

FB_TS

FB_ALE

FB_CSn

FB_OEn

FB_BEn

FB_TA

AA=1

AA=0

FB4

FB5

AA=1

AA=0

FB_TSIZ[1:0]

TSIZ

S1

S0

S2

S3

S0

Figure 13. FlexBus read timing diagram

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Write Timing Parameters

FB1

FB_CLK

FB2

FB3

FB_A[Y]

FB_D[X]

FB_RW

Address

Data

FB_TS

FB_ALE

FB_CSn

FB_OEn

FB_BEn

FB_TA

AA=1

AA=0

FB4

FB5

AA=1

AA=0

FB_TSIZ[1:0]

TSIZ

Figure 14. FlexBus write timing diagram

3.4.4 SDRAM controller specifications

Following figure shows SDRAM read cycle.

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Peripheral operating requirements and behaviors

0

1

2

3

4

5

6

7

8

9

10

11

12

13

D0

CLKOUT

D3

D1

Row

Column

A[23:0]

D4

SRAS

SCAS

D2

1

D4

DRAMW

D[31:16]

D5

D6

D4

SDRAM_CS[1:0]

BS[3:0]

NOP

ACTV

NOP

READ

PRE

1

DACR[CASL] = 2

Figure 15. SDRAM read timing diagram

Table 29. SDRAM Timing (Full voltage range)

NUM

Characteristic ¹

Symbol

1.71

MIn

Max

Unit

Operating voltage

3.6

V

Frequency of operation

—

CLKOUT

MHz

D0

D1

D2

D3

D4

D5

D6

D7³

D8³

Clock period

1/CLKOUT

t_CHDAV

t_CHDCV

t_CHDAI

—

-

ns

2

CLKOUT high to SDRAM address valid

CLKOUT high to SDRAM control valid

CLKOUT high to SDRAM address invalid

CLKOUT high to SDRAM control invalid

SDRAM data valid to CLKOUT high

CLKOUT high to SDRAM data invalid

CLKOUT high to SDRAM data valid

CLKOUT high to SDRAM data invalid

11.2

ns

11.1

1.0

12.0

1.0

-

t_CHDCI

-

t_DDVCH

t_CHDDI

t_CHDDVW

t_CHDDIW

-

12.0

-

1.0

1. All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.

2. CLKOUT is same as FB_CLK, maximum frequency can be 60 MHz

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3. D7 and D8 are for write cycles only.

Table 30. SDRAM Timing (Limited voltage range)

NUM

Characteristic ¹

Symbol

2.7

MIn

Max

Unit

Operating voltage

3.6

V

Frequency of operation

—

CLKOUT

MHz

D0

D1

D2

D3

D4

D5

D6

D7³

D8³

Clock period

1/CLKOUT

t_CHDAV

t_CHDCV

t_CHDAI

—

-

ns

2

CLKOUT high to SDRAM address valid

CLKOUT high to SDRAM control valid

CLKOUT high to SDRAM address invalid

CLKOUT high to SDRAM control invalid

SDRAM data valid to CLKOUT high

CLKOUT high to SDRAM data invalid

CLKOUT high to SDRAM data valid

CLKOUT high to SDRAM data invalid

11.1

ns

11.1

1.0

11.3

1.0

-

t_CHDCI

-

t_DDVCH

t_CHDDI

t_CHDDVW

t_CHDDIW

-

11.1

-

1.0

1. All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.

2. CLKOUT is same as FB_CLK, maximum frequency can be 60 MHz

3. D7 and D8 are for write cycles only.

Following figure shows an SDRAM write cycle.

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0

1

2

3

4

5

6

7

8

9

10

11

12

D0

CLKOUT

D3

D1

Row

Column

A[23:0]

SRAS

D2

1

SCAS

D4

DRAMW

D[31:16]

D7

D8

D4

SDRAM_CS[1:0]

BS[3:0]

D4

D2

D4

ACTV

NOP

WRITE

NOP

PALL

1

DACR[CASL] = 2

Figure 16. SDRAM write timing diagram

3.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

3.6 Analog

3.6.1 ADC electrical specifications

The 16-bit accuracy specifications listed in Table 31 and Table 32 are achievable on

the differential pins ADCx_DP0, ADCx_DM0.

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All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy

specifications.

3.6.1.1 16-bit ADC operating conditions

Table 31. 16-bit ADC operating conditions

Symbol Description

Conditions

Min.

1.71

-100

1.13

Typ.¹

Max.

3.6

Unit

V

Notes

V_DDA

ΔV_DDA

ΔV_SSA

V_REFH

Supply voltage

Absolute

—

2

Delta to V_DD(V_DD– V_DDA

)

0

+100

V_DDA

mV

V

Ground voltage Delta to V_SS(V_SS– V_SSA

)

0

2

ADC reference

voltage high

V_DDA

V_REFL

V_ADIN

ADC reference

voltage low

V_SSA

V

Input voltage

• 16-bit differential mode

• All other modes

• 16-bit mode

VREFL

—

31/32 *

VREFH

—

VREFH

C_ADIN

Input

capacitance

—

8

4

10

5

pF

• 8-bit / 10-bit / 12-bit

modes

R_ADIN

R_AS

Input series

resistance

—

2

5

kΩ

—

3

Analog source

resistance

(external)

13-bit / 12-bit modes

f_ADCK< 4 MHz

—

f_ADCK

C_rate

ADC conversion ≤ 13-bit mode

clock frequency

1.0

2.0

—

24

MHz

4

5

ADC conversion 16-bit mode

clock frequency

12.0

ADC conversion ≤ 13-bit modes

rate

20.000

—

1200

kS/s

No ADC hardware averaging

Continuous conversions

enabled, subsequent

conversion time

C_rate

ADC conversion 16-bit mode

5

37.037

—

461.467

kS/s

rate

No ADC hardware averaging

Continuous conversions

enabled, subsequent

conversion time

1. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

2. DC potential difference.

3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The

R_AS/C_AStime constant should be kept to < 1 ns.

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Peripheral operating requirements and behaviors

4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.

5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

SIMPLIFIED

INPUT PIN EQUIVALENT

ZADIN

CIRCUIT

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

Pad

leakage

ZAS

ADC SAR

ENGINE

RAS

RADIN

VADIN

CAS

VAS

RADIN

INPUT PIN

CADIN

Figure 17. ADC input impedance equivalency diagram

3.6.1.2 16-bit ADC electrical characteristics

Table 32. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA

)

Symbol Description

Conditions¹

Min.

0.215

1.2

Typ.²

Max.

1.7

3.9

6.1

7.3

9.5

Unit

Notes

I_{DDA_ADC}Supply current

—

mA

3

ADC asynchronous

clock source

• ADLPC = 1, ADHSC = 0

• ADLPC = 1, ADHSC = 1

• ADLPC = 0, ADHSC = 0

• ADLPC = 0, ADHSC = 1

2.4

4.0

5.2

6.2

MHz

t_ADACK= 1/

f_ADACK

2.4

f_ADACK

3.0

4.4

Sample Time

See Reference Manual chapter for sample times

TUE

DNL

Total unadjusted

error

• 12-bit modes

• <12-bit modes

—

4

6.8

2.1

LSB⁴

5

1.4

Differential non-

linearity

• 12-bit modes

• <12-bit modes

—

0.7

0.2

–1.1 to

+1.9

–0.3 to

0.5

Table continues on the next page...

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Table 32. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA) (continued)

Symbol Description

Conditions¹

Min.

Typ.²

Max.

Unit

Notes

INL

Integral non-linearity

• 12-bit modes

—

1.0

–2.7 to

+1.9

LSB⁴

5

• <12-bit modes

—

0.5

–0.7 to

+0.5

5

E_FS

E_Q

Full-scale error

• 12-bit modes

• <12-bit modes

• 16-bit modes

• ≤13-bit modes

—

–4

–1.4

–1 to 0

—

–5.4

–1.8

—

LSB⁴

V_ADIN= V_DDA

Quantization error

0.5

ENOB Effective number of 16-bit differential mode

6

bits

12.8

11.9

14.5

13.8

—

bits

• Avg = 32

• Avg = 4

16-bit single-ended mode

• Avg = 32

12.2

11.4

13.9

13.1

—

bits

dB

• Avg = 4

Signal-to-noise plus See ENOB

SINAD

6.02 × ENOB + 1.76

distortion

THD

Total harmonic

distortion

16-bit differential mode

• Avg = 32

7

dB

—

-94

-85

—

16-bit single-ended mode

• Avg = 32

—

SFDR Spurious free

dynamic range

16-bit differential mode

• Avg = 32

—

dB

82

78

95

90

16-bit single-ended mode

• Avg = 32

E_IL

Input leakage error

I_In× R_AS

mV

I_In= leakage

current

(refer to the

MCU's

voltage and

current

operating

ratings)

Temp sensor slope Across the full temperature

range of the device

1.55

706

1.62

716

1.69

726

mV/°C

mV

8

V_TEMP25Temp sensor

voltage

25 °C

8

1. All accuracy numbers assume the ADC is calibrated with V_REFH= V_DDA

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Peripheral operating requirements and behaviors

2. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 2.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with

1 MHz ADC conversion clock speed.

4. 1 LSB = (V_REFH- V_REFL)/2^N

5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)

6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.

7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.

8. ADC conversion clock < 3 MHz

Typical ADC 16-bit Differential ENOB vs ADC Clock

100Hz, 90% FS Sine Input

15.00

14.70

14.40

14.10

13.80

13.50

13.20

12.90

12.60

Hardware Averaging Disabled

Averaging of 4 samples

12.30

12.00

Averaging of 8 samples

Averaging of 32 samples

1

2

3

4

5

6

7

8

9

10

11

12

ADC Clock Frequency (MHz)

Figure 18. Typical ENOB vs. ADC_CLK for 16-bit differential mode

Typical ADC 16-bit Single-Ended ENOB vs ADC Clock

100Hz, 90% FS Sine Input

14.00

13.75

13.50

13.25

13.00

12.75

12.50

12.25

12.00

11.75

11.50

11.25

Averaging of 4 samples

Averaging of 32 samples

11.00

1

2

3

4

5

6

7

8

9

10

11

12

ADC Clock Frequency (MHz)

Figure 19. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

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3.6.2 CMP and 6-bit DAC electrical specifications

Table 33. Comparator and 6-bit DAC electrical specifications

Symbol

V_DD

Description

Min.

1.71

—

Typ.

—

Max.

3.6

Unit

V

Supply voltage

I_DDHS

I_DDLS

V_AIN

Supply current, High-speed mode (EN=1, PMODE=1)

Supply current, low-speed mode (EN=1, PMODE=0)

Analog input voltage

—

200

20

μA

V

—

V_SS– 0.3

—

V_DD

20

V_AIO

Analog input offset voltage

Analog comparator hysteresis¹

• CR0[HYSTCTR] = 00

—

mV

V_H

—

5

—

mV

10

20

30

• CR0[HYSTCTR] = 01

• CR0[HYSTCTR] = 10

• CR0[HYSTCTR] = 11

V_CMPOh

V_CMPOl

t_DHS

Output high

V_DD– 0.5

—

50

250

—

7

—

0.5

200

600

40

V

Output low

Propagation delay, high-speed mode (EN=1, PMODE=1)

Propagation delay, low-speed mode (EN=1, PMODE=0)

Analog comparator initialization delay²

6-bit DAC current adder (enabled)

6-bit DAC integral non-linearity

20

ns

t_DLS

80

ns

—

μs

I_DAC6b

INL

—

μA

LSB³

LSB

–0.5

–0.3

—

0.5

0.3

DNL

6-bit DAC differential non-linearity

1. Typical hysteresis is measured with input voltage range limited to 0.6 to V_DD–0.6 V.

2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.

3. 1 LSB = V_reference/64

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Peripheral operating requirements and behaviors

0.08

0.07

0.06

0.05

0.04

0.03

HYSTCTR

Setting

00

01

10

11

0.02

0.01

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 20. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

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Peripheral operating requirements and behaviors

0.18

0.16

0.14

0.12

HYSTCTR

Setting

0.1

00

01

10

11

0.08

0.06

0.04

0.02

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 21. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

3.6.3 12-bit DAC electrical characteristics

3.6.3.1 12-bit DAC operating requirements

Table 34. 12-bit DAC operating requirements

Symbol

V_DDA

V_DACR

C_L

Desciption

Min.

Max.

3.6

100

1

Unit

V

Notes

Supply voltage

Reference voltage

Output load capacitance

Output load current

1.13

—

V

1

2

pF

mA

I_L

—

1. The DAC reference can be selected to be V_DDAor V_REFH

.

2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

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3.6.3.2 12-bit DAC operating behaviors

Table 35. 12-bit DAC operating behaviors

Symbol Description

Min.

Typ.

Max.

150

Unit

Notes

I_{DDA_DACL}Supply current — low-power mode

—

μA

P

I_{DDA_DACH}Supply current — high-speed mode

—

100

15

700

200

30

μA

μs

P

t_DACLPFull-scale settling time (0x080 to 0xF7F) —

low-power mode

1

t_DACHPFull-scale settling time (0x080 to 0xF7F) —

high-power mode

t_CCDACLPCode-to-code settling time (0xBF8 to

0xC08) — low-power mode and high-

speed mode

0.7

1

V_dacoutlDAC output voltage range low — high-

speed mode, no load, DAC set to 0x000

—

100

mV

V_dacouthDAC output voltage range high — high-

speed mode, no load, DAC set to 0xFFF

V_DACR

−100

V_DACR

INL

DNL

Integral non-linearity error — high speed

mode

—

8

1

LSB

2

3

4

Differential non-linearity error — V_DACR> 2

V

Differential non-linearity error — V_DACR

VREF_OUT

=

V_OFFSETOffset error

E_GGain error

PSRR Power supply rejection ratio, V_DDA≥ 2.4 V

—

60

—

0.4

0.1

0.8

0.6

90

%FSR

dB

5

—

T_CO

T_GE

A_C

Temperature coefficient offset voltage

Temperature coefficient gain error

Offset aging coefficient

3.7

—

μV/C

%FSR/C

μV/yr

Ω

6

0.000421

—

100

250

Rop

SR

Output resistance (load = 3 kΩ)

Slew rate -80h→ F7Fh→ 80h

—

V/μs

• High power (SP_HP

• Low power (SP_LP

)

1.2

1.7

—

)

0.05

0.12

CT

Channel to channel cross talk

3dB bandwidth

—

-80

dB

BW

kHz

• High power (SP_HP

• Low power (SP_LP

)

550

40

—

)

1. Settling within 1 LSB

2. The INL is measured for 0 + 100 mV to V_DACR−100 mV

3. The DNL is measured for 0 + 100 mV to V_DACR−100 mV

4. The DNL is measured for 0 + 100 mV to V_DACR−100 mV with V_DDA> 2.4 V

5. Calculated by a best fit curve from V_SS+ 100 mV to V_DACR− 100 mV

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6. V_DDA= 3.0 V, reference select set for V_DDA(DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set

to 0x800, temperature range is across the full range of the device

8

6

4

2

0

-2

-4

-6

-8

0

500

1000

1500

2000

2500

3000

3500

4000

Digital Code

Figure 22. Typical INL error vs. digital code

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Peripheral operating requirements and behaviors

1.499

1.4985

1.498

1.4975

1.497

1.4965

1.496

55

85

25

105

125

-40

Temperature °C

Figure 23. Offset at half scale vs. temperature

3.6.4 Voltage reference electrical specifications

Table 36. VREF full-range operating requirements

Symbol

V_DDA

T_A

Description

Supply voltage

Temperature

Min.

Max.

Unit

Notes

3.6

V

Operating temperature

range of the device

°C

C_L

Output load capacitance

100

nF

1, 2

1. C_Lmust be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external

reference.

2. The load capacitance should not exceed +/-25% of the nominal specified C_Lvalue over the operating temperature

range of the device.

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Table 37. VREF full-range operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_out

Voltage reference output with factory trim at

1.190

1.195

1.200

V

1

nominal V_DDAand temperature=25C

Voltage reference output — factory trim

Voltage reference output — user trim

Voltage reference trim step

V_out

1.1584

1.193

—

1.2376

1.197

—

V

1

V_step

V_tdrift

0.5

—

mV

Temperature drift (Vmax -Vmin across the full

temperature range)

—

80

Ac

I_bg

Aging coefficient

—

400

80

uV/yr

µA

—

1

Bandgap only current

ΔV_LOADLoad regulation

• current = 1.0 mA

µV

1, 2

—

200

—

T_stup

Buffer startup time

—

100

35

µs

T_{chop_osc_st}Internal bandgap start-up delay with chop

ms

—

1

oscillator enabled

up

V_vdrift

Voltage drift (Vmax -Vmin across the full voltage

range)

—

2

—

mV

1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.

2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 38. VREF limited-range operating requirements

Symbol

Description

Min.

Max.

Unit

Notes

T_A

Temperature

0

50

°C

Table 39. VREF limited-range operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

V_out

Voltage reference output with factory trim

1.173

1.225

V

3.7 Timers

See General switching specifications.

3.8 Communication interfaces

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Peripheral operating requirements and behaviors

3.8.1 Ethernet switching specifications

The following timing specs are defined at the chip I/O pin and must be translated

appropriately to arrive at timing specs/constraints for the physical interface.

3.8.1.1 MII signal switching specifications

The following timing specs meet the requirements for MII style interfaces for a range

of transceiver devices.

Table 40. MII signal switching specifications (limited voltage range)

Symbol

—

Description

Min.

2.7

Max.

3.6

Unit

V

Operating Voltage

RXCLK frequency

RXCLK pulse width high

—

25

MHz

RXCLK

period

RXCLK

period

ns

MII1

35%

65%

MII2

RXCLK pulse width low

35%

65%

MII3

MII4

—

RXD[3:0], RXDV, RXER to RXCLK setup

RXCLK to RXD[3:0], RXDV, RXER hold

TXCLK frequency

5

—

ns

—

25

MHz

TXCLK

period

TXCLK

period

ns

MII5

TXCLK pulse width high

35%

65%

MII6

TXCLK pulse width low

35%

65%

MII7

MII8

TXCLK to TXD[3:0], TXEN, TXER invalid

TXCLK to TXD[3:0], TXEN, TXER valid

2

—

25

ns

Table 41. MII signal switching specifications (full voltage range)

Symbol

—

Description

Min.

1.7

Max.

3.6

Unit

V

Operating Voltage

RXCLK frequency

RXCLK pulse width high

—

25

MHz

MII1

35%

65%

RXCLK

period

RXCLK

period

ns

MII2

MII3

RXCLK pulse width low

35%

5

65%

—

RXD[3:0], RXDV, RXER to RXCLK setup

Table continues on the next page...

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Table 41. MII signal switching specifications (full voltage range)

(continued)

Symbol

MII4

—

Description

Min.

5

Max.

—

Unit

ns

RXCLK to RXD[3:0], RXDV, RXER hold

TXCLK frequency

—

25

MHz

TXCLK

period

TXCLK

period

ns

MII5

TXCLK pulse width high

35%

65%

MII6

TXCLK pulse width low

35%

65%

MII7

MII8

TXCLK to TXD[3:0], TXEN, TXER invalid

TXCLK to TXD[3:0], TXEN, TXER valid

2

—

25

ns

MII6

MII5

MII7

TXCLK (input)

MII8

Valid data

TXD[n:0]

TXEN

Valid data

TXER

Figure 24. RMII/MII transmit signal timing diagram

MII2

MII1

RXCLK (input)

RXD[n:0]

RXDV

MII3

MII4

Valid data

RXER

Figure 25. RMII/MII receive signal timing diagram

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3.8.1.2 RMII signal switching specifications

The following timing specs meet the requirements for RMII style interfaces for a

range of transceiver devices.

Table 42. RMII signal switching specifications (limited voltage range)

Num

—

Description

Min.

2.7

Max.

3.6

Unit

Operating Voltage

—

EXTAL frequency (RMII input clock RMII_CLK)

RMII_CLK pulse width high

—

50

MHz

RMII1

35%

65%

RMII_CLK

period

RMII2

RMII_CLK pulse width low

35%

65%

RMII_CLK

period

RMII3

RMII4

RMII7

RMII8

RXD[1:0], CRS_DV, RXER to RMII_CLK setup

RMII_CLK to RXD[1:0], CRS_DV, RXER hold

RMII_CLK to TXD[1:0], TXEN invalid

4

2

—

ns

4

—

RMII_CLK to TXD[1:0], TXEN valid

—

15.4

Table 43. RMII signal switching specifications (full voltage range)

Num

—

Description

Min.

1.7

Max.

3.6

Unit

Operating Voltage

—

EXTAL frequency (RMII input clock RMII_CLK)

RMII_CLK pulse width high

—

50

MHz

RMII1

35%

65%

RMII_CLK

period

RMII2

RMII_CLK pulse width low

35%

65%

RMII_CLK

period

RMII3

RMII4

RMII7

RMII8

RXD[1:0], CRS_DV, RXER to RMII_CLK setup

RMII_CLK to RXD[1:0], CRS_DV, RXER hold

RMII_CLK to TXD[1:0], TXEN invalid

4

2

—

ns

4

—

RMII_CLK to TXD[1:0], TXEN valid

—

17.5

3.8.1.3 MDIO serial management timing specifications

Table 44. MDIO serial management channel signal timing

Num

E10

E11

E12

E13

E14

E15

Characteristic

MDC cycle time

Symbol

Min

400

40

—

Max

—

Unit

ns

t_MDC

MDC pulse width

60

% t_MDC

ns

MDC to MDIO output valid

MDC to MDIO output invalid

MDIO input to MDC setup

MDIO input to MDC hold

375

—

25

10

0

ns

—

ns

—

ns

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E10

E11

MDC (Output)

MDIO (Output)

MDIO (Input)

E11

E12

E13

E15

Valid Data

E14

Valid Data

Figure 26. MDIO serial management channel timing diagram

3.8.2 USB Voltage Regulator Electrical Specifications

Table 45. USB VREG electrical specifications

Symbol

Description

Min.

Typ.¹

Max.

Unit

Notes

VREG_IN0 Regulator selectable input supply voltages

VREG_IN1

2.7

—

5.5

V

2

I_DDon

Quiescent current — Run mode, load current

equal zero, input supply (VREG_IN*) > 3.6 V

μA

—

VREG_IN0

VREG_IN1

157

2

I_DDstby

Quiescent current — Standby mode, load

current equal zero

—

VREG_IN0

VREG_IN1

I_DDoff

2

Quiescent current — Shutdown mode

VREG_IN0

VREG_IN1

• VREG_IN*= 5.0 V and temperature=25 °C

—

680

920

—

nA

I_LOADrun

I_LOADstby

Maximum load current — Run mode

—

150

1

mA

mV

3

4

Maximum load current — Standby mode

—

V_DROPOUTRegulator drop-out voltage — Run mode at

maximum load current with inrush current limit

disabled

300

—

VREG_OUT Regulator programmable output target voltage

— Selected input supply > programmed output

target voltage + V_DROPOUT

3

3.3

2.8

3.6

V

2.1

• Run mode

• Standby mode

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Table 45. USB VREG electrical specifications

(continued)

Symbol

C_OUT

Description

Min.

1.76

1

Typ.¹

Max.

8.16

100

Unit

μF

Notes

External output capacitor

2.2

ESR

External output capacitor equivalent series

resistance

—

mΩ

I_LIM

Short circuit current

Inrush current limit

—

350

—

mA

5

I_INRUSH

40

100

6, 7, 8,

9, 10

1. Typical values assume the selected input supply is 5.0 V, Temp = 25 °C unless otherwise stated.

2. Operation range is 2.7 V to 5.5 V; tolerance voltage is up to 6 V.

3. 150mA is inclusive of the run mode current of the on-chip USB modules. Available load outside of the chip depends on

USB operation and device power dissipation limits.

4. The target voltage for the regulator is programmable, accounting for the range of the max and min values

5. Current limit disabled.

6. Current limit should be disabled after the powers have stabilized to allow full functionality of the regulator.

7. Limited Characterization

8. I_INRUSHwith VREGINx=4.0 V to 5.5 V

9. The minimum value of I_INRUSHis stated for operation when only one of VREG_IN0 / VREG_IN1 is powered, or when

VREG_IN0 and VREG_IN1 both have the same voltage level. When VREG_IN0 and VREG_IN1 are operated at

different voltage levels with the selected VREG_IN lower than the non-selected VREG_IN, the minumum value of

I_INRUSHmay decrease to a lower value.

10. Total current load on startup should be less than I_INRUSHmin over full input voltage range of the regulator.

3.8.3 USB Full Speed Transceiver and High Speed PHY

specifications

This section describes the USB0 port Full Speed/Low Speed transceiver and USB1

port USB-PHY High Speed Phy parameters. The high speed phy is capable of full and

low speed signalling as well.

The USB0 (FS/LS Transceiver) and USB1 ((USB HS/FS/LS) meet the electrical

compliance requirements defined in the Universal Serial Bus Revision 2.0

Specification with the amendments below.

• USB ENGINEERING CHANGE NOTICE

• Title: 5V Short Circuit Withstand Requirement Change

• Applies to: Universal Serial Bus Specification, Revision 2.0

• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000

• USB ENGINEERING CHANGE NOTICE

• Title: Pull-up/Pull-down resistors

• Applies to: Universal Serial Bus Specification, Revision 2.0

• USB ENGINEERING CHANGE NOTICE

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• Title: Suspend Current Limit Changes

• Applies to: Universal Serial Bus Specification, Revision 2.0

• On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification

• Revision 2.0 version 1.1a July 27, 2012

• Battery Charging Specification (available from USB-IF)

• Revision 1.2 (including errata and ECNs through March 15, 2012), March 15,

2012

USB1_VBUS pin is a detector function which is 5v tolerant and complies with the

above specifications without needing any external voltage division components.

3.8.4 USB DCD electrical specifications

Table 46. USB DCD electrical specifications

Symbol

V_{DP_SRC}

Description

Min.

Typ.

Max.

Unit

,

USB_DP and USB_DM source voltages (up to 250

0.5

—

0.7

V

V_{DM_SRC}μA)

V_LGC

I_{DP_SRC}

I_{DM_SINK}

Threshold voltage for logic high

0.8

7

—

10

2.0

13

V

USB_DP source current

μA

,

USB_DM and USB_DP sink currents

50

100

150

I_{DP_SINK}

R_{DM_DWN}D- pulldown resistance for data pin contact detect

V_{DAT_REF}Data detect voltage

14.25

0.25

—

24.8

0.4

kΩ

V

0.33

3.8.5 CAN switching specifications

See General switching specifications.

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3.8.6 DSPI switching specifications (limited voltage range)

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with

master and slave operations. Many of the transfer attributes are programmable. The

tables below provide DSPI timing characteristics for classic SPI timing modes. Refer

to the DSPI chapter of the Reference Manual for information on the modified transfer

formats used for communicating with slower peripheral devices.

Table 47. Master mode DSPI timing (limited voltage range)

Num

Description

Min.

2.7

Max.

3.6

30

Unit

V

Notes

Operating voltage

Frequency of operation

—

MHz

ns

DS1

DS2

DS3

DSPI_SCK output cycle time

DSPI_SCK output high/low time

DSPI_PCSn valid to DSPI_SCK delay

2 x t_BUS

—

(t_SCK/2) − 2 (t_SCK/2) + 2

ns

(t_BUSx 2) −

2

—

ns

1

2

DS4

DSPI_SCK to DSPI_PCSn invalid delay

(t_BUSx 2) −

2

—

ns

DS5

DS6

DS7

DS8

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

—

1.0

15.8

0

15.0

—

ns

—

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].

2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

DSPI_PCSn

DS1

DS3

DS2

DS4

DSPI_SCK

(CPOL=0)

DS8

DS7

Data

Last data

First data

DSPI_SIN

DS5

DS6

First data

Data

Last data

DSPI_SOUT

Figure 27. DSPI classic SPI timing — master mode

Table 48. Slave mode DSPI timing (limited voltage range)

Num

Description

Min.

Max.

Unit

V

Operating voltage

2.7

3.6

Frequency of operation

15 ¹

MHz

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Table 48. Slave mode DSPI timing (limited voltage range) (continued)

Num

DS9

Description

DSPI_SCK input cycle time

Min.

Max.

Unit

ns

4 x t_BUS

—

DS10

DS11

DS12

DS13

DS14

DS15

DS16

DSPI_SCK input high/low time

(t_SCK/2) − 2

(t_SCK/2) + 2

DSPI_SCK to DSPI_SOUT valid

—

0

23.0

—

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

DSPI_SS active to DSPI_SOUT driven

DSPI_SS inactive to DSPI_SOUT not driven

2.7

7.0

—

13

1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with

continuous CS and SCK, there is a constraint that SPI clock should not be greater than 1/6 of bus clock, for example,

when bus clock is 60MHz, SPI clock should not be greater than 10MHz.

DSPI_SS

DS10

DS9

DSPI_SCK

(CPOL=0)

DS15

DS12

DS16

DS11

First data

DS14

Last data

DSPI_SOUT

Data

DS13

First data

Last data

DSPI_SIN

Figure 28. DSPI classic SPI timing — slave mode

3.8.7 DSPI switching specifications (full voltage range)

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with

master and slave operations. Many of the transfer attributes are programmable. The

tables below provides DSPI timing characteristics for classic SPI timing modes. Refer

to the DSPI chapter of the Reference Manual for information on the modified transfer

formats used for communicating with slower peripheral devices.

Table 49. Master mode DSPI timing (full voltage range)

Num

Description

Min.

1.71

—

Max.

3.6

Unit

V

Notes

Operating voltage

Frequency of operation

1

15

MHz

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Table 49. Master mode DSPI timing (full voltage range) (continued)

Num

DS1

DS2

DS3

Description

DSPI_SCK output cycle time

Min.

Max.

Unit

ns

Notes

4 x t_BUS

—

DSPI_SCK output high/low time

(t_SCK/2) - 4 (t_SCK/2)+ 4

ns

DSPI_PCSn valid to DSPI_SCK delay

(t_BUSx 2) −

4

—

ns

2

3

DS4

DSPI_SCK to DSPI_PCSn invalid delay

(t_BUSx 2) −

4

—

ns

DS5

DS6

DS7

DS8

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

—

1.0

15.8

0

15

—

ns

1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].

3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

DSPI_PCSn

DS1

DS3

DS2

DS4

DSPI_SCK

(CPOL=0)

DS8

DS7

Data

Last data

First data

DSPI_SIN

DS5

DS6

First data

Data

Last data

DSPI_SOUT

Figure 29. DSPI classic SPI timing — master mode

Table 50. Slave mode DSPI timing (full voltage range)

Num

Description

Min.

Max.

3.6

Unit

V

Operating voltage

1.71

Frequency of operation

—

7.5

MHz

ns

DS9

DSPI_SCK input cycle time

8 x t_BUS

—

DS10

DS11

DS12

DS13

DS14

DS15

DS16

DSPI_SCK input high/low time

(t_SCK/2) - 4

(t_SCK/2)+ 4

23.1

—

ns

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

DSPI_SS active to DSPI_SOUT driven

DSPI_SS inactive to DSPI_SOUT not driven

—

0

ns

2.6

7.0

—

ns

—

ns

13.0

ns

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DSPI_SS

DS10

DS9

DSPI_SCK

DS15

DS12

DS16

DS11

(CPOL=0)

First data

Last data

DSPI_SOUT

Data

DS13

DS14

First data

Last data

DSPI_SIN

Figure 30. DSPI classic SPI timing — slave mode

3.8.8 Inter-Integrated Circuit Interface (I²C) timing

Table 51. I ²C timing

Characteristic

Symbol

Standard Mode

Minimum Maximum

100

Fast Mode

Unit

Minimum

Maximum

400

SCL Clock Frequency

f_SCL

0

kHz

µs

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated.

t_HD; STA

4

—

0.6

—

LOW period of the SCL clock

HIGH period of the SCL clock

t_LOW

t_HIGH

4.7

4

—

1.25

0.6

—

µs

Set-up time for a repeated START

condition

t_SU; STA

4.7

0.6

Data hold time for I²C bus devices

t_HD; DAT

t_SU; DAT

t_r

0¹

250⁴

—

3.45²

—

0³

100^{2, 5}

20 +0.1C_b

0.6

0.9¹

—

µs

ns

µs

Data set-up time

6

5

Rise time of SDA and SCL signals

Fall time of SDA and SCL signals

Set-up time for STOP condition

1000

300

—

300

—

t_f

—

t_SU; STO

t_BUF

4

Bus free time between STOP and

START condition

4.7

—

1.3

—

Pulse width of spikes that must be

suppressed by the input filter

t_SP

N/A

0

50

ns

1. The master mode I²C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves

acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL

lines.

2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.

3. Input signal Slew = 10 ns and Output Load = 50 pF

4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.

5. A Fast mode I²C bus device can be used in a Standard mode I2C bus system, but the requirement t_{SU; DAT}≥ 250 ns

must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such

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a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line t_rmax+ t_SU;

_DAT= 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification) before the SCL line is released.

6. C_b= total capacitance of the one bus line in pF.

Table 52. I ²C 1 Mbps timing

Characteristic

Symbol

f_SCL

Minimum

Maximum

Unit

MHz

µs

SCL Clock Frequency

0

1¹

Hold time (repeated) START condition. After this

period, the first clock pulse is generated.

t_HD; STA

0.26

—

LOW period of the SCL clock

HIGH period of the SCL clock

Set-up time for a repeated START condition

Data hold time for I₂C bus devices

Data set-up time

t_LOW

t_HIGH

0.5

0.26

0

—

µs

ns

µs

t_SU; STA

t_HD; DAT

t_SU; DAT

t_r

—

50

—

, 2

Rise time of SDA and SCL signals

Fall time of SDA and SCL signals

Set-up time for STOP condition

20 +0.1C_b

0.26

120

—

2

t_f

t_SU; STO

t_BUF

Bus free time between STOP and START

condition

0.5

—

Pulse width of spikes that must be suppressed by

the input filter

t_SP

0

50

ns

1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins

across the full voltage range.

2. C_b= total capacitance of the one bus line in pF.

SDA

t_{SU; DAT}

t_f

t_r

t_BUF

t_f

t_r

t_{HD; STA}

t_SP

t_LOW

SCL

t_{SU; STA}

t_{SU; STO}

HD; STA

S

SR

P

S

t_{HD; DAT}

t_HIGH

Figure 31. Timing definition for devices on the I²C bus

3.8.9 UART switching specifications

See General switching specifications.

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3.8.10 Low Power UART switching specifications

See General switching specifications.

3.8.11 SDHC specifications

The following timing specs are defined at the chip I/O pin and must be translated

appropriately to arrive at timing specs/constraints for the physical interface.

Table 53. SDHC full voltage range switching specifications

Num

Symbol

Description

Min.

Max.

Unit

Operating voltage

1.71

3.6

V

Card input clock

SD1

fpp

f_OD

t_WL

t_WH

t_TLH

t_THL

Clock frequency (low speed)

0

400

25\50

20\50

400

—

kHz

MHz

kHz

ns

Clock frequency (SD\SDIO full speed\high speed)

Clock frequency (MMC full speed\high speed)

Clock frequency (identification mode)

Clock low time

0

SD2

SD3

SD4

SD5

7

Clock high time

7

—

ns

Clock rise time

—

3

ns

Clock fall time

3

ns

SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)

SDHC output delay (output valid) -5 8.6 8.3

SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)

SD6

t_OD

ns

SD7

SD8

t_ISU

t_IH

SDHC input setup time

SDHC input hold time

5

0

—

ns

Table 54. SDHC limited voltage range switching specifications

Num

Symbol

Description

Min.

Max.

Unit

Operating voltage

2.7

3.6

V

Card input clock

SD1

fpp

f_OD

t_WL

t_WH

t_TLH

t_THL

Clock frequency (low speed)

0

400

25\50

20\50

400

—

kHz

MHz

kHz

ns

Clock frequency (SD\SDIO full speed\high speed)

Clock frequency (MMC full speed\high speed)

Clock frequency (identification mode)

Clock low time

0

SD2

SD3

SD4

SD5

7

Clock high time

7

—

ns

Clock rise time

—

3

ns

Clock fall time

3

ns

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Table 54. SDHC limited voltage range switching specifications (continued)

Num

Symbol

Description

SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)

SDHC output delay (output valid) -5 7.6 8.3

SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)

Min.

Max.

Unit

SD6

t_OD

ns

SD7

SD8

t_ISU

t_IH

SDHC input setup time

SDHC input hold time

5

0

—

ns

SD3

SD6

SD2

SD1

SDHC_CLK

Output SDHC_CMD

Output SDHC_DAT[3:0]

Input SDHC_CMD

SD7

SD8

Input SDHC_DAT[3:0]

Figure 32. SDHC timing

3.8.12 I²S switching specifications

This section provides the AC timings for the I²S in master (clocks driven) and slave

modes (clocks input). All timings are given for non-inverted serial clock polarity

(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] =

0, RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been

inverted, all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or

the frame sync (I2S_FS) shown in the figures below.

Table 55. I2S master mode timing (limited voltage range)

Num

Description

Min.

2.7

Max.

3.6

—

Unit

Operating voltage

V

S1

S2

S3

I2S_MCLK cycle time

I2S_MCLK pulse width high/low

I2S_BCLK cycle time

40

ns

MCLK period

ns

45%

80

55%

—

Table continues on the next page...

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Table 55. I2S master mode timing (limited voltage range) (continued)

Num

S4

Description

Min.

45%

—

Max.

55%

15

Unit

I2S_BCLK pulse width high/low

I2S_BCLK to I2S_FS output valid

I2S_BCLK to I2S_FS output invalid

I2S_BCLK to I2S_TXD valid

BCLK period

S5

ns

S6

0

—

S7

—

15

S8

I2S_BCLK to I2S_TXD invalid

I2S_RXD/I2S_FS input setup before I2S_BCLK

I2S_RXD/I2S_FS input hold after I2S_BCLK

0

—

S9

15

0

—

S10

—

S1

S2

I2S_MCLK (output)

I2S_BCLK (output)

I2S_FS (output)

I2S_FS (input)

I2S_TXD

S3

S4

S5

S7

S6

S10

S9

S7

S8

S9

S10

I2S_RXD

Figure 33. I²S timing — master mode

Table 56. I2S slave mode timing (limited voltage range)

Num

Description

Operating voltage

Min.

2.7

80

45%

4.5

2

Max.

Unit

3.6

—

V

S11

S12

S13

S14

S15

S16

S17

S18

S19

I2S_BCLK cycle time (input)

ns

I2S_BCLK pulse width high/low (input)

I2S_FS input setup before I2S_BCLK

I2S_FS input hold after I2S_BCLK

55%

—

MCLK period

ns

—

I2S_BCLK to I2S_TXD/I2S_FS output valid

I2S_BCLK to I2S_TXD/I2S_FS output invalid

I2S_RXD setup before I2S_BCLK

—

20

—

0

4.5

2

—

I2S_RXD hold after I2S_BCLK

I2S_TX_FS input assertion to I2S_TXD output valid¹

—

25

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

68

Kinetis K66 Sub-Family, Rev. 4, 04/2017

NXP Semiconductors

Peripheral operating requirements and behaviors

S11

S12

I2S_BCLK (input)

I2S_FS (output)

I2S_FS (input)

I2S_TXD

S12

S15

S16

S13

S14

S19

S15

S16

S15

S16

S17

S18

I2S_RXD

Figure 34. I²S timing — slave modes

3.8.12.1 Normal Run, Wait and Stop mode performance over the full

operating voltage range

This section provides the operating performance over the full operating voltage for the

device in Normal Run, Wait and Stop modes.

Table 57. I2S/SAI master mode timing

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.71

40

3.6

—

V

S1

S2

S3

S4

S5

I2S_MCLK cycle time

ns

I2S_MCLK (as an input) pulse width high/low

I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)

45%

80

55%

—

MCLK period

ns

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%

55%

15

BCLK period

ns

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output valid

—

S6

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output invalid

0

—

ns

S7

S8

S9

I2S_TX_BCLK to I2S_TXD valid

I2S_TX_BCLK to I2S_TXD invalid

—

0

15

—

ns

I2S_RXD/I2S_RX_FS input setup before

I2S_RX_BCLK

15

S10

I2S_RXD/I2S_RX_FS input hold after

I2S_RX_BCLK

0

—

ns

Kinetis K66 Sub-Family, Rev. 4, 04/2017

69

NXP Semiconductors

Peripheral operating requirements and behaviors

S1

S2

I2S_MCLK (output)

S3

S4

I2S_TX_BCLK/

I2S_RX_BCLK (output)

S4

S5

S7

S6

I2S_TX_FS/

I2S_RX_FS (output)

S10

S9

I2S_TX_FS/

I2S_RX_FS (input)

S7

S8

I2S_TXD

I2S_RXD

S9

S10

Figure 35. I2S/SAI timing — master modes

Table 58. I2S/SAI slave mode timing

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.71

80

3.6

—

V

S11

S12

I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)

ns

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low

(input)

45%

55%

MCLK period

S13

S14

I2S_TX_FS/I2S_RX_FS input setup before

I2S_TX_BCLK/I2S_RX_BCLK

4.5

2

—

ns

I2S_TX_FS/I2S_RX_FS input hold after

I2S_TX_BCLK/I2S_RX_BCLK

—

S15

S16

S17

S18

S19

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid

I2S_RXD setup before I2S_RX_BCLK

—

0

23.1

—

ns

4.5

2

—

I2S_RXD hold after I2S_RX_BCLK

I2S_TX_FS input assertion to I2S_TXD output valid¹

—

25

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

70

Kinetis K66 Sub-Family, Rev. 4, 04/2017

NXP Semiconductors

Peripheral operating requirements and behaviors

S11

S12

I2S_TX_BCLK/

I2S_RX_BCLK (input)

S12

S15

S16

I2S_TX_FS/

I2S_RX_FS (output)

S13

S14

I2S_TX_FS/

I2S_RX_FS (input)

S15

S19

S16

I2S_TXD

I2S_RXD

S17

S18

Figure 36. I2S/SAI timing — slave modes

3.8.12.2 VLPR, VLPW, and VLPS mode performance over the full

operating voltage range

This section provides the operating performance over the full operating voltage for the

device in VLPR, VLPW, and VLPS modes.

Table 59. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.71

62.5

3.6

—

V

S1

S2

S3

S4

S5

I2S_MCLK cycle time

ns

I2S_MCLK pulse width high/low

I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)

45%

250

55%

—

MCLK period

ns

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%

55%

45

BCLK period

ns

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output valid

—

S6

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output invalid

0

—

ns

S7

S8

S9

I2S_TX_BCLK to I2S_TXD valid

I2S_TX_BCLK to I2S_TXD invalid

—

0

45

—

ns

I2S_RXD/I2S_RX_FS input setup before

I2S_RX_BCLK

45

S10

I2S_RXD/I2S_RX_FS input hold after

I2S_RX_BCLK

0

—

ns

Kinetis K66 Sub-Family, Rev. 4, 04/2017

71

NXP Semiconductors

Peripheral operating requirements and behaviors

S1

S2

I2S_MCLK (output)

S3

S4

I2S_TX_BCLK/

I2S_RX_BCLK (output)

S4

S5

S7

S6

I2S_TX_FS/

I2S_RX_FS (output)

S10

S9

I2S_TX_FS/

I2S_RX_FS (input)

S7

S8

I2S_TXD

I2S_RXD

S9

S10

Figure 37. I2S/SAI timing — master modes

Table 60. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.71

250

3.6

—

V

S11

I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)

ns

S12

S13

S14

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low

(input)

45%

55%

MCLK period

I2S_TX_FS/I2S_RX_FS input setup before

I2S_TX_BCLK/I2S_RX_BCLK

30

5

—

ns

I2S_TX_FS/I2S_RX_FS input hold after

I2S_TX_BCLK/I2S_RX_BCLK

—

S15

S16

S17

S18

S19

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid

I2S_RXD setup before I2S_RX_BCLK

—

0

56.5

—

ns

30

5

—

I2S_RXD hold after I2S_RX_BCLK

I2S_TX_FS input assertion to I2S_TXD output valid¹

—

72

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

72

Kinetis K66 Sub-Family, Rev. 4, 04/2017

NXP Semiconductors

Dimensions

S11

S12

I2S_TX_BCLK/

I2S_RX_BCLK (input)

S12

S15

S16

I2S_TX_FS/

I2S_RX_FS (output)

S13

S14

I2S_TX_FS/

I2S_RX_FS (input)

S15

S19

S16

I2S_TXD

I2S_RXD

S17

S18

Figure 38. I2S/SAI timing — slave modes

3.9 Human-machine interfaces (HMI)

3.9.1 TSI electrical specifications

Table 61. TSI electrical specifications

Symbol

TSI_RUNF

TSI_RUNV

Description

Min.

—

Typ.

100

—

Max.

Unit

µA

Fixed power consumption in run mode

—

Variable power consumption in run mode

(depends on oscillator's current selection)

1.0

128

µA

TSI_EN

TSI_DIS

Power consumption in enable mode

Power consumption in disable mode

TSI analog enable time

—

100

1.2

66

—

µA

µs

pF

V

TSI_TEN

—

TSI_CREF

TSI_DVOLT

TSI reference capacitor

—

1.0

—

Voltage variation of VP & VM around nominal

values

0.19

1.03

4 Dimensions

4.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

Kinetis K66 Sub-Family, Rev. 4, 04/2017

73

NXP Semiconductors

Pinout

To find a package drawing, go to nxp.com and perform a keyword search for the

drawing’s document number:

If you want the drawing for this package

144-pin LQFP

Then use this document number

98ASS23177W

98ASA00222D

144-pin MAPBGA

5 Pinout

5.1 K66 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control Module is responsible

for selecting which ALT functionality is available on each pin.

144

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

LQFP MAP

BGA

—

L5

RTC_

WAKEUP_B

—

1

M5

A10

B10

C10

D3

NC

PTE0

ADC1_SE4a

PTE0

SPI1_PCS1

SPI1_SOUT

SPI1_SCK

SPI1_SIN

UART1_TX

UART1_RX

SDHC0_D1

SDHC0_D0

TRACE_

CLKOUT

I2C1_SDA

I2C1_SCL

RTC_

CLKOUT

2

3

4

D2

D1

E4

PTE1/

LLWU_P0

ADC1_SE5a

ADC1_SE6a

ADC1_SE7a

ADC1_SE5a

ADC1_SE6a

ADC1_SE7a

PTE1/

LLWU_P0

TRACE_D3

TRACE_D2

TRACE_D1

SPI1_SIN

PTE2/

LLWU_P1

PTE2/

LLWU_P1

UART1_

CTS_b

SDHC0_

DCLK

PTE3

UART1_

RTS_b

SDHC0_

CMD

SPI1_SOUT

5

6

7

E5

H3

E3

VDD

VSS

VDD

VSS

PTE4/

LLWU_P2

DISABLED

PTE4/

LLWU_P2

SPI1_PCS0

UART3_TX

UART3_RX

SDHC0_D3

TRACE_D0

8

9

E2

E1

PTE5

DISABLED

PTE5

SPI1_PCS2

SPI1_PCS3

SDHC0_D2

I2S0_MCLK

FTM3_CH0

FTM3_CH1

PTE6/

LLWU_P16

PTE6/

LLWU_P16

UART3_

CTS_b

USB0_SOF_

OUT

10

F4

PTE7

DISABLED

PTE7

UART3_

RTS_b

I2S0_RXD0

FTM3_CH2

74

NXP Semiconductors

Kinetis K66 Sub-Family, Rev. 4, 04/2017

Pinout

144

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

LQFP MAP

BGA

11

12

13

14

15

F3

F2

F1

G4

G3

PTE8

DISABLED

PTE8

I2S0_RXD1

I2S0_TXD1

I2C3_SDA

I2C3_SCL

I2S0_RX_FS LPUART0_

TX

FTM3_CH3

FTM3_CH4

FTM3_CH5

FTM3_CH6

FTM3_CH7

PTE9/

LLWU_P17

PTE9/

LLWU_P17

I2S0_RX_

BCLK

LPUART0_

RX

PTE10/

LLWU_P18

PTE10/

LLWU_P18

I2S0_TXD0

LPUART0_

CTS_b

USB1_ID

PTE11

I2S0_TX_FS

LPUART0_

RTS_b

PTE12

I2S0_TX_

BCLK

16

17

18

19

20

21

22

23

24

25

26

27

28

E6

F7

F6

H1

H2

G1

G2

J2

VDD

VSS

USB0_DP

USB0_DM

VREG_OUT

VREG_IN0

VREG_IN1

USB1_VSS

USB1_DP

USB1_DM

USB0_DP

USB0_DM

VREG_OUT

VREG_IN0

DISABLED

USB0_DP

USB0_DM

VREG_OUT

VREG_IN0

VREG_IN1

USB1_VSS

USB1_DP

USB1_DM

USB1_VBUS

K2

J1

K1

L1

L2

USB1_VBUS DISABLED

ADC0_DM0/

ADC1_DM3

ADC0_DM0/

ADC1_DM3

ADC0_DM0/

ADC1_DM3

29

30

M1

M2

ADC1_DP0/

ADC0_DP3

ADC1_DP0/

ADC0_DP3

ADC1_DP0/

ADC0_DP3

ADC1_DM0/

ADC0_DM3

ADC1_DM0/

ADC0_DM3

ADC1_DM0/

ADC0_DM3

31

32

33

34

35

H5

G5

G6

H6

K3

VDDA

VREFH

VREFL

VSSA

VDDA

VREFH

VREFL

VSSA

VDDA

VREFH

VREFL

VSSA

ADC1_SE16/ ADC1_SE16/ ADC1_SE16/

CMP2_IN2/

ADC0_SE22

CMP2_IN2/

ADC0_SE22

CMP2_IN2/

ADC0_SE22

36

37

J3

ADC0_SE16/ ADC0_SE16/ ADC0_SE16/

CMP1_IN2/

ADC0_SE21

CMP1_IN2/

ADC0_SE21

CMP1_IN2/

ADC0_SE21

M3

VREF_OUT/

CMP1_IN5/

CMP0_IN5/

ADC1_SE18

VREF_OUT/

CMP1_IN5/

CMP0_IN5/

ADC1_SE18

VREF_OUT/

CMP1_IN5/

CMP0_IN5/

ADC1_SE18

Kinetis K66 Sub-Family, Rev. 4, 04/2017

75

NXP Semiconductors

Pinout

144

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

LQFP MAP

BGA

38

39

L3

L4

DAC0_OUT/

CMP1_IN3/

ADC0_SE23

DAC0_OUT/

CMP1_IN3/

ADC0_SE23

DAC0_OUT/

CMP1_IN3/

ADC0_SE23

DAC1_OUT/

CMP0_IN4/

CMP2_IN3/

ADC1_SE23

DAC1_OUT/

CMP0_IN4/

CMP2_IN3/

ADC1_SE23

DAC1_OUT/

CMP0_IN4/

CMP2_IN3/

ADC1_SE23

40

41

42

43

44

45

M7

M6

L6

—

XTAL32

EXTAL32

VBAT

XTAL32

EXTAL32

VBAT

XTAL32

EXTAL32

VBAT

VDD

—

VSS

M4

PTE24

ADC0_SE17

PTE24

CAN1_TX

CAN1_RX

UART4_TX

UART4_RX

I2C0_SCL

I2C0_SDA

EWM_OUT_

b

46

47

48

K5

K4

J4

PTE25/

LLWU_P21

ADC0_SE18

DISABLED

ADC0_SE18

PTE25/

LLWU_P21

EWM_IN

PTE26

PTE27

PTE26

PTE27

ENET_1588_ UART4_

CLKIN

RTC_

CLKOUT

USB0_CLKIN

CTS_b

UART4_

RTS_b

49

50

H4

J5

PTE28

PTA0

PTE28

PTA0

JTAG_TCLK/ TSI0_CH1

SWD_CLK/

EZP_CLK

UART0_

CTS_b/

UART0_

COL_b

FTM0_CH5

LPUART0_

CTS_b

JTAG_TCLK/ EZP_CLK

SWD_CLK

51

52

J6

PTA1

PTA2

JTAG_TDI/

EZP_DI

TSI0_CH2

TSI0_CH3

PTA1

PTA2

UART0_RX

FTM0_CH6

FTM0_CH7

I2C3_SDA

I2C3_SCL

LPUART0_

RX

JTAG_TDI

EZP_DI

K6

JTAG_TDO/

TRACE_

SWO/

UART0_TX

LPUART0_

TX

JTAG_TDO/

TRACE_

SWO

EZP_DO

53

54

55

K7

L7

PTA3

JTAG_TMS/

SWD_DIO

TSI0_CH4

TSI0_CH5

PTA3

UART0_

RTS_b

FTM0_CH0

FTM0_CH1

LPUART0_

RTS_b

JTAG_TMS/

SWD_DIO

PTA4/

LLWU_P3

NMI_b/

EZP_CS_b

PTA4/

LLWU_P3

NMI_b

EZP_CS_b

M8

PTA5

DISABLED

PTA5

USB0_CLKIN FTM0_CH2

RMII0_

RXER/

CMP2_OUT

I2S0_TX_

BCLK

JTAG_

TRST_b

MII0_RXER

56

57

58

E7

G7

J7

VDD

VSS

VDD

VSS

PTA6

DISABLED

PTA6

PTA7

FTM0_CH3

FTM0_CH4

CLKOUT

TRACE_

CLKOUT

59

J8

PTA7

ADC0_SE10

RMII0_MDIO/

MII0_MDIO

TRACE_D3

76

NXP Semiconductors

Kinetis K66 Sub-Family, Rev. 4, 04/2017

Pinout

144

LQFP MAP

BGA

144

Pin Name

Default

ADC0_SE11

DISABLED

CMP2_IN0

CMP2_IN1

DISABLED

CMP3_IN1

CMP3_IN2

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

60

61

62

63

64

65

66

67

68

K8

L8

PTA8

ADC0_SE11

PTA8

FTM1_CH0

FTM1_CH1

FTM2_CH0

FTM2_CH1

FTM1_CH0

FTM1_CH1

UART0_TX

UART0_RX

RMII0_MDC/

MII0_MDC

FTM1_QD_

PHA/

TPM1_CH0

TRACE_D2

TRACE_D1

TRACE_D0

PTA9

MII0_RXD3

MII0_RXD2

FTM1_QD_

PHB/

TPM1_CH1

M9

L9

PTA10/

LLWU_P22

PTA10/

LLWU_P22

FTM2_QD_

PHA/

TPM2_CH0

PTA11/

LLWU_P23

PTA11/

LLWU_P23

MII0_RXCLK I2C2_SDA

FTM2_QD_

PHB/

TPM2_CH1

K9

PTA12

CMP2_IN0

CMP2_IN1

PTA12

CAN0_TX

CAN0_RX

SPI0_PCS0

SPI0_SCK

SPI0_SOUT

RMII0_

RXD1/

MII0_RXD1

I2C2_SCL

I2C2_SDA

I2S0_TXD0

FTM1_QD_

PHA/

TPM1_CH0

J9

PTA13/

LLWU_P4

PTA13/

LLWU_P4

RMII0_

RXD0/

MII0_RXD0

I2S0_TX_FS

FTM1_QD_

PHB/

TPM1_CH1

L10

L11

K10

PTA14

PTA15

PTA16

PTA14

PTA15

PTA16

RMII0_CRS_ I2C2_SCL

I2S0_RX_

BCLK

I2S0_TXD1

DV/

MII0_RXDV

CMP3_IN1

CMP3_IN2

RMII0_

TXEN/

MII0_TXEN

I2S0_RXD0

UART0_

CTS_b/

UART0_

COL_b

RMII0_TXD0/

MII0_TXD0

I2S0_RX_FS I2S0_RXD1

I2S0_MCLK

69

K11

PTA17

ADC1_SE17

PTA17

SPI0_SIN

UART0_

RTS_b

RMII0_TXD1/

MII0_TXD1

70

71

72

E8

G8

VDD

VSS

M12

PTA18

EXTAL0

PTA18

PTA19

FTM0_FLT2

FTM1_FLT0

FTM_CLKIN0

FTM_CLKIN1

TPM_

CLKIN0

73

M11

PTA19

XTAL0

LPTMR0_

ALT1

TPM_

CLKIN1

74

75

76

77

78

79

80

81

L12

K12

J12

J11

J10

H12

H11

H10

RESET_b

PTA24

PTA25

PTA26

PTA27

PTA28

PTA29

RESET_b

CMP3_IN4

CMP3_IN5

DISABLED

RESET_b

CMP3_IN4

CMP3_IN5

PTA24

PTA25

PTA26

PTA27

PTA28

PTA29

MII0_TXD2

FB_A29

FB_A28

FB_A27

FB_A26

FB_A25

FB_A24

MII0_TXCLK

MII0_TXD3

MII0_CRS

MII0_TXER

MII0_COL

PTB0/

LLWU_P5

ADC0_SE8/

ADC1_SE8/

TSI0_CH0

ADC0_SE8/

ADC1_SE8/

TSI0_CH0

PTB0/

LLWU_P5

I2C0_SCL

FTM1_CH0

RMII0_MDIO/ SDRAM_

MII0_MDIO

FTM1_QD_

PHA/

TPM1_CH0

CAS_b

Kinetis K66 Sub-Family, Rev. 4, 04/2017

77

NXP Semiconductors

Pinout

144

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

LQFP MAP

BGA

82

H9

PTB1

ADC0_SE9/

ADC1_SE9/

TSI0_CH6

ADC0_SE9/

ADC1_SE9/

TSI0_CH6

PTB1

I2C0_SDA

FTM1_CH1

RMII0_MDC/

MII0_MDC

SDRAM_

RAS_b

FTM1_QD_

PHB/

TPM1_CH1

83

84

G12

G11

PTB2

PTB3

ADC0_SE12/ ADC0_SE12/ PTB2

TSI0_CH7 TSI0_CH7

I2C0_SCL

I2C0_SDA

UART0_

RTS_b

ENET0_

1588_TMR0

SDRAM_WE

FTM0_FLT3

ADC0_SE13/ ADC0_SE13/ PTB3

UART0_

CTS_b/

UART0_

COL_b

ENET0_

1588_TMR1

SDRAM_

CS0_b

FTM0_FLT0

TSI0_CH8

85

86

87

88

89

90

91

92

G10

G9

PTB4

PTB5

PTB6

PTB7

PTB8

PTB9

PTB10

PTB11

ADC1_SE10

ADC1_SE11

ADC1_SE12

ADC1_SE13

DISABLED

ADC1_SE10

ADC1_SE11

ADC1_SE12

ADC1_SE13

PTB4

PTB5

PTB6

PTB7

PTB8

PTB9

PTB10

PTB11

ENET0_

1588_TMR2

SDRAM_

CS1_b

FTM1_FLT0

FTM2_FLT0

ENET0_

1588_TMR3

F12

F11

F10

F9

FB_AD23/

SDRAM_D23

FB_AD22/

SDRAM_D22

UART3_

RTS_b

FB_AD21/

SDRAM_D21

DISABLED

SPI1_PCS1

SPI1_PCS0

SPI1_SCK

UART3_

CTS_b

FB_AD20/

SDRAM_D20

E12

E11

ADC1_SE14

ADC1_SE15

ADC1_SE14

ADC1_SE15

UART3_RX

FB_AD19/

SDRAM_D19

FTM0_FLT1

FTM0_FLT2

UART3_TX

FB_AD18/

SDRAM_D18

93

94

95

H7

F5

VSS

VDD

E10

PTB16

TSI0_CH9

PTB16

PTB17

PTB18

SPI1_SOUT

SPI1_SIN

CAN0_TX

UART0_RX

UART0_TX

FTM2_CH0

FTM_CLKIN0 FB_AD17/

SDRAM_D17

EWM_IN

TPM_

CLKIN0

96

97

E9

PTB17

PTB18

TSI0_CH10

TSI0_CH11

TSI0_CH10

TSI0_CH11

FTM_CLKIN1 FB_AD16/

SDRAM_D16

EWM_OUT_

b

TPM_

CLKIN1

D12

I2S0_TX_

BCLK

FB_AD15/

SDRAM_A23 PHA/

TPM2_CH0

FTM2_QD_

98

D11

PTB19

TSI0_CH12

PTB19

CAN0_RX

FTM2_CH1

I2S0_TX_FS

FB_OE_b

FTM2_QD_

PHB/

TPM2_CH1

99

D10

D9

PTB20

PTB21

PTB22

PTB23

DISABLED

PTB20

PTB21

PTB22

PTB23

SPI2_PCS0

SPI2_SCK

SPI2_SOUT

SPI2_SIN

FB_AD31/

SDRAM_D31

CMP0_OUT

CMP1_OUT

CMP2_OUT

CMP3_OUT

100

101

102

FB_AD30/

SDRAM_D30

C12

C11

FB_AD29/

SDRAM_D29

SPI0_PCS5

FB_AD28/

SDRAM_D28

78

NXP Semiconductors

Kinetis K66 Sub-Family, Rev. 4, 04/2017

Pinout

144

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

LQFP MAP

BGA

103

104

105

B12

B11

A12

PTC0

ADC0_SE14/ ADC0_SE14/ PTC0

TSI0_CH13 TSI0_CH13

SPI0_PCS4

SPI0_PCS3

SPI0_PCS2

PDB0_

EXTRG

USB0_SOF_

OUT

FB_AD14/

SDRAM_A22

I2S0_TXD1

I2S0_TXD0

I2S0_TX_FS

PTC1/

LLWU_P6

ADC0_SE15/ ADC0_SE15/ PTC1/

TSI0_CH14 TSI0_CH14 LLWU_P6

UART1_

RTS_b

FTM0_CH0

FB_AD13/

SDRAM_A21

PTC2

ADC0_SE4b/ ADC0_SE4b/ PTC2

UART1_

CTS_b

FTM0_CH1

FB_AD12/

SDRAM_A20

CMP1_IN0/

TSI0_CH15

CMP1_IN0/

TSI0_CH15

106

A11

PTC3/

LLWU_P7

CMP1_IN1

PTC3/

LLWU_P7

SPI0_PCS1

UART1_RX

UART1_TX

FTM0_CH2

CLKOUT

I2S0_TX_

BCLK

107

108

109

H8

—

VSS

VDD

VSS

VDD

A9

PTC4/

LLWU_P8

DISABLED

PTC4/

LLWU_P8

SPI0_PCS0

SPI0_SCK

SPI0_SOUT

SPI0_SIN

FTM0_CH3

I2S0_RXD0

FB_AD11/

SDRAM_A19

CMP1_OUT

CMP0_OUT

I2S0_MCLK

110

111

112

113

114

115

116

117

118

119

120

D8

C8

B8

A8

D7

C7

B7

A7

D6

C6

B6

PTC5/

LLWU_P9

DISABLED

CMP0_IN0

CMP0_IN1

PTC5/

LLWU_P9

LPTMR0_

ALT2

FB_AD10/

SDRAM_A18

FTM0_CH2

PTC6/

LLWU_P10

CMP0_IN0

CMP0_IN1

PTC6/

LLWU_P10

PDB0_

EXTRG

I2S0_RX_

BCLK

FB_AD9/

SDRAM_A17

PTC7

PTC8

PTC9

PTC10

PTC7

USB0_SOF_

OUT

I2S0_RX_FS FB_AD8/

SDRAM_A16

ADC1_SE4b/ ADC1_SE4b/ PTC8

CMP0_IN2 CMP0_IN2

FTM3_CH4

FTM3_CH5

FTM3_CH6

FTM3_CH7

I2S0_MCLK

FB_AD7/

SDRAM_A15

ADC1_SE5b/ ADC1_SE5b/ PTC9

CMP0_IN3

I2S0_RX_

BCLK

FB_AD6/

SDRAM_A14

FTM2_FLT0

FTM3_FLT0

CMP0_IN3

ADC1_SE6b

PTC10

I2C1_SCL

I2C1_SDA

I2S0_RX_FS FB_AD5/

SDRAM_A13

PTC11/

LLWU_P11

ADC1_SE7b

DISABLED

ADC1_SE7b

PTC11/

LLWU_P11

I2S0_RXD1

FB_RW_b

PTC12

PTC13

PTC14

PTC15

PTC12

PTC13

PTC14

PTC15

UART4_

RTS_b

FTM_CLKIN0 FB_AD27/

SDRAM_D27

TPM_

CLKIN0

UART4_

CTS_b

FTM_CLKIN1 FB_AD26/

SDRAM_D26

TPM_

CLKIN1

UART4_RX

FB_AD25/

SDRAM_D25

UART4_TX

FB_AD24/

SDRAM_D24

121

122

123

—

VSS

VDD

A6

PTC16

DISABLED

PTC16

PTC17

CAN1_RX

CAN1_TX

UART3_RX

UART3_TX

ENET0_

1588_TMR0

FB_CS5_b/

FB_TSIZ1/

FB_BE23_

16_BLS15_

8_b/

SDRAM_

DQM2

124

D5

PTC17

DISABLED

ENET0_

1588_TMR1

FB_CS4_b/

FB_TSIZ0/

Kinetis K66 Sub-Family, Rev. 4, 04/2017

79

NXP Semiconductors

Pinout

144

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

LQFP MAP

BGA

FB_BE31_

24_BLS7_0_

b/

SDRAM_

DQM3

125

C5

PTC18

DISABLED

PTC18

UART3_

RTS_b

ENET0_

1588_TMR2

FB_TBST_b/

FB_CS2_b/

FB_BE15_8_

BLS23_16_b/

SDRAM_

DQM1

126

127

B5

A5

PTC19

DISABLED

PTC19

UART3_

CTS_b

ENET0_

1588_TMR3

FB_CS3_b/

FB_BE7_0_

BLS31_24_b/

SDRAM_

FB_TA_b

DQM0

PTD0/

LLWU_P12

PTD0/

LLWU_P12

SPI0_PCS0

UART2_

RTS_b

FTM3_CH0

FB_ALE/

FB_CS1_b/

FB_TS_b

128

129

130

131

132

D4

C4

B4

A4

A3

PTD1

ADC0_SE5b

DISABLED

ADC0_SE6b

ADC0_SE5b

PTD1

SPI0_SCK

SPI0_SOUT

SPI0_SIN

UART2_

CTS_b

FTM3_CH1

FTM3_CH2

FTM3_CH3

FTM0_CH4

FTM0_CH5

FB_CS0_b

PTD2/

LLWU_P13

PTD2/

LLWU_P13

UART2_RX

FB_AD4/

SDRAM_A12

I2C0_SCL

I2C0_SDA

SPI1_PCS0

SPI1_SCK

PTD3

UART2_TX

FB_AD3/

SDRAM_A11

PTD4/

LLWU_P14

PTD4/

LLWU_P14

SPI0_PCS1

SPI0_PCS2

UART0_

RTS_b

FB_AD2/

SDRAM_A10

EWM_IN

PTD5

ADC0_SE6b

ADC0_SE7b

PTD5

UART0_

CTS_b/

UART0_

COL_b

FB_AD1/

SDRAM_A9

EWM_OUT_

b

133

A2

PTD6/

LLWU_P15

ADC0_SE7b

PTD6/

LLWU_P15

SPI0_PCS3

UART0_RX

FTM0_CH6

FTM0_CH7

FB_AD0

FTM0_FLT0

SPI1_SOUT

SPI1_SIN

134

135

136

M10

F8

VSS

VDD

PTD7

VDD

A1

DISABLED

PTD7

CMT_IRO

I2C0_SCL

I2C0_SDA

UART0_TX

SDRAM_

CKE

FTM0_FLT1

FB_A16

137

138

139

140

C9

B9

B3

B2

PTD8/

LLWU_P24

DISABLED

PTD8/

LLWU_P24

LPUART0_

RX

PTD9

LPUART0_

TX

FB_A17

PTD10

LPUART0_

RTS_b

FB_A18

PTD11/

LLWU_P25

PTD11/

LLWU_P25

SPI2_PCS0

SDHC0_

CLKIN

LPUART0_

CTS_b

FB_A19

141

142

B1

C3

PTD12

PTD13

DISABLED

PTD12

PTD13

SPI2_SCK

FTM3_FLT0

SDHC0_D4

SDHC0_D5

FB_A20

FB_A21

SPI2_SOUT

80

NXP Semiconductors

Kinetis K66 Sub-Family, Rev. 4, 04/2017

Pinout

144

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

LQFP MAP

BGA

143

144

C2

C1

PTD14

PTD15

DISABLED

PTD14

PTD15

SPI2_SIN

SDHC0_D6

SDHC0_D7

FB_A22

FB_A23

SPI2_PCS1

5.2 Recommended connection for unused analog and digital

pins

Table 62 shows the recommended connections for analog interface pins if those

analog interfaces are not used in the customer's application

Table 62. Recommended connection for unused analog interfaces

Pin Type

Analog/non GPIO

GPIO/Analog

K66

Short recommendation

Float

Detailed recommendation

Analog input - Float

ADCx/CMPx

VREF_OUT

Float

Analog output - Float

DAC0_OUT, DAC1_OUT

RTC_WAKEUP_B

XTAL32

Analog output - Float

EXTAL32

Analog input - Float

PTA18/EXTAL0

PTA19/XTAL0

PTx/ADCx

Analog input - Float

GPIO/Analog

Analog output - Float

GPIO/Analog

Float (default is analog input)

GPIO/Analog

PTx/CMPx

GPIO/Analog

PTx/TSIOx

GPIO/Digital

PTA0/JTAG_TCLK

Float (default is JTAG with

pulldown)

GPIO/Digital

PTA1/JTAG_TDI

PTA2/JTAG_TDO

PTA3/JTAG_TMS

PTA4/NMI_b

Float

Float (default is JTAG with

pullup)

Float (default is JTAG with

pullup)

Float (default is JTAG with

pullup)

10kΩ pullup or disable and

float

Pull high or disable in PCR &

FOPT and float

GPIO/Digital

USB

PTx

Float

Float (default is disabled)

USB0_DP

USB0_DM

VREG_OUT

Float

USB

Tie to input and ground

through 10kΩ

Tie to input and ground

through 10kΩ

USB

VREG_IN0

Tie to output and ground

through 10kΩ

Tie to output and ground

through 10kΩ

Table continues on the next page...

Kinetis K66 Sub-Family, Rev. 4, 04/2017

81

NXP Semiconductors

Pinout

Table 62. Recommended connection for unused analog interfaces (continued)

Pin Type

K66

Short recommendation

Detailed recommendation

USB

VREG_IN1

Tie to output and ground

through 10kΩ

Tie to output and ground

through 10kΩ

USB

USB1_VSS

USB1_DP

USB1_DM

Always connect to VSS

USB

Float

USB

USB1_VBUS

VBAT

VDDA

Always connect to VDD

potential

Always connect to VDD

potential

VREFH

VREFL

VSSA

VREFH

VREFL

VSSA

Always connect to VDD

potential

Always connect to VDD

potential

Always connect to VSS

potential

Always connect to VSS

potential

Always connect to VSS

potential

Always connect to VSS

potential

5.3 K66 Pinouts

The below figure shows the pinout diagram for the devices supported by this document.

Many signals may be multiplexed onto a single pin. To determine what signals can be

used on which pin, see the previous section.

82

Kinetis K66 Sub-Family, Rev. 4, 04/2017

NXP Semiconductors

Pinout

PTE0

PTE1/LLWU_P0

PTE2/LLWU_P1

PTE3

1

108

107

106

105

104

103

102

101

100

99

VDD

2

VSS

3

PTC3/LLWU_P7

PTC2

4

VDD

5

PTC1/LLWU_P6

PTC0

VSS

6

PTE4/LLWU_P2

PTE5

7

PTB23

PTB22

PTB21

PTB20

PTB19

PTB18

PTB17

PTB16

VDD

8

PTE6/LLWU_P16

PTE7

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

PTE8

98

PTE9/LLWU_P17

PTE10/LLWU_P18

PTE11

97

96

95

PTE12

94

VDD

VSS

93

VSS

PTB11

PTB10

PTB9

92

VSS

91

USB0_DP

90

USB0_DM

PTB8

89

VREG_OUT

VREG_IN0

PTB7

88

PTB6

87

VREG_IN1

PTB5

86

USB1_VSS

USB1_DP

PTB4

85

PTB3

84

USB1_DM

PTB2

83

USB1_VBUS

ADC0_DM0/ADC1_DM3

ADC1_DP0/ADC0_DP3

ADC1_DM0/ADC0_DM3

VDDA

PTB1

82

PTB0/LLWU_P5

PTA29

PTA28

PTA27

PTA26

PTA25

PTA24

RESET_b

PTA19

81

80

79

78

VREFH

77

VREFL

76

VSSA

75

_SE16/CMP2_IN2/ADC0_SE22

_SE16/CMP1_IN2/ADC0_SE21

74

73

Figure 39. K66 144 LQFP Pinout Diagram

Kinetis K66 Sub-Family, Rev. 4, 04/2017

83

NXP Semiconductors

Ordering parts

1

2

3

4

5

6

7

8

9

10

11

12

PTD6/

LLWU_P15

A

B

C

D

E

F

PTC8

PTC4/

LLWU_P8

NC

PTC3/

LLWU_P7

PTC2

A

B

C

D

E

F

PTD7

PTD12

PTD15

PTD5

PTD4/

LLWU_P14

PTD0/

LLWU_P12

PTC16

PTC12

PTD11/

LLWU_P25

PTD10

PTD13

PTE0

PTD3

PTC19

PTC18

PTC17

VDD

PTC15

PTC14

PTC13

VDD

PTC11/

LLWU_P11

PTC7

PTD9

NC

PTC1/

LLWU_P6

PTC0

PTB22

PTB18

PTB10

PTB6

PTD14

PTD2/

LLWU_P13

PTC10

PTC9

VDD

VSS

PTC6/

LLWU_P10

PTD8/

LLWU_P24

PTB23

PTB19

PTB11

PTB7

PTE2/

LLWU_P1

PTE1/

LLWU_P0

PTD1

PTE3

PTC5/

LLWU_P9

PTB21

PTB17

PTB9

PTB5

PTB1

PTB20

PTB16

PTB8

PTB4

PTE6/

LLWU_P16

PTE5

PTE4/

LLWU_P2

VDD

VSS

PTE10/

LLWU_P18

PTE9/

LLWU_P17

PTE8

PTE12

VSS

PTE7

VDD

VSS

G

H

J

G

H

J

VREG_OUT

USB0_DP

VREG_IN0

USB0_DM

VREG_IN1

USB1_VSS

PTE11

PTE28

PTE27

PTE26

VREFH

VDDA

PTA0

VREFL

VSSA

PTA1

VSS

PTB3

PTB2

VSS

PTB0/

LLWU_P5

PTA29

PTA26

PTA17

PTA15

PTA28

PTA25

PTA24

RESET_b

ADC0_SE16/

CMP1_IN2/

ADC0_SE21

PTA13/

LLWU_P4

USB1_DP

PTA6

PTA3

PTA7

PTA8

PTA9

PTA27

PTA16

PTA14

ADC1_SE16/

CMP2_IN2/

ADC0_SE22

PTE25/

LLWU_P21

K

L

K

L

USB1_DM

USB1_VBUS

PTA2

PTA12

DAC1_OUT/

CMP0_IN4/

CMP2_IN3/

ADC1_SE23

DAC0_OUT/

CMP1_IN3/

ADC0_SE23

ADC0_DM0/

ADC1_DM3

RTC_

WAKEUP_B

VBAT

PTA4/

LLWU_P3

PTA11/

LLWU_P23

VREF_OUT/

CMP1_IN5/

CMP0_IN5/

ADC1_SE18

M

ADC1_DP0/ ADC1_DM0/

PTE24

NC

EXTAL32

XTAL32

PTA5

PTA10/

LLWU_P22

VSS

PTA19

PTA18

ADC0_DP3

ADC0_DM3

1

2

3

4

5

6

7

8

9

10

11

12

Figure 40. K66 144 MAPBGA Pinout Diagram

6 Ordering parts

84

Kinetis K66 Sub-Family, Rev. 4, 04/2017

NXP Semiconductors

Part identification

6.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable

part numbers for this device, go to nxp.com and perform a part number search for the

following device numbers: PK66 and MK66

7 Part identification

7.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the

values of these fields to determine the specific part you have received.

7.2 Format

Part numbers for this device have the following format:

Q K## A M FFF R T PP CC N

7.3 Fields

This table lists the possible values for each field in the part number (not all

combinations are valid):

Field

Description

Values

Q

Qualification status

Kinetis family

• M = Fully qualified, general market flow

• P = Prequalification

K##

A

• K65

• K66

Key attribute

• D = Cortex-M4 w/ DSP

• F = Cortex-M4 w/ DSP and FPU

M

Flash memory type

• N = Program flash only

• X = Program flash and FlexMemory

FFF

Program flash memory size

• 32 = 32 KB

• 64 = 64 KB

• 128 = 128 KB

• 256 = 256 KB

• 512 = 512 KB

• 768 = 768 KB

Table continues on the next page...

Kinetis K66 Sub-Family, Rev. 4, 04/2017

85

NXP Semiconductors

Terminology and guidelines

Field

Description

Values

• 1M0 = 1 MB

• 2M0 = 2 MB

R

Silicon revision

• Z = Initial

• (Blank) = Main

• A = Revision after main

T

Temperature range (°C)

Package identifier

• V = –40 to 105

• C = –40 to 85

PP

• FM = 32 QFN (5 mm x 5 mm)

• FT = 48 QFN (7 mm x 7 mm)

• LF = 48 LQFP (7 mm x 7 mm)

• LH = 64 LQFP (10 mm x 10 mm)

• MP = 64 MAPBGA (5 mm x 5 mm)

• LK = 80 LQFP (12 mm x 12 mm)

• LL = 100 LQFP (14 mm x 14 mm)

• MC = 121 MAPBGA (8 mm x 8 mm)

• LQ = 144 LQFP (20 mm x 20 mm)

• MD = 144 MAPBGA (13 mm x 13 mm)

• MI= 169 MAPBGA (9 mm x 9 mm)

• AC= 169 WLCSP (5.6 mm x 5.5 mm)

CC

Maximum CPU frequency (MHz)

• 5 = 50 MHz

• 7 = 72 MHz

• 10 = 100 MHz

• 12 = 120 MHz

• 15 = 150 MHz

• 16 = 168 MHz

• 18 = 180 MHz

N

Packaging type

• R = Tape and reel

• (Blank) = Trays

7.4 Example

This is an example part number:

MK66FN2M0VMD18

8 Terminology and guidelines

8.1 Definitions

Key terms are defined in the following table:

86

Kinetis K66 Sub-Family, Rev. 4, 04/2017

NXP Semiconductors

Terminology and guidelines

Term

Definition

Rating

A minimum or maximum value of a technical characteristic that, if exceeded, may cause

permanent chip failure:

• Operating ratings apply during operation of the chip.

• Handling ratings apply when the chip is not powered.

NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic

begins to exceed one of its operating ratings.

Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during

operation to avoid incorrect operation and possibly decreasing the useful life of the chip

Operating behavior

A specified value or range of values for a technical characteristic that are guaranteed during

operation if you meet the operating requirements and any other specified conditions

Typical value

A specified value for a technical characteristic that:

• Lies within the range of values specified by the operating behavior

• Is representative of that characteristic during operation when you meet the typical-value

conditions or other specified conditions

NOTE: Typical values are provided as design guidelines and are neither tested nor

guaranteed.

8.2 Examples

Operating rating:

EXAMPLE

Operating requirement:

Operating behavior that includes a typical value:

EXAMPLE

Kinetis K66 Sub-Family, Rev. 4, 04/2017

87

NXP Semiconductors

Terminology and guidelines

8.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as

specified):

Symbol

Description

Ambient temperature

Supply voltage

Value

Unit

T_A

25

°C

V

V_DD

3.3

8.4 Relationship between ratings and operating requirements

Fatal range

Degraded operating range

Normal operating range

Degraded operating range

Fatal range

Expected permanent failure

- No permanent failure

- Correct operation

- No permanent failure

Expected permanent failure

- Possible decreased life

- Possible incorrect operation

- Possible decreased life

- Possible incorrect operation

–∞

∞

Operating (power on)

Fatal range

Handling range

Fatal range

Expected permanent failure

No permanent failure

Expected permanent failure

–∞

∞

Handling (power off)

8.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.

• During normal operation, don’t exceed any of the chip’s operating requirements.

• If you must exceed an operating requirement at times other than during normal

operation (for example, during power sequencing), limit the duration as much as

possible.

88

Kinetis K66 Sub-Family, Rev. 4, 04/2017

NXP Semiconductors

Revision History

9 Revision History

The following table provides a revision history for this document.

Table 63. Revision History

Rev. No.

Date

Substantial Changes

Initial Release

0

1

02/2015

04/2015

• Editorial change

• Updated OTG/EH and BC rev. 1.2 specification references in USB Full Speed

Transceiver and High Speed PHY specifications section

• Updated USBDCD electrical specifications table

• Updated the typical values and maximum values of specs in Power consumption

operating behaviors table

• Removed PSTOP2 current from Power consumption operating behaviors table

• Updated the values of DS5 and DS7 in Master mode DSPI timing (full voltage

range) table

• Updated the footnote and description of V_DIO, V_AIOand I_Din Voltage and current

operating ratings table

• Updated the values and description of specs in Voltage and current operating

requirements table

• Updated the leakage current specs in Voltage and current operating behaviors table

• Added Notes column in Thermal operating requirements

• Updated the values of 48MHz IRC in Low power mode peripheral adders table

• Added new footnotes for I_INRUSHin USB VREG electrical specifications table to

better document operation.

• Updated the figures "SDRAM write timing diagram" and SDRAM read timing

diagram" in the section "SDRAM controller specifications."

• Updated the pinout table, and pinout diagrams in the section "Pinouts."

2

3

05/2015

01/2016

• Added new footnotes for I_INRUSHin USB VREG electrical specifications table to

better document operation.

• Updated the figures "SDRAM write timing diagram" and SDRAM read timing

diagram" in the section "SDRAM controller specifications."

• Updated the pinout table, and pinout diagrams in the section "Pinouts."

• Updated the symbol in footnote of Thermal Operating specs

• Updated the description of PLL operating current in MCG specifications table

• Updated the values of IRC48M specifications table

• Added USB FS and USB HS logo in front page

• Updated Terminology and guidelines section

• Updated the maximum values of I_{DD_LLS2}and I_{DD_LLS3}in Power consumption

operating behaviors table

4

03/2017

• Removed the verbiage of "except RTC_WAKEUP pins" from the description for R_PU

and R_PDin Voltage and current operating behaviors table

• Updated the unit of ADC conversion rate from "Kbps" to "kS/s" in 16-bit ADC

operating conditions table

• Added MII signal switching specifications table and RMII signal switching

specifications table for full voltage range

• Added MDIO serial management timing specifications section

• Updated I2C switching specifications section

• Updated the minimum and maximum value of Voltage reference output with factory

trim in VREF full-range operating requirements table in Voltage reference electrical

specifications section

Kinetis K66 Sub-Family, Rev. 4, 04/2017

89

NXP Semiconductors

Revision History

90

Kinetis K66 Sub-Family, Rev. 4, 04/2017

NXP Semiconductors


型号：	MK66FX1M0VMD18
厂家：	NXP
描述：	Kinetis K66 Sub-Family
文件：	总91页 (文件大小：1097K)
中文：	中文翻译
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