MC33253DWR2_技术文档

Order Number: MC33253/D

Rev 3, 03/2001

MC33253

Advance Information

55 VOLTS

Full Bridge Pre-Driver

SEMICONDUCTOR

TECHNICAL DATA

The MC33253 is a full bridge driver including integrated charge

pump, two independent high and low side driver channels.

The high and low side drivers include a cross conduction suppression

circuit, which, if enabled, prevents the external power FETs from being on

at the same time.

The drive outputs are capable to source and sink 1 A pulse peak

current. The low side channel is referenced to ground, the high side

channel is floating above ground.

A linear regulator provides a maximum of 15.5V to supply the low

side gate driver stages. The high side driver stages are supplied with a

10V charge pump voltage. Such built-in feature, associated to external

capacitor provides a full floating high side drive.

An under- and over-voltage protection prevents erratic system

operation at abnormal supply voltages. Under fault, these functions force

the driver stages into off state.

DW SUFFIX

PLASTIC PACKAGE

CASE 751F-05

The logic inputs are compatible with standard CMOS or LSTTL

outputs. The input hysteresis makes the output switching time

independent of the input transition time.

The global enable logic signal can be used to disable the charge

pump and all the bias circuit. The net advantage is the reduction of the

quiescent supply current to under 10µA. To wake up the circuit, 5 V has to

be provided at G_EN. A built-in single supply operational amplifier could

be used to feedback information from the output load to the external

MCU.

PIN CONNECTIONS

(TOP VIEW)

CASE 751F-05

1

28

27

26

25

24

23

22

21

V_CC

C2

IS_OUT

G_EN

2

• V_CCOperating Voltage Range from 5.5 V up to 55 V

• V_CC2Operating Voltage Range from 5.5 V up to 28 V

• Automotive Temperature Range -40°C to 125°C

• 1A Pulse Current Output Driver

/CCS

3

4

5

6

7

8

9

CP_OUT

SRC_HS₁

SRC_HS₂

GATE_HS₁

/IN_HS₁

GATE_HS₂

/IN_HS₂

IN_HS₂

• Fast PWM Capability

IN_HS₁

• Built-In Charge Pump

/IN_LS₁

IN_LS₁

/IN_LS₂

• Cross Conduction Suppression Circuit

20 IN_LS₂

19

18

17

GATE_LS₂

GND2

10

11

GATE_LS₁

GND1

LR_OUT 12

V_CC2

GND_A 14

IS_-IN

13

16 IS_+IN

C1

15

ORDERING INFORMATION

Temperature

Device

PC33253DW

Package

SOIC28

Range

-40^oC to +125^oC

This document contains information on a new product. Specifications and information herein are

subject to change without notice.

Page 1/15

MC33253

Figure 1. Principal Building Blocks

Ccp

C1

C2

V

CC2

V

CC

V

CC2

UV/OV

Detect

V

C1

C2

CC

5.5 V...

V

CC

RDY

28 V

Charge

Pump

V

DD

EN

Vpos

V

CC

GND

+13.5 V

G_EN

/CCS

5.5 V...

55 V

C

CP_OUT

V

CC2

V

DD

V

+13.5 V

CP_OUT

CC2

Linear

Reg

EN

+5.0 V

C

LR_OUT

GND

+13.5 V

LR_OUT

HIGH AND LOW SIDE

CONTROL WITH CHARGE PUMP

CCS

BRG_EN

Vgs_ls

Vgs_hs

OUT

CCS

V

CC

IN_HS1

Output

Driver

IN

V

/V

Pulse

DD

DD POS

GATE_HS1

SRC_HS1

Generator

Level Shift

/IN_HS1

IN_LS1

G_LOW_H

Input

&

G_LOW_LS

CCS

LOGIC

V

OUT

DD

IN

Output

Driver

V

/V

Pulse

Generator

DD CC

GATE_LS1

Level Shift

/IN_LS1

IN_HS2

HIGH AND LOW SIDE CHANNEL

WITH CROSS CONDUCTION SUPPRESSION

Vgs_ls

BRG_EN

CCS

V

CC

OUT

Output

Driver

IN

V

/V

Pulse

Generator

DD

DD POS

GATE_HS2

SRC_HS2

Level Shift

/IN_HS2

IN_LS2

G_LOW_H

Input

&

G_LOW_LS

CCS

V

DD

IN

OUT

Output

Driver

V

/V

Pulse

Generator

DD CC

GATE_LS2

Level Shift

/IN_LS2

HIGH AND LOW SIDE CHANNEL WITH

CROSS CONDUCTION SUPPRESSION

CA^-

SENSE CURRENT AMPLIFIER

CAO

-

+

CA⁺

GND

IS

-IN

OUT

+IN

MC33253

MOTOROLA

rev3.0 - 2/15

MC33253

ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to GND.

Rating

Symbol

Min

Max

Unit

Supply Voltage1

V_CC

-0.3

65

V

Supply Voltage2 (NOTE 1)

V_CC2

-0.3

35

18

65

20

V

Linear Regulator Output Voltage

High Side Floating Supply Absolute Voltage

High Side Floating Source Voltage

High Side Gate Voltage

V_{LR_out}

V_{CP_OUT}

V_{SRC_HS}

V_{GATE_HS}

High Side Gate Source Voltage

V_{GATE_HS}

- V_{SRC_HS}

High Side Source Current from Cpout in Switch On State

High Side Floating Supply Gate Voltage

I_S

250

65

mA

V

V_{CP_OUT}

-0.3

- V_{GATE_HS}

Low Side Output Voltage

V_{GATE_LS}

V_{G_EN}

V_IN

-0.3

17

V

Wake up Voltage

35

Logic Input Voltage

10

Charge Pump Capacitor Voltage

Operational Amplifier Output Voltage

Operational Amplifier Inverting Input Voltage

V_C1

V_{LR_OUT}

V_C2

65

7

V_CAO

-

7

V_CA

+

Operational Amplifier Non Inverting Input Voltage

ESD Voltage on any Pins (HBM, 100pF, 1.5kOhms)

-0.3

-2.0

7

V

V_CA

V_ESD

2.0

kV

Power Dissipation and Thermal Characteristics

Maximum Power Dissipation@25°C

Thermal Resistance Junction-to-Air

Operating Junction Temperature

Storage Temperature

P_D

R_θJA

T_J

2

W

°C/W

°C

60

-40

-65

+150

T_stg

°C

OPERATING CONDITIONS ^{Typical values for T}_A^{= 25}°C, Min/Max values for T_A= -40°C to +125°C

Rating

Symbol

Min

Max

Unit

Supply Voltage1

Supply Voltage2

V_CC

5.5

55

V

V_CC2

5.5

28

V

High Side Floating Supply Absolute Voltage

V_{CP_OUT}

V_CC+4

V_CC+11but<65

NOTE1: VCC can sustain load dump pulse 40V, 400ms, 2Ohms

MC33253

MOTOROLA

rev3.0 - 3/15

MC33253

STATIC ELECTRICAL CHARACTERISTICS V = 12 V, V

= 12 V, C = 33 nF, G_EN = 4.5 V unless otherwise specified.

CC

CC2

CP

Typical values for TA = 25°C, Min/Max values for TA = -40°C to +125°C, unless otherwise specified.

Characteristics

LOGIC SECTION

Pin #

Symbol

Min

Typ

Max

Unit

Logic “1” Input Voltage (IN_LS & IN_HS)

Logic “0” Input Voltage (IN_LS & IN_HS)

Logic “1” Input Current Vin=5V

7, 9, 20, 22

V_IH

V_IL

2.0

10

0.8

V

I_in+

200

2.0

1000

10

uA

V

Logic “0” Input Current Vin=0V

I_in-

Logic “0” Input Voltage (/IN_LS & /IN_HS&/CCS)

Logic “1” Input Voltage (/IN_LS & /IN_HS&/CCS)

Logic “0” Input Current Vin=5V

6, 8, 21, 23,

26

V_IH

V_IL

0.8

V

6, 8, 21, 23,

26

I_in+

TBD

4.5

TBD

V_CC2

500

uA

V

Logic “1” Input Current Vin=0V

I_in-

Wake Up Input Voltage (G_EN)

27

V_{G_EN}

I_{G_EN}

5.0

Wake Up Current (G_EN) VG_EN = 14 V

LINEAR REGULATOR SECTION

200

uA

Linear Regulator

V_{LR_OUT}@ V_CC2from 16.5 to 28 V, I_LOADfrom

0mA to 20mA

12

V_{LR_OUT}

13.5

16.5

V

Linear Regulator

V_{LR_OUT}@ V_CC2=12 V, I_LOAD= 20mA

V_{LR_OUT}

V_CC2

1.5

-

V_{LR_OUT}@ V_CC2=5.5V, I_LOAD=TBD, V_CC= 5.5V

TBD

CHARGE PUMP SECTION

Charge Pump Output Voltage, referenced to V_CC

I_LOAD= 0mA, C_Cpout=1uF

3

V_{CP_OUT}

V_{LR_OUT}

- 2

V

Charge Pump Output Voltage, referenced to V_CC

I_LOAD= 7mA, C_Cpout=1uF

V_{LR_OUT}

-3

Charge Pump Output Voltage, referenced to V_CC

V_CC2= V_CC=5.5V

V_{LR_OUT}

- TBD

I_LOAD= 0mA, C_Cpout=1uF

Charge Pump Output Voltage, referenced to V_CC

3

V_{CP_OUT}

V_{LR_OUT-}

-TBD

V

V_CC2= V_CC=5.5V

I

_LOAD= 7mA, C_Cpout=1uF

Peak current through pin 15under rapid changing

Vcc voltages (see Figure 6)

15

I_C1

-2.0

-1.5

2.0

A

V

Minimum peak voltage at pin 15under rapid

changing Vcc voltages (see Figure 6)

V_C1min

SUPPLY VOLTAGE SECTION

Quiescent Vcc Supply Current V_{G_EN}=0V

1

TBD

uA

Operating Vcc Supply Current

(@V_CC=55V and V_CC2=28V)

(@V_CC=12V and V_CC2=12V)

1

TBD

mA

Quiescent Vcc2 Supply Current V_{G_EN}=0V

13

TBD

uA

MC33253

MOTOROLA

rev3.0 - 4/15

MC33253

Pin #

Characteristics

Symbol

Min

Typ

Max

Unit

Operating Vcc2 Supply Current

(@V_CC=55V and V_CC2=28V)

(@V_CC=12V and V_CC2=12V)

Logic pin inactive (high impedance)

13

10

8

mA

Under Voltage Shutdown V_CC2(Note2)

Under Voltage Shutdown V_CC

Over Voltage Shutdown V_CC

Over Voltage Shutdown V_CC2

OUTPUT SECTION

13

1

UV2

UV

4.6

5.1

61

5.5

64

V

1

OV

57

13

OV2

29.5

31

32.5

Output Sink Resistance (Turned off)

V_{GATE_HS}- V_{SRC_HS}=1V

R_DS

22.0

200

18

Ohms

mA

3, 4, 5, 10,

19, 24, 25

Output Source Resistance (Turned on)

R_DS

V_{CP_OUT}- V_{GATE_HS}=0.1V

High Side Source Current from Cpout in Switch

On State

4, 25

I_Smax

Max Voltage (V_{GATE_HS}- V_{SRC_HS)}

,

V

4, 5, 24, 25

INH=1, I_Smax=200mA

SENSE CURRENT AMPLIFIER SECTION (Internal VCC supply @ 12V)

Output Dynamic Range (I_sink/source= 200µA)

28

V_OH

V_OL

4.7

5.0

50

V

mV

300

Open Loop Gain (at 25°C)

A

dB

uA

mV

V

Input Bias Current

16, 17

I_IB

1.0

5.0

5

Input Offset Voltage (at 25°C)

Input Common Mode Voltage Range

Common Mode Rejection Ratio

Sink Capability (Vo>1.1V) (Note 3)

Source Capability (Vo<5V) (Note 3)

Gain Bandwidth Product

V_io

-5.0

0

2.0

ICMR

CMRR

I_sink

70

3.0

1.8

dB

mA

MHz

V

28

2.0

I_source

GBW

V_CAO

Operational Amplifier Output Voltage, I_sink=500uA

28

0.5

Operational Amplifier Output Voltage,

I_source=500uA

5

V

Operational Amplifier Slew Rate (+)

Operational Amplifier Slew Rate (-)

SR+

SR-

1

V/us

MC33253

MOTOROLA

rev3.0 - 5/15

MC33253

DYNAMIC ELECTRICAL CHARACTERISTICS V = 12 V, V

= 12 V, C = 33 nF, G_EN = 4.5 V unless otherwise specified.

CP

CC

CC2

Typical values for TA = 25°C, Min/Max values for TA = -40°C to +125°C, unless otherwise specified.

Characteristics

Pin #

Symbol

Min

Typ

Max

Unit

Prop. Delay HS and LS, C_load=5nF;

Between 50% Input to 50% Output

(see Figure 2)

5, 6, 7, 8, 9,

20, 21, 22, 23

t_PD

200

300

ns

Turn On Rise Time, C_load=5nF ;

10% to 90% (NOTE 4) (see Figure 2)

t_r

t_f

80

180

ns

Turn Off Fall Time, C_load=5nF ;

10% to 90% (NOTE 4) (see Figure 2)

5, 10, 19, 24

NOTE 2: Between 4.6V and 5.5V, the device has been a non erroneous behaviour.

NOTE 3: Input overdrive 1V

NOTE 4: Rise time is given by time needed to charge the gate from 1V to 10V (Vice versa for fall time)

NOTE : C_loadcorresponds to a capacitor between GATE_HS and SRC_HS for the high side and between GATE_LS and ground for low side.

N.B.

In some applications a large dV/dt at Pin 2 (C2) due to sudden changes at V_CCcan cause a large peak currents flowing through

Pin15 (C1).

Positive transitions at Pin2 (C2) ;mimimum peak current :

I_c1min = 2.0A

t_c1min = 600ns (see for peak description)

Negative transitions at Pin2 (C2); maximum peak current :

I_c1max = 2.0A

t

_c1max = 600ns (see for peak description)

Current sourced by Pin 15 (C1) during a large dV/dt will result in a negative voltage at Pin 15; negative transitions at Pin2(C2);

minimum peak voltage:

V_c1min = -1.5V

t

_c1max = 600ns (see for peak description)

Figure 2. Limits of C1 Current&Voltage with Large ValuesdV/dt of Vcc

VCC

I

_c1max

t_C1min

I[C1+C2]

0 A

t_c1max

I

_c1min

V[LR_OUT]

0 V

V[C1]

V

_c1min

MC33253

MOTOROLA

rev3.0 - 6/15

MC33253

Figure 3. Dynamic Characteristics

/IN_HS

or /IN_LS

50%

IN_HS

or IN_LS

t

pd

GATE_HS

or GATE_LS

50%

t

r

f

10% 90%

90%10%

Driver Characteristics

Turn-On

For turn-on the current required to charge the gate source capacitor Ciss in the specified time can be calculated as follows:

Peak Current for Rise/Fall Time (tr) and a typical PowerMosFET Gate Charge Qg. IP = Qg/tr = 75 nC/80 ns ª 1.0 A

Turn-Off

The peak current for turn-off can be obtained in the same way as for turn-on. In addition to the dynamic current, required to

turn-off or turn-on the FET, various application related switching scenarios have to be considered:

The output driver sources a peak current of up to 1A for 200 ns to turn on the gate. After 200 ns 100 mA are provided

continuously to maintain the gate charged. The output driver sinks a peak current of up to 1A for 200 ns to turn off the gate. After

200 ns 100 mA are sinked continuously to maintain the gate discharged. In order to withstand high dV/dt spikes a low resistive

path between gate and source is implemented during the off state.

Figure 4. OFF-State Driver Requirement

Flyback Spike charge LS-Gate via C

Flyback Spike pull down HS-

Flyback Spike charge LS-Gate via

C Charge Current I up to 2.0 A!

rss

Drain V Increase Delayed

Drain V Increase Uncontrolled

Charge Current I up to 2.0 A! Uncon-

GS

rss

Turn-Off of High Side FET

Turn-On of High Side FET

trolled Turn-On of Low Side FET

Delayed Turn-Off of Low Side FET

V

BAT

C

rss

OFF

g_hs

OFF

g_hs

V

GATE

g_hs

-V

DRN

I

LOAD

L1

C

iss

C

iss

C

rss

I

rss

V

GATE

g_ls

OFF

g_ls

OFF

g_ls

C

iss

Driver Requirement: Low

Resistive Gate-Source

Path during OFF-State

Driver Requirement: Low Resistive Driver Requirement:

Driver Requirement: Low Resistive

Gate Source Path during OFF-State. High Peak Sink Current Capab. Gate-Source Path during OFF-State

High Peak Sink Current Capab.

MC33253

MOTOROLA

rev3.0 - 7/15

MC33253

Driver Supply

The High Side Driver is supplied from the internal charge pump buffered at CP_OUT. The low-drop regulator provides

approx. 3.5 mA (f_PWM=50kHz)pergate.In case of the full bridge that means approximately. 14 mA; 7.0 mA for the high side and

7.0 mA for the low side. (Note: The average current required to switch a gate with a frequency of 100kHz is: Average Current

(Charge Pump) for PWM Frq. (f_PWM) andI_CP=Q_g*f_PWM=75nC*100kHz=7.5mA.A full bridge application switch only one high side

and one low side at the same time.)

External capacitors on Charge Pump and on Linear Regulator are necessary to supply high peak current absorbed during

switching. The Low Side Driver is supplied from built in low drop regulator.

Gate Protection

The low side gate is protected by the internal linear regulator, which guarantees that V_{GATE_LS}doesnotexceed the maximum

V_GS. Especially when working with the charge pump the voltage at POS_HS can be up to 65V. The high side gate is clamped

internally, in order to avoid a V_GSexceeding 14V.

The Gate protection does not include a Flyback Voltage Clamp that protects the driver and the external FET from a Flyback

voltage that can appear when driving inductive load.This Flyback voltage can reach high negative voltage values and needs to

be clamped externally.

Figure 5. Gate Protection and Flyback Voltage Clamp

V

gs_hs

gs_ls

V

M

CC

1

OUT

IN

GATE_HS

SRC_HS

Output

Driver

V

< 14 V

GS

under all

G_LOW

conditions

L

Inductive

Flyback Voltage

Clamp

1

D

cl

G_LOW

IN

M

2

OUT

GATE_LS

Output

Driver

TMOS Failure Protection

All output driver stages are protected against TMOS failure conditions. If one of the external power FETs is destroyed (Gate

= V_CC, or Gate = Gnd) the function of the remaining output driver stages is not affected. All output drivers are short circuit

protected against short circuits to ground.

Cross Conduction Suppression

The purpose of the cross conduction suppression is to avoid that high and low side FET are turned on at the same time,

which prevents the half bridge power FETs of a shoot-through condition. The CCS can be disabled / enabled by an external

signal (/CCS).

- /CCS=0, the cross conduction is not allowed.

- /CCS=1, the cross conduction is allowed.

MC33253

MOTOROLA

rev3.0 - 8/15

MC33253

Figure 6. Input Logic and Cross Conduction Suppression

G_EN

EN_CP/LDO

AND

“1” Enable Charge Pump and LDO

UV_OV

RDY

“1” Supply is ok

{

“1” Charge Pump is Ready

/CCS

“0” Cross Conduction Suppression is Enabled

en2hs = G_LOW_LS, en2ls = G_LOW_HS

CCS

BRG_EN

“1” Cross Conduction Suppression is Disabled

en2hs = “1”, en2ls = “1” en1hs = “0”, en1ls = “0”

10 k

IN_HS

AND

OUT_HS

AND

en1_hs

10 k

“1” Turn-On FET

OR

G_LOW_H

en2_hs

/IN_HS

AND

“1” FET is Turned-Off

G_LOW_LS

10 k

IN_LS

en2_ls

drv_ls

“1” FET is Turned-Off

OR

OUT_LS

en1_ls

AND

“1” Turn-On FET

/IN_LS

Logic Inputs

Logic Input Voltage Range:

Absolute Max :

-0.3 V ... 10 V

Wake Up Function:

(G_EN)

4.5 V ... V_CC2

During Wake-Up the logic is supplied from the G_EN pin.

Low Drop Linear Regulator

The low drop linear regulator provides the 5.0 V for the logic section of the driver, the V_{gs_ls}buffered at LR_OUT and the +13.5 V for the

charge pump, which generates the V_{gs_hs}.The low drop linear regulator provides 3.5 mA average current per driver stage. If typically V_CC2

exceeds 14.5V the output is limited to 14V.

Charge Pump

The charge pump generates the high side driver supply voltage ( V_{gs_hs}), buffered at C_{CP_OUT}. The basic circuit (Fig 7), shows

charge pump without load:

Figure 7. Charge Pump Basic Circuit

V_{CP_OUT}

(2)

D1

V_{LR_OUT}

Ccp

Ccp_out

Osc.

A

D2

(1)

Vbat

When the oscillator is in low state (1), C_cpis charged through D2 until its voltage reaches V_bat-V_d2. When the oscillator is in high

state (2), C_cpis discharged though D1 in C_{cp_out}, and final voltage of the charge pump, V_{cp_out}is V_bat+V_{LR_OUT}- 2V_d. The frequency of

the MC33253 oscillator is about 330 kHz.

MC33253

MOTOROLA

rev3.0 - 9/15

MC33253

The Figure 8 represents a simplified circuitry of the high side gate driver.

Figure 8. High Side Gate Driver

V_LR-OUT

CP_out

Tosc2

Ccp

D1

Ccp_out

C1

C2

D2

Tosc1

Vcc

(3)

T1

HS

MOSFET

GATE_HS

Rg

T2

SRC_HS

M

LS

MOSFET

pins

The transistors Tosc1 and Tosc2 are the oscillator switching MOSFETs. When Tosc1 is on, the oscillator is at low level. When

Tosc2 is on, the oscillator is at high level. The high side MOSFET predriver is composed of two transistors T1 and T2. When T1 is on

the HS MOSFET is turn on, when T2 is on the HS MOSFET is off. The capacitor C_{cp_out}provides peak current to the HS MOSFET

through T1 during turn on (3) as shown in figure 11.

C_cp

C_cpchoice depends on Power MOSFET characteristics and the working switching frequency. The following diagrams show the

influence of C_cpvalue on V_{cp_out}average voltage level. The diagrams are given at two different frequencies for two power MOSFETs

(MTP60N06HD and MPT36N06V).

Figure 9. V_{cp_out}Versus C_cp

21.5

21

20kHz

20KhZ

100 KhZ

100kHz

21

20.5

20

20.5

20

19.5

19

19.5

19

18.5

18

18.5

5

25

45

65

85

5

25

45

Ccp (nF)

65

85

Ccp (nF)

MTP36N06V (Q_g=40nC)

MTP60N06HD (Q_g=50nC)

Figure 10.

MOTOROLA

MC33253

rev3.0 - 10/15

MC33253

The smaller C_cpvalue is, the smaller V_{cp_out}value is. Moreover, for a same C_cpvalue, when the switching frequency

increases, the average V_{cp_out}level decreases. For most of the applications a typical value of 33nF is recommended.

C_{cp_out}

As shown in figure 11, at high side MOSFET turn on, V_{cp_out}voltage decreases. This decrease can be calculated according to

C_{cp_out}value as following :

Q_g

∆V_{Ccp_ out}

=

C_{cp _ out}

Q_g: Power MosFET Gate Charge

The following figure is the simplified C_{cp_out}current and voltage waveforms.

f

_pwm: working switching frequency

Figure 11. Simplified C_{cp_out}Current and Voltage Waveforms

High Side

turn on

Oscillator

in high

state

V_{Cp_out}

Oscillator

in low

∆V_Ccp

_ out

state

average V_{Cp_out}

I_{Cp_out}

f_PWM

f=330kHz

Peak

Current

C_{LR_OUT}

C_{LR_OUT}provides peak current needed by the low side MOSFET turn on. V_{LR_OUT}decreasing is as follow:

Q_g

∆V_{LR _out}

=

C_{LR _out}

Capacitors typical values

In most working cases the following typical values are advised for a good charge pump performing:

C_cp=33nF, C_{cp_out}=470nF and C_{LR_OUT}=470nF.

These values give a typical 100mV voltage ripple on V_{cp_out}and V_{LR_OUT}with Q_g=50nC.

OP-Amp

The built-in A.O.P. available in the MC33253 allows to get a voltage image of the H-bridge current. This voltage can be

provided by a shunt resistor, as shown in figure 13.

Typically shunt resistivity is dimensioned as low as possible (25mOhm/10A). The maximum A.O.P output voltage is 5V.

Therefore a gain of 10 sets the maximum drop voltage on the sensing resistance at 500mV.

MC33253

MOTOROLA

rev3.0 - 11/15

MC33253

A differential mode is advised as shown in fig 12:

Figure 12. : Differential A.O.P

R

3

IS

+IN

IS

OUT

+

_

AOP

R

4

V

2

IS

-IN

V

out

R

1

R

2

V

1

R2

R1

with R2=R4 and R1=R3,

V_out

R2

=

(V 2 −V1)

A gain of 10 gives

= 10 ( a )

R1

To minimize the perturbations, impedance seen by the A.O.P inputs may be as low as possible.

Knowing the maximum output current (2mA), the minimum value of (R1+R2) can be deduced when V_OUTmaximum is 5V:

5V

(R₁+ R₂)_min

=

= 2,5k ( b )

2mA

with (a) and (b), the minimum values of R1, R2, R3 and R4 can be calculated.

R1=R3=227 Ohms and R2=R4=2.27 kOhms

Over/Under Voltage Shutdown

The under voltage protection becomes active at V_CCbelow 5.5 V and the overvoltage protection is activated at V_CCabove 55 V or

at V_CC2above 28 V. If the O/UV protection is activated the outputs are driven low, in order to switch off the FETs.

Protection

A protection against double battery and load dump spikes up to 55 V is given by V_CC= 55 V. A protection against reverse

polarity is given by the external power FET with the free wheeling diodes, forming a conducting pass from ground to V_CC. An

additional protection is not provided within the circuit. There is a temperature shut down protection per each half bridge. It protects

the circuitry against temperature damage by blocking the output drives.

MC33253

MOTOROLA

rev3.0 - 12/15

MC33253

Figure 13. DC Motor Control with Microcontroller

C

V

470nF

LRout

BAT

V

LOGIC

V

/V

CC CC2

LR_OUT

/G_EN

/CCS

470nF

M

3

1

CP_OUT

C

Pout

C

1

50ohms

C2

C

33nF

GATE_HS

Cp

1

CAN

PWM

SRC_HS

1

50ohms

IN_HS

HS_1

GATE_LS

1

2

1

M

1

2

3

4

FULL

BRIDGE

DRIVER

50ohms

IN_LS

IN_HS

IN_LS

LS_1

HS_2

LS_2

GATE_HS

2

PWM

SRC_HS

2

GATE_LS

2

GND

IS

+IN

M

G

M

G

2

4

ISOUT

CURRENT FDB

-IN

mC

S

L

R

2

R

3

R

sense

R

4

R

1

This application use the internal charge pump to provide the high side floating voltage. This voltage can be provided by an

external source also.

MC33253

MOTOROLA

rev3.0 - 13/15

MC33253

Symbol

Pin Description

1

V

Supply1

CC

2

3

C2

Charge Pump Capacitor

Charge Pump Out

CP_OUT

SRC_HS1

GATE_HS1

/IN_HS1

IN_HS1

4

Source 1 Output High Side

Gate 1 Output High Side

Neg. Input High Side 1

Pos. Input High Side 1

Neg. Input Low Side 1

Pos. Input Low Side 1

Gate 1 Output Low Side

Power Ground

5

6

7

8

/IN_LS1

IN_LS1

9

10

11

12

13

GATE_LS1

GND1

LR_OUT

Linear Regulator Output

Supply 2

V

CC2

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

GND_A

C1

Analog Ground (A.O.P)

Charge Pump Capacitor

Sense OpAmp Pos. Input

Sense OpAmp Neg. Input

Logic Ground 2

IS+

IS-

GND2

GATE_LS2

IN_LS2

/IN_LS2

IN_HS2

/IN_HS2

GATE_HS2

SRC_HS2

/CCS

Gate 2 Output Low Side

Pos. Input Low Side 2

Neg. Input Low Side 2

Pos. Input High Side 2

Neg. Input High Side 2

Gate 2 Output High Side

Source 2 Output High Side

Enable Cross Conduction Suppression

Global Enable

G_EN

IS_OUT

Sense Current OpAmp Output

MC33253

MOTOROLA

rev3.0 - 14/15

D

NOTES:

A

28

15

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD PROTRUSIONS.

4. MAXIMUM MOLD PROTRUSION 0.015 PER

SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN

1

14

MILLIMETERS

DIM MIN MAX

B

PIN 1 IDENT

A

A1

B

2.35

0.13

0.35

0.23

2.65

0.29

0.49

0.32

C

D

E

e

H

L

θ

17.80 18.05

7.40 7.60

1.27 BSC

10.05 10.55

L

0.10

e

0.41

0

0.90

8

C

°

SEATING

B

C

θ

PLANE

M

S

0.025

C A

B

CASE 751F-05

ISSUE F

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability

of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all

liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do

vary in different applications and actual performance may vary over time. All operating parameters, including “Typical” must be validated for each customer application by

customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for

use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any application in which the failure of the

Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized

application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or un authorized use, even if

such claim alleges that Motorola was negligent regarding the design or manufacture of the parts. Motorola and

an Equal Employment Opportunity/Affirmative Action Employer.

are registered trademarks of Motorola, Inc. Motorola, Inc. is

How to reach us:

USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;

JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1,

P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447

Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-344-3569

Technical Information Center: 1-800-521-6274

ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre,

2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

852-26668334

HOME PAGE: http://www.motorola.com/semiconductors

MC33253/D

MC33253

MOTOROLA


型号：	MC33253DWR2
厂家：	NXP
描述：	BRUSH DC MOTOR CONTROLLER, PDSO28, PLASTIC, SOIC-28 电动机控制光电二极管
文件：	总15页 (文件大小：434K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC33253DWR2 [NXP]

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