MC33260DR2G [ONSEMI]
GreenLine TM Compact Power Factor Controller: Innovative Circuit for Cost Effective Solutions; 绿线TM紧凑型功率因数控制器：创新电路的成本效益解决方案
| 型号： | MC33260DR2G |
| 厂家： | 
ONSEMI |
| 描述： | GreenLine TM Compact Power Factor Controller: Innovative Circuit for Cost Effective Solutions |
| 文件： | 总22页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC33260
GreenLinet Compact
Power Factor Controller:
Innovative Circuit for
Cost Effective Solutions
The MC33260 is a controller for Power Factor Correction
preconverters meeting international standard requirements in
electronic ballast and off−line power conversion applications.
Designed to drive a free frequency discontinuous mode, it can also be
synchronized and in any case, it features very effective protections that
ensure a safe and reliable operation.
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MARKING
DIAGRAMS
8
This circuit is also optimized to offer extremely compact and cost
effective PFC solutions. While it requires a minimum number of
external components, the MC33260 can control the follower boost
operation that is an innovative mode allowing a drastic size reduction
of both the inductor and the power switch. Ultimately, the solution
system cost is significantly lowered.
MC33260P
AWL
YYWWG
PDIP−8
P SUFFIX
CASE 626
8
1
1
Also able to function in a traditional way (constant output voltage
regulation level), any intermediary solutions can be easily
implemented. This flexibility makes it ideal to optimally cope with a
wide range of applications.
8
SO−8
D SUFFIX
CASE 751
33260
ALYW
G
8
General Features
1
1
• Standard Constant Output Voltage or “Follower Boost” Mode
• Switch Mode Operation: Voltage Mode
• Latching PWM for Cycle−by−Cycle On−Time Control
• Constant On−Time Operation That Saves the Use of an Extra Multiplier
• Totem Pole Output Gate Drive
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
WW, W = Work Week
G or G
= Pb−Free Package
• Undervoltage Lockout with Hysteresis
• Low Startup and Operating Current
PIN CONNECTIONS
• Improved Regulation Block Dynamic Behavior
• Synchronization Capability
Feedback Input
1
2
3
4
8
7
6
5
V
CC
• Internally Trimmed Reference Current Source
• Pb−Free Packages are Available
V
Gate Drive
Gnd
control
Oscillator
Safety Features
Capacitor (C )
Current Sense
Input
T
• Overvoltage Protection: Output Overvoltage Detection
• Undervoltage Protection: Protection Against Open Loop
• Effective Zero Current Detection
Synchronization
Input
MC33260P
• Accurate and Adjustable Maximum On−Time Limitation
• Overcurrent Protection
Oscillator
1
8
V
control
Capacitor (C )
Current Sense
Input
T
Feedback Input
• ESD Protection on Each Pin
2
3
4
7
6
5
Synchronization
V
CC
Input
Filtering
Capacitor
D1...D4
Gnd
Gate Drive
L1
D1
MC33260D
C1
+
V
LOAD
(SMPS, Lamp
Ballast,...)
CC
1
2
3
4
8
7
6
5
M1
V
control
R
o
ORDERING INFORMATION
See detailed ordering and shipping information in the package
Sync
CT
R
OCP
R
cs
dimensions section on page 20 of this data sheet.
DIP−8 CONFIGURATION SHOWN
Figure 1. Typical Application
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
September, 2005 − Rev. 9
MC33260/D
MC33260
V
o
Current Mirror
I
o
2 x I x I
FB
O
O
I
− ch =
OSC
I
o
I
ref
Current
Mirror
I
o
I
o
I
ref
CT
V
ref
11 V
1.5 V
97%I
1
0
15 pF
300 k
V
reg
V
control
I
o
I
ref
ref
Output_Ctrl
I
/I
11 V
ovpH ovpL
V
ref
REGULATOR
Enable
+
I
ref
−
OVP
UVP
r
I
r
uvp
−
+
11 V/8.5 V
+
−
I
cs
(205 mA)
Synchro
r
−60 mV
1
0
11 V
+
−
Current
Sense
Synchro
Arrangement
LEB
V
CC
11 V
Output_Ctrl
ThStdwn
Drive
Gnd
S
R
R
R
Q
PWM
Latch
+
Output_Ctrl
−
Q
PWM Comparator
MC33260
Figure 2. Block Diagram
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2
MC33260
MAXIMUM RATINGS
Pin #
Pin #
PDIP−8 SO−8
Rating
Symbol
Value
Unit
Gate Drive Current*
Source
Sink
7
8
5
6
mA
I
−500
500
O(Source)
I
O(Sink)
V
Maximum Voltage
(Vcc)
16
V
V
CC
max
Input Voltage
V
in
−0.3 to +10
Power Dissipation and Thermal Characteristics
P Suffix, PDIP Package
P
Maximum Power Dissipation @ T = 85°C
600
100
mW
°C/W
D
A
R
Thermal Resistance Junction−to−Air
Operating Junction Temperature
Operating Ambient Temperature
q
T
T
JA
150
°C
°C
J
−40 to +105
A
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
ELECTRICAL CHARACTERISTICS (V = 13 V, T = 25°C for typical values, T = −40 to 105°C for min/max values
CC
J
J
unless otherwise noted.)
Pin #
Pin #
PDIP−8 SO−8
Characteristic
Symbol
Min
Typ
Max
Unit
GATE DRIVE SECTION
Gate Drive Resistor
Source Resistor @ I
7
5
W
= 100 mA
= 100 mA
R
R
OH
10
5
20
10
35
25
Drive
OL
Sink Resistor @ I
Drive
Gate Drive Voltage Rise Time (From 3.0 V Up to 9.0 V)
(Note 1)
7
7
5
5
t
−
50
−
ns
ns
r
Output Voltage Falling Time (From 9.0 V Down to 3.0 V)
(Note 1)
t
−
50
−
f
OSCILLATOR SECTION
Maximum Oscillator Swing
3
3
3
3
1
1
1
1
DV
1.4
87.5
350
1.5
100
1.6
112.5
450
V
mA
T
Charge Current @ I = 100 mA
I
I
FB
charge
charge
Charge Current @ I = 200 mA
400
mA
FB
Ratio Multiplier Gain Over Maximum Swing
K
5600
6400
7200
1/(V.A)
osc
@ I = 100 mA
FB
Ratio Multiplier Gain Over Maximum Swing
3
3
1
1
K
5600
10
6400
15
7200
20
1/(V.A)
pF
osc
@ I = 200 mA
FB
Average Internal Oscillator Pin Capacitance Over
C
int
Oscillator Maximum Swing (C Voltage Varying From
T
0 Up to 1.5 V) (Note 2)
Discharge Time (C = 1.0 nF)
3
1
T
−
0.5
1.0
ms
T
disch
REGULATION SECTION
Regulation High Current Reference
Ratio (Regulation Low Current Reference)/I
1
1
1
7
7
7
I
192
0.965
−
200
0.97
300
208
0.98
−
mA
−
regH
I
/I
regL regH
regH
V
Impedance
Z
kW
control
Vcontrol
NOTE: I is the current that is drawn by the Feedback Input Pin.
FB
1. 1.0 nF being connected between the Pin 7 and ground for PDIP−8, between Pin 5 and ground for SO−8.
2. Guaranteed by design.
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3
MC33260
ELECTRICAL CHARACTERISTICS (V = 13 V, T = 25°C for typical values, T = −40 to 105°C for min/max values
CC
J
J
unless otherwise noted.)
Pin #
Pin #
PDIP−8 SO−8
Characteristic
Symbol
Min
Typ
Max
Unit
REGULATION SECTION (continued)
Feedback Pin Clamp Voltage @ I = 100 mA
1
1
7
7
V
V
1.5
2.0
2.1
2.6
2.5
3.0
V
V
FB
FB−100
FB−200
Feedback Pin Clamp Voltage @ I = 200 mA
FB
CURRENT SENSE SECTION
Zero Current Detection Comparator Threshold
4
4
4
7
4
2
2
2
5
2
V
−90
−
−60
−0.7
−
−30
−
mV
V
ZCD−th
Negative Clamp Level (I
Bias Current @ Vcs = V
= −1.0 mA)
Cl−neg
CS−pin
ZCD−th
I
−0.2
−
−
mA
ns
mA
ns
ns
b−cs
Propagation Delay (Vcs > V
) to Gate Drive High
ZCD−th
T
500
205
400
160
−
ZCD
OCP
Current Sense Pin Internal Current Source
Leading Edge Blanking Duration
I
192
−
218
−
τ
LEB
OverCurrent Protection Propagation Delay
7
5
T
100
240
OCP
(Vcs < V
to Gate Drive Low)
ZCD−th
SYNCHRONIZATION SECTION
Synchronization Threshold
PDIP−8
SO−8
5
−
−
3
V
V
0.8
0.8
1.0
1.0
1.2
1.4
V
V
sync−th
sync−th
Negative Clamp Level (I
Minimum Off−Time
= −1.0 mA)
5
7
5
3
5
3
Cl−neg
−
1.5
−
−0.7
2.1
−
−
V
sync
T
off
2.7
0.5
ms
ms
Minimum Required Synchronization Pulse Duration
OVERVOLTAGE PROTECTION SECTION
T
sync
OverVoltage Protection High Current Threshold
1
1
7
7
I
−I
8.0
0
13
−
18
−
mA
OVPH regH
and I
Difference
regH
OverVoltage Protection Low Current Threshold
I
−I
−
OVPL regH
and I
Difference
regH
Ratio (I
/I
)
1
7
7
5
I
/I
OVPH OVPL
1.02
−
−
−
−
−
OVPH OVPL
Propagation Delay (I > 110% I to Gate Drive Low)
T
OVP
500
ns
FB
ref
UNDERVOLTAGE PROTECTION SECTION
Ratio (UnderVoltage Protection Current
1
7
7
5
I
/I
12
−
14
16
−
%
UVP regH
Threshold)/I
regH
Propagation Delay (I < 12% I to Gate Drive Low)
T
UVP
500
ns
FB
ref
THERMAL SHUTDOWN SECTION
Thermal Shutdown Threshold
Hysteresis
7
7
5
5
T
—
−
150
30
−
−
°C
°C
stdwn
DT
stdwn
V
UNDERVOLTAGE LOCKOUT SECTION
CC
Startup Threshold
8
8
6
6
V
9.7
7.4
11
12.3
9.6
V
V
stup−th
Disable Voltage After Threshold Turn−On
V
8.5
disable
TOTAL DEVICE
Power Supply Current
8
6
I
mA
CC
Startup (V = 5 V with V Increasing)
−
−
0.1
4.0
0.25
8.0
CC
CC
Operating @ I = 200 mA
FB
NOTE: Vcs is the Current Sense Pin Voltage and I is the Feedback Pin Current.
FB
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4
MC33260
Pin Numbers are Relevant to the PDIP−8 Version
1.6
1.4
1.2
1.0
0.8
0.6
0.4
1.6
1.4
1.2
1.0
0.8
0.6
−40°C
25°C
105°C
−40°C
25°C
0.4
105°C
0.2
0
0.2
0
0
20 40 60 80 100 120 140 160 180 200 220 240
185
190
195
200
205
210
I
: FEEDBACK CURRENT (mA)
I
pin1
: FEEDBACK CURRENT (mA)
pin1
Figure 3. Regulation Block Output versus
Feedback Current
Figure 4. Regulation Block Output versus
Feedback Current
1.340
1.335
1.330
1.325
1.320
1.315
1.310
3.5
3.0
2.5
2.0
1.5
1.0
−40°C
25°C
0.5
0
1.305
1.300
105°C
−40
−20
0
20
40
60
80
100
0
20 40 60 80 100 120 140 160 180 200 220 240
: FEEDBACK CURRENT (mA)
JUNCTION TEMPERATURE (°C)
I
pin1
Figure 5. Maximum Oscillator Swing versus
Temperature
Figure 6. Feedback Input Voltage versus
Feedback Current
500
450
400
350
410
405
400
395
−40°C
25°C
I
= 200 mA
pin1
105°C
300
250
200
150
100
390
385
50
0
0
20 40 60 80 100 120 140 160 180 200 220 240
: FEEDBACK CURRENT (mA)
−40
−20
0
20
40
60
80
100
I
JUNCTION TEMPERATURE (°C)
pin1
Figure 7. Oscillator Charge Current versus
Feedback Current
Figure 8. Oscillator Charge Current versus
Temperature
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5
MC33260
Pin Numbers are Relevant to the PDIP−8 Version
104
103
102
101
100
99
120
100
80
−40°C
25°C
I
= 100 mA
pin1
105°C
1 nF Connected to Pin 3
60
40
20
0
98
97
−40
−20
0
20
40
60
80
100
30
50
70
90
110 130 150 170 190 210
T , JUNCTION TEMPERATURE (°C)
J
I
: FEEDBACK CURRENT (mA)
pin1
Figure 9. Oscillator Charge Current versus
Temperature
Figure 10. On−Time versus Feedback Current
75
65
55
45
35
207
206
205
204
203
202
201
200
199
I
OCP
−40°C
25°C
105°C
1 nF Connected to Pin 3
I
regH
25
15
198
197
50
60
70
80
90
100
−40
−20
0
20
40
60
80
100
I
: FEEDBACK CURRENT (mA)
T , JUNCTION TEMPERATURE (°C)
J
pin1
Figure 11. On−Time versus Feedback Current
Figure 12. Internal Current Sources versus
Temperature
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.150
0.148
0.146
0.144
0.142
(I
/I
)
)
ovpH ref
(I /I
ovpL ref
0.140
0.138
0.136
0.134
(I /I
)
regL ref
0.97
0.96
0.132
0.130
−40
−20
0
20
40
60
80
100
−40
−20
0
20
40
60
80
100
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 13. (IovpH/Iref), (IovpL/Iref), (IregL/Iref
versus Temperature
)
Figure 14. Undervoltage Ratio versus
Temperature
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6
MC33260
Pin Numbers are Relevant to the PDIP−8 Version
−54.8
−55
4.5
−40°C
4.0
3.5
3.0
2.5
2.0
1.5
1.0
25°C
−55.2
−55.4
−55.6
−55.8
−56
105°C
−56.2
−56.4
−56.6
0.5
0
−40
−20
0
20
40
60
80
100
0
2
4
6
8
10
12
14
16
T , JUNCTION TEMPERATURE (°C)
J
V
: SUPPLY VOLTAGE (V)
CC
Figure 16. Circuit Consumption versus
Supply Voltage
Figure 15. Current Sense Threshold versus
Temperature
Vgate
20
15
10
−40°C
25°C
25°C
1
V
= 12 V
CC
C
= 1 nF
gate
I
(50 mA/div)
cross−cond
105°C
5
0
2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Ch1 10.0 V
Ch2 10.0 mVW M 1.00 ms Ch1
600 mV
V
: PIN 2 VOLTAGE (V)
control
Figure 17. Oscillator Pin Internal Capacitance
Figure 18. Gate Drive Cross Conduction
Vgate
Vgate
−ꢀ40°C
CC
105°C
CC
1
1
V
= 12 V
V
= 12 V
C
= 1 nF
C
= 1 nF
gate
gate
I
(50 mA/div)
I
(50 mA/div)
cross−cond
cross−cond
2
2
Ch1 10.0 V
Ch2 10.0 mVW M 1.00 ms Ch1
600 mV
Ch1 10.0 V
Ch2 10.0 mVW M 1.00 ms Ch1
600 mV
Figure 19. Gate Drive Cross Conduction
Figure 20. Gate Drive Cross Conduction
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7
MC33260
PIN FUNCTION DESCRIPTION
Pin #
PDIP−8
Pin #
SO−8
Function
Description
1
7
Feedback Input
This pin is designed to receive a current that is proportional to the preconverter output
voltage. This information is used for both the regulation and the overvoltage and
undervoltage protections. The current drawn by this pin is internally squared to be used
as oscillator capacitor charge current.
2
8
V
This pin makes available the regulation block output. The capacitor connected between
this pin and ground, adjusts the control bandwidth. It is typically set below 20 Hz to
obtain a nondistorted input current.
control
3
4
1
2
Oscillator Capacitor The circuit uses an on−time control mode. This on−time is controlled by comparing the
(C )
T
C
T
voltage to the V voltage. C is charged by the squared feedback current.
control T
Zero Current
Detection Input
This pin is designed to receive a negative voltage signal proportional to the current
flowing through the inductor. This information is generally built using a sense resistor.
The Zero Current Detection prevents any restart as long as the Pin 4 voltage is below
(−60 mV). This pin is also used to perform the peak current limitation. The overcurrent
threshold is programmed by the resistor connected between the pin and the external
current sense resistor.
5
3
Synchronization
Input
This pin is designed to receive a synchronization signal. For instance, it enables to
synchronize the PFC preconverter to the associated SMPS. If not used, this pin must
be grounded.
6
7
8
4
5
6
Ground
This pin must be connected to the preregulator ground.
Gate Drive
The gate drive current capability is suited to drive an IGBT or a power MOSFET.
V
This pin is the positive supply of the IC. The circuit turns on when V becomes higher
CC
CC
than 11 V, the operating range after startup being 8.5 V up to 16 V.
Filtering
Capacitor
D1...D4
L1
D1
C1
+
Load
(SMPS, Lamp
Ballast,...)
V
CC
1
2
3
4
8
7
6
5
M1
R
o
V
control
Sync
R
OCP
CT
R
cs
DIP−8 CONFIGURATION SHOWN
Figure 21. Application Schematic
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8
MC33260
FUNCTIONAL DESCRIPTION
Pin Numbers are Relevant to the PDIP−8 Version
INTRODUCTION
OPERATION DESCRIPTION
The need of meeting the requirements of legislation on
line current harmonic content, results in an increasing
demand for cost effective solutions to comply with the
Power Factor regulations. This data sheet describes a
monolithic controller specially designed for this purpose.
Most off−line appliances use a bridge rectifier associated
to a huge bulk capacitor to derive raw dc voltage from the
utility ac line.
The MC33260 is optimized to just as well drive a free
running as a synchronized discontinuous voltage mode.
It also features valuable protections (overvoltage and
undervoltage protection, overcurrent limitation, ...) that
make the PFC preregulator very safe and reliable while
requiring very few external components. In particular, it is
able to safely face any uncontrolled direct charges of the
output capacitor from the mains which occur when the
output voltage is lower than the input voltage (startup,
overload, ...).
In addition to the low count of elements, the circuit can
control an innovative mode named “Follower Boost” that
permits to significantly reduce the size of the preconverter
inductor and power MOSFET. With this technique, the
output regulation level is not forced to a constant value, but
can vary according to the a.c. line amplitude and to the
power. The gap between the output voltage and the ac line
is then lowered, what allows the preconverter inductor and
power MOSFET size reduction. Finally, this method brings
a significant cost reduction.
Rectifiers
Converter
AC
Line
+
Bulk
Load
Storage
Capacitor
Figure 22. Typical Circuit Without PFC
This technique results in a high harmonic content and in
poor power factor ratios. In effect, the simple rectification
technique draws power from the mains when the
instantaneous ac voltage exceeds the capacitor voltage. This
occurs near the line voltage peak and results in a high charge
current spike. Consequently, a poor power factor (in the
range of 0.5 − 0.7) is generated, resulting in an apparent input
power that is much higher than the real power.
A description of the functional blocks is given below.
REGULATION SECTION
Connecting a resistor between the output voltage to be
regulated and the Pin 1, a feedback current is obtained.
Typically, this current is built by connecting a resistor
between the output voltage and the Pin 1. Its value is then
given by the following equation:
V
pk
Rectified DC
V
* V
o
pin1
0
0
I
+
pin1
R
o
Line Sag
where:
R is the feedback resistor,
AC Line Voltage
AC Line Current
o
V is the output voltage,
o
V
pin1
is the Pin 1 clamp value.
The feedback current is compared to the reference current
so that the regulation block outputs a signal following the
characteristic depicted in Figure 25. According to the power
and the input voltage, the output voltage regulation level
Figure 23. Line Waveforms Without PFC
varies between two values (V )
and (V )
o regL
o regH
Active solutions are the most popular way to meet the
legislation requirements. They consist of inserting a PFC
pre−regulator between the rectifier bridge and the bulk
capacitor. This interface is, in fact, a step−up SMPS that
outputs a constant voltage while drawing a sinusoidal
current from the line.
corresponding to the I
and I
levels.
regL
regH
Regulation Block Output
1.5 V
Rectifiers
PFC Preconverter
Converter
AC
Line
+
I
o
I
I
regH
regL
(97%I
)
ref
(I )
ref
Figure 25. Regulation Characteristic
Figure 24. PFC Preconverter
The feedback resistor must be chosen so that the feedback
current should equal the internal current source I when
the output voltage exceeds the chosen upper regulation
The MC33260 was developed to control an active solution
with the goal of increasing its robustness while lowering its
global cost.
regH
voltage [(V ) ].
o regH
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9
MC33260
Pin Numbers are Relevant to the PDIP−8 Version
Consequently:
In practice, V
equation can be simplified as follows (I
replaced by its typical value 200 mA):
where:
ǒ
Ǔ
V
* V
V is the output voltage,
o
o
regH
I
pin1
R
+
R is the feedback resistor,
o
o
regH
V
pin1
is the Pin 1 clamp voltage.
is small compared to (V )
and this
being also
In practice, V
that is in the range of 2.5 V, is very small
pin1
o regH
pin1
compared to V . The equation can then be simplified by
neglecting V
regH
o
:
pin1
ǒ
Ǔ
o
regH
2
o
( )
kW
R
[ 5 V
2 V
o
I
[
charge
2
R
I
The regulation block output is connected to the Pin 2
through a 300 kW resistor. The Pin 2 voltage (V ) is
compared to the oscillator sawtooth for PWM control.
An external capacitor must be connected between Pin 2
and ground, for external loop compensation. The bandwidth
is typically set below 20 Hz so that the regulation block
output should be relatively constant over a given ac line
cycle. This integration that results in a constant on−time over
the ac line period, prevents the mains frequency output
ripple from distorting the ac line current.
o
ref
control
It must be noticed that the oscillator terminal (Pin 3) has
an internal capacitance (C ) that varies versus the Pin 3
voltage. Over the oscillator swing, its average value
typically equals 15 pF (min 10 pF, max 20 pF).
The total oscillator capacitor is then the sum of the internal
and external capacitors.
int
C
+ C ) C
pin3
T
int
PWM LATCH SECTION
OSCILLATOR SECTION
The oscillator consists of three phases:
The MC33260 operates in voltage mode: the regulation
block output (V − Pin 2 voltage) is compared to the
control
• Charge Phase: The oscillator capacitor voltage grows
oscillator sawtooth so that the gate drive signal (Pin 7) is
high until the oscillator ramp exceeds V
The on−time is then given by the following equation:
up linearly from its bottom value (ground) until it
.
control
exceeds V
(regulation block output voltage). At
control
that moment, the PWM latch output gets low and the
oscillator discharge sequence is set.
C
V
pin3
control
t
+
on
• Discharge Phase: The oscillator capacitor is abruptly
discharged down to its valley value (0 V).
• Waiting Phase: At the end of the discharge sequence,
the oscillator voltage is maintained in a low state until
the PWM latch is set again.
I
ch
where:
is the on−time,
t
C
on
is the total oscillator capacitor (sum of the
internal and external capacitor),
pin3
I
= 2 ꢀ I ꢀ I / I
o o ref
charge
I
is the oscillator charge current (Pin 3 current),
charge
V
is the Pin 2 voltage (regulation block output).
control
1
0
Output_Ctrl
Consequently, replacing I
by the expression given in
charge
the Oscillator Section:
CT
3
2
R
I C
V
o
ref
pin3
control
1
0
t
+
on
2
15 pF
2 V
o
One can notice that the on−time depends on V
o
(preconverter output voltage) and that the on−time is
maximum when Vcontrol is maximum (1.5 V typically).
Figure 26. Oscillator
At a given V , the maximum on−time is then expressed by
the following equation:
o
The oscillator charge current is dependent on the feedback
current (I ). In effect
o
2
2
ǒVcontrolǓ
ref
C
R I
I
o
pin3
o
max
I
+ 2
ǒ
Ǔ
max +
t
charge
on
I
2
2 V
ref
o
where:
This equation can be simplified replacing
I
is the oscillator charge current,
charge
2
I is the feedback current (drawn by Pin 1),
NJ
Njby K
osc
o
[(
)
]
V
* I
control max ref
I
is the internal reference current (200 mA).
ref
So, the oscillator charge current is linked to the output
voltage level as follows:
Refer to Electrical Characteristics, Oscillator Section.
Then:
2 ǒV pin1Ǔ2
2
C
R
o
pin3
* V
ǒ
Ǔ
max +
t
o
on
2
K
V
I
+
osc
o
charge
2
R
I
o
ref
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10
MC33260
Pin Numbers are Relevant to the PDIP−8 Version
Zero Current Detection
This equation shows that the maximum on−time is inversely
proportional to the squared output voltage. This property is
used for follower boost operation (refer to Follower Boost
section).
The Zero Current Detection function guarantees that the
MOSFET cannot turn on as long as the inductor current
hasn’t reached zero (discontinuous mode).
The Pin 4 voltage is simply compared to the (−60 mV)
threshold so that as long as V is lower than this threshold,
CURRENT SENSE BLOCK
cs
the circuit gate drive signal is kept in low state.
Consequently, no power MOSFET turn on is possible until
The inductor current is converted into a voltage by
inserting a ground referenced resistor (R ) in series with the
cs
the inductor current is measured as smaller than (60 mV/R )
input diodes bridge (and the input filtering capacitor).
Therefore a negative voltage proportional to the inductor
current is built:
cs
that is, the inductor current nearly equals zero.
I
(205 mA)
+ −ǒRcs LǓ
ocp
V
I
cs
D1...D4
S
Output_Ctrl
−60 mV
PWM
Latch
where:
I is the inductor current,
1
0
L
Output_Ctrl
R
R
cs
is the current sense resistor,
is the measured R voltage.
Q
+
R
V
OCP
R
V
cs
cs
−
4
LEB
OCP
R
cs
To Output Buffer
(Output_Ctrl Low <=> Gate Drive in Low State)
Figure 28. Current Sense Block
Time
Overcurrent Protection
During the power switch conduction (i.e. when the Gate
Drive Pin voltage is high), a current source is applied to the
Pin 4. A voltage drop V
is then generated across the
OCP
resistor R
that is connected between the sense resistor
OCP
and the Current Sense Pin (refer to Figure 28). So, instead of
V , the sum (V + V ) is compared to (−60 mV) and the
cs
cs
OCP
maximum permissible current is the solution of the
following equation:
ǒ
Ǔ
) V
− R Ipk
+ −60 mV
cs
max
OCP
V
OCP
where:
Ipk
is maximum allowed current,
is the sensing resistor.
max
R
cs
The overcurrent threshold is then:
−60 mV
−3
ǒROCP OCPǓ) 60 10
I
Zero Current Detection
Ipk
+
max
R
cs
V
= R
ꢀ I
OCP
OCP OCP
where:
R
An overcurrent is detected if V
crosses the threshold (−60 mV)
pin4
is the resistor connected between the pin and the
during the Power Switch on state
OCP
sensing resistor (R ),
is the current supplied by the Current Sense Pin
when the gate drive signal is high (power switch
cs
Figure 27. Current Sensing
I
OCP
The negative signal V is applied to the current sense
cs
through a resistor R . The pin is internally protected by a
conduction phase). I
equals 205 mA typically.
OCP
OCP
negative clamp (−0.7 V) that prevents substrate injection.
As long as the Pin 4 voltage is lower than (−60 mV), the
Current Sense comparator resets the PWM latch to force the
gate drive signal low state. In that condition, the power
MOSFET cannot be on.
During the on−time, the Pin 4 information is used for the
overcurrent limitation while it serves the zero current
detection during the off time.
Practically, the V
and the precedent equation can be simplified. The maximum
current is then given by the following equation:
offset is high compared to 60 mV
OCP
(
)
kW
R
OCP
( )
( )
0.205 A
Ipk
[
max
R
W
cs
Consequently, the R
resistor can program the OCP level
OCP
whatever the R value is. This gives a high freedom in the
cs
choice of R . In particular, the inrush resistor can be utilized.
cs
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11
MC33260
Pin Numbers are Relevant to the PDIP−8 Version
V
Th−Stdwn
CC
Synchronization
Arrangement
S
R
Output
Buffer
5
Q
Q
7
OVP, UVP
Current Sense
Comparator
PWM
Latch
−
+
ZCD & OCP
&
Output_Ctrl
−60 mV
PWM Latch
Comparator
+
−
V
(V
− Regulation Output)
control pin2
Oscillator Sawtooth
Figure 29. PWM Latch
A LEB (Leading Edge Blanking) has been implemented.
This circuitry disconnects the Current Sense comparator
from Pin 4 and disables it during the 400 first ns of the power
switch conduction. This prevents the block from reacting on
the current spikes that generally occur at power switch turn
on. Consequently, proper operation does not require any
filtering capacitor on Pin 4.
Practically, V
neglected. The equation can then be simplified:
that is in the range of 2.5 V, can be
pin1
(
)
(
) ( )
mA
V
+ R MW I
V
o
ovpH
ovpH
On the other hand, the OVP low threshold is:
) ǒR ovpLǓ
V
+ V
I
o
ovpL
pin1
PROTECTIONS
where I
is the internal low OVP current threshold.
ovpL
Consequently, V
being neglected:
pin1
OCP (Overcurrent Protection)
Refer to Current Sense Block.
(
)
(
) ( )
mA
V
+ R MW I
V
o
ovpL
ovpL
The OVP hysteresis prevents erratic behavior.
is guaranteed to be higher than IregH (refer to
parameters specification). This ensures that the OVP
OVP (Overvoltage Protection)
I
ovpL
The feedback current (I ) is compared to a threshold
o
current (I ). If it exceeds this value, the gate drive signal
ovpH
function doesn’t interfere with the regulation one.
is maintained low until this current gets lower than a second
level (I ).
ovpL
UVP (Undervoltage Protection)
This function detects when the feedback current is lower
Gate
Drive
Enable
than 14% of I . In this case, the PWM latch is reset and the
ref
power switch is kept off.
This protection is useful to:
• Protect the preregulator from working in too low
V
control
mains conditions.
• To detect the feedback current absence (in case of a
nonproper connection for instance).
I
o
The UVP threshold is:
I
I
I
I
I
ovpH
uvp
regL regH ovpL
ǒ
Ǔ
) ( )
mA V
(
)
(
V
[ V
) R MW I
uvp
uvp
o
pin1
Figure 30. Internal Current Thresholds
Practically (V
being neglected),
pin1
So, the OVP upper threshold is:
(
)
(
) ( )
mA V
V
+ R MW I
uvp
o
uvp
) ǒR ovpHǓ
V
+ V
I
o
ovpH
pin1
Maximum On−Time Limitation
As explained in PWM Latch, the maximum on−time is
accurately controlled.
where:
R is the feedback resistor that is connected between
o
Pin 1 and the output voltage,
Pin Protection
All the pins are ESD protected.
I
V
is the internal upper OVP current threshold,
is the Pin 1 clamp voltage.
ovpH
pin1
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12
MC33260
Pin Numbers are Relevant to the PDIP−8 Version
In particular, a 11 V Zener diode is internally connected
between the terminal and ground on the following pins:
Feedback,
Synchronization.
V
,
Oscillator, Current Sense, and
control
Sync
+
5
S1
Q1
Q1 High <=>
Synchronization Mode
−
1 V
R
sync
UVLO
R2
PWM
Latch
Set
2 ms
&
S2
R2
Q2
1 V
Output_Ctrl
Figure 31. Synchronization Arrangement
OUTPUT SECTION
SYNCHRONIZATION BLOCK
The MC33260 features two modes of operation:
• Free Running Discontinuous Mode: The power switch
is turned on as soon as there is no current left in the
inductor (Zero Current Detection). This mode is
simply obtained by grounding the synchronization
terminal (Pin 5).
The output stage contains a totem pole optimized to
minimize the cross conduction current during high speed
operation. The gate drive is kept in a sinking mode whenever
the Undervoltage Lockout is active. The rise and fall times
have been controlled to typically equal 50 ns while loaded
by 1.0 nF.
• Synchronization Mode: This mode is set as soon as a
signal crossing the 1.0 V threshold, is applied to the
Pin 5. In this case, operation in free running can only
be recovered after a new circuit startup. In this mode,
the power switch cannot turn on before the two
following conditions are fulfilled.
REFERENCE SECTION
An internal reference current source (I ) is trimmed to be
4% accurate over the temperature range (the typical value
ref
is 200 mA). I is the reference used for the regulation
ref
(I
= I ).
regH
ref
− Still, the zero current must have been detected.
− The precedent turn on must have been followed by
(at least) one synchronization raising edge
crossing the 1.0 V threshold.
UNDERVOLTAGE LOCKOUT SECTION
An Undervoltage Lockout comparator has been
implemented to guarantee that the integrated circuit is
operating only if its supply voltage (V ) is high enough to
CC
enable a proper working. The UVLO comparator monitors
the Pin 8 voltage and when it exceeds 11 V, the device gets
active. To prevent erratic operation as the threshold is
crossed, 2.5 V of hysteresis is provided.
In other words, the synchronization acts to prolong the
power switch off time.
Consequently, a proper synchronized operation requires
that the current cycle (on−time + inductor demagnetization)
is shorter than the synchronization period. Practically, the
inductor must be chosen accordingly. Otherwise, the system
will keep working in free running discontinuous mode.
Figure 36 illustrates this behavior.
It must be noticed that whatever the mode is, a 2.0 ms
minimum off−time is forced. This delay limits the switching
frequency in light load conditions.
The circuit off state consumption is very low: in the range
of 100 mA @ V = 5.0 V. This consumption varies versus
CC
V
CC
as the circuit presents a resistive load in this mode.
THERMAL SHUTDOWN
An internal thermal circuitry is provided to disable the
circuit gate drive and then to prevent it from oscillating, if
the junction temperature exceeds 150°C typically.
The output stage is again enabled when the temperature
drops below 120°C typically (30°C hysteresis).
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13
MC33260
Pin Numbers are Relevant to the PDIP−8 Version
FOLLOWER BOOST
of the follower boost: it allows the use of smaller, lighter and
cheaper inductors compared to traditional systems.
Finally, this technique utilization brings a drastic system
cost reduction by lowering the size and then the cost of both
the inductor and the power switch.
Traditional PFC preconverters provide the load with a fixed
and regulated voltage that generally equals 230 V or 400 V
according to the mains type (U.S., European, or universal).
In the “Follower Boost” operation, the preconverter
output regulation level is not fixed but varies linearly versus
the ac line amplitude at a given input power.
traditional preconverter
follower boost preconverter
Ipk
IL
Traditional Output
time
V (Follower Boost)
o
Vin
Vin
V
ac
Vin
Vout
Vin
IL
IL
Load
the power switch is off
Figure 33. Off−Time Duration Increase
the power switch is on
Figure 32. Follower Boost Characteristics
This technique aims at reducing the gap between the
output and the input voltages to minimize the boost
efficiency degradation.
Follower Boost Implementation
In the MC33260, the on−time is differently controlled
according to the feedback current level. Two areas can be
defined:
Follower Boost Benefits
• When the feedback current is higher than I
(refer
The boost presents two phases:
regL
to regulation section), the regulation block output
(V ) is modulated to force the output voltage to a
desired value.
• The on−time during which the power switch is on. The
control
inductor current grows up linearly according to a slope
(V /L ), where V is the instantaneous input voltage
in
p
in
• On the other hand, when the feedback current is lower
and L the inductor value.
p
than I
, the regulation block output and therefore,
regL
• The off−time during which the power switch is off.
the on−time are maximum. As explained in PWM
Latch Section, the on−time is then inversely
proportional to the output voltage square. The
Follower Boost is active in these conditions in which
the on−time is simply limited by the output voltage
level. Note: In this equation, the Feedback Pin voltage
The inductor current decreases linearly according the
slope (V − V )/L , where V is the output voltage.
o
in
p
o
This sequence that terminates when the current equals
zero, has a duration that is inversely proportional to the
gap between the output and input voltages.
Consequently, the off−time duration becomes longer
in follower boost.
(V ) is neglected compared to the output voltage
pin1
(refer to the PWM Latch Section).
Consequently, for a given peak inductor current, the
longer the off time, the smaller power switch duty cycle and
then its conduction dissipation. This is the first benefit of this
technique: the MOSFET on−time losses are reduced.
The increase of the off time duration also results in a
switching frequency diminution (for a given inductor
value). Given that in practise, the boost inductor is selected
big enough to limit the switching frequency down to an
acceptable level, one can immediately see the second benefit
2
C
R
o
pin3
ǒ
Ǔ
max +
t
+ t
on
on
2
K
V
osc
o
where:
C
pin3
is the total oscillator capacitor (sum of the
internal and external capacitors − C + C ),
int
T
K
osc
is the ratio (oscillator swing over oscillator gain),
V is the output voltage,
o
R is the feedback resistor.
o
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14
MC33260
Pin Numbers are Relevant to the PDIP−8 Version
On the other hand, the boost topology has its own rule that
dictates the on−time necessary to deliver the required power:
Regulation Block is Active
V = V
o pk
V
o
4 L P
p
(P )min
in
in
t
+
on
2
V
pk
P
in
where:
V
is the peak ac line voltage,
pk
(P )max
in
L is the inductor value,
p
P
in
is the input power.
non usable area
Combining the two equations, one can obtain the
Follower Boost equation:
C
R
pin3
o
Ǹ
V
+
V
o
pk
2
K
L P
V
ac
osc
p
in
Consequently, a linear dependency links the output
voltage to the ac line amplitude at a given input power.
V
acLL
V
ac
V
acHL
Figure 35. Follower Boost Output Voltage
The Regulation Block is Active
Mode Selection
(V )max
ac
The operation mode is simply selected by adjusting the
oscillator capacitor value. As shown in Figure 35, the output
voltage first has an increasing linear characteristic versus the
ac line magnitude and then is clamped down to the
regulation value. In the traditional mode, the linear area
must be rejected. This is achieved by dimensioning the
oscillator capacitor so that the boost can deliver the
maximum power while the output voltage equals its
regulation level and this, whatever the given input voltage.
Practically, that means that whatever the power and input
voltage conditions are, the follower boost would generate
output voltages values higher than the regulation level, if
there was no regulation block.
V
ac
Output Voltage
Input Power
P
in
(V )min
ac
V
o
2
t
on
= k/V
o
t
on
on−time
Figure 34. Follower Boost Characteristics
In other words, if (V )
is the low output regulation
o regL
level:
The behavior of the output voltage is depicted in
Figures 34 and 35. In particular, Figure 35 illustrates how
the output voltage converges to a stable equilibrium level.
First, at a given ac line voltage, the on−time is dictated by the
power demand. Then, the follower boost characteristic
makes correspond one output voltage level to this on−time.
Combining these two laws, it appears that the power level
forces the output voltage.
C
) C
R
o
T
int
ǒ
Ǔ
V
v
V
o
Ǹ
regL
pk
2
ǒP Ǔmax
K
L
p
osc
in
Consequently,
2
regL
ǒ
Ǔ
ǒP Ǔmax V
4 K
L
p
osc
o
in
C
w −C
)
T
int
2
2
pk
R
V
One can notice that the system is fully stable:
o
• If an output voltage increase makes it move away from
its equilibrium value, the on−time will immediately
diminish according to the follower boost law. This will
result in a delivered power decrease. Consequently,
the supplied power being too low, the output voltage
will decrease back,
Using I
(regulation block current reference), this
regL
equation can be simplified as follows:
2
regL
ǒP Ǔmax I
4 K
L
p
osc
in
C
w −C
)
T
int
2
pk
V
• In the same way, if the output voltage decreases, more
power will be transferred and then the output voltage
will increase back.
In the Follower Boost case, the oscillator capacitor must
be chosen so that the wished characteristics are obtained.
Consequently, the simple choice of the oscillator
capacitor enables the mode selection.
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15
MC33260
Synchronization
Signal
Zero Current
Detection
2 ms
Delay
2 ms
2 ms
2 ms
2 ms
V
control
Oscillator
Circuit
Output
205 mA
I
cs
Inductor
Current
1
2
3
4
case no. 1: the turn on is delayed by the Zero Current Detection
cases no. 2 and no. 3: the turn on is delayed by the synchronization signal
case no. 4: the turn on is delayed by the minimum off−time (2 ms)
Figure 36. Typical Waveforms
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16
MC33260
MAIN DESIGN EQUATIONS (Note 3)
rms Input Current (I
)
ac
η (preconverter efficiency) is generally in the
range of 90 − 95%.
P
o
I
+
ac
h V
ac
Maximum Inductor Peak Current ((I )max):
(I )max is the maximum inductor current.
pk
pk
Ǹ
2 2 (P )max
o
(I )max +
pk
h V
acLL
Output Voltage Peak to Peak 100Hz (120Hz) Ripple ((DVo)pk−pk):
f
is the ac line frequency (50 or 60Hz).
ac
P
o
(DV )
+
o
pk–pk
2p f C V
ac
o
o
t is the maximum switching period.
(t = 40 ms) for universal mains operation and
(t = 20 ms) for narrow range are generally
used.
V
Inductor Value (L ):
p
o
2
2 t
ǒ
* V
Ǔ
V
Ǹ
acLL
acLL
2
L
+
p
V V
(I ) max
pk
o
acLL
Maximum Power MOSFET Conduction Losses ((p )max):
(Rds)on is the MOSFET drain source on−time
resistor.
on
1.2 V
1
acLL
(P )max [ (Rds)on (I )max2
ƪ
1 *
ƫ
In Follower Boost, the ratio (V /V ) is
acLL o
on
pk
3
V
o
higher. The on−time MOSFET losses are then
reduced.
Maximum Average Diode Current (I ):
The Average Diode Current depends on the
power and on the output voltage.
d
(P )max
o
(I )max +
d
(V )min
o
Current Sense Resistor Losses (pR ):
This formula indicates the required dissipation
cs
capability for R (current sense resistor).
cs
1
6
pR
+
(Rds)on (I )2 max
cs
pk
Over Current Protection Resistor (R
):
OCP
The overcurrent threshold is adjusted by R
OCP
at a given R
.
R
(I ) max
cs
cs
osc
C
pk
(kW)
R
cs
can be a preconverter inrush resistor.
R
[
OCP
0.205
Oscillator External Capacitor Value (C ):
The Follower Boost characteristic is adjusted
by the C choice.
T
−Traditional Operation
2 K
L (P )max I2
T
p
in
regL
The Traditional Mode is also selected by C .
T
C
w * C
)
V2
ac
C
int
is the oscillator pin internal capacitor.
T
int
− Follower Boost:
) C
R
o
T
int
V
+
V
pk
Ǹ
o
2
K
L P
osc
p
in
Feedback Resistor (R ):
The output voltage regulation level is adjusted
by R .
o
(V )
* VFB
V
o reg
o
(MW)
o
R
+
[
o
I
200
regH
3. The preconverter design requires the following characteristics specification:
− (V ) : desired output voltage regulation level
o reg
− (DV )
: admissible output peak to peak ripple voltage
o pk−pk
− P : desired output power
o
− V : ac rms operating line voltage
ac
− V : minimum ac rms operating line voltage
acLL
− V : Feedback Pin voltage
FB
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17
MC33260
L1 320 mH
D5
MUR460E
1N4007
D1
R1
1 MW
0.25 W
80 W Load
(SMPS, Lamp
Ballast,...)
D2
D4
Q1
MTP4N50E
+
C2
47 mF
450 V
C1
330 nF
500 Vdc
90 to
EMI
D3
270 Vac
Filter
R2
1 MW
0.25 W
R4
R3
15 kW/0.25 W
1 W/2 W
R5
22 W/0.25 W
V
ref
I
ref
I
o
I
ref
MC33260
I
o
Feedback
Block
11 V/8.5 V
I
I
ref
−
+
o
REGULATOR
Enable
UVP, OVP
Feedback
Input
V
V
prot
CC
V
reg
Regulation
Block
1.5 V
V
V
reg
control
I
o
V
prot
(− − −)
C3
680 nF
I
o
300 k
I
I
I
uvp
ovpL ovpH
ThStdwn
Drive
Gnd
Output
Buffer
97%.I
I
ref
ref
PWM Comp
Oscillator
+
−
R
S
Q
Q
2x|0x|0
I
+
PWM
Latch
osc–ch
I
ref
Current
Sense
Block
Output
I
(205 mA)
ocp
CT
C4
330 pF
0
1
1
0
−60 mV
+
Synchro
15 pF
Synchronization
Block
−
LEB
Output
L1: Coilcraft N2881 − A (primary: 62 turns of # 22 AWG − Secondary: 5 turns of # 22 AWG Core: Coilcraft PT2510, EE 25
L1: Gap: 0.072″ total for a primary inductance (Lp) of 320 mH)
Figure 37. 80 W Wide Mains Power Factor Corrector
POWER FACTOR CONTROLLER TEST DATA*
AC Line Input
Current Harmonic Distortion (% I
)
DC Output
fund
V
(V)
P
(W)
PF
(−)
I
V
(V)
DV
(V)
I
P
o
(W)
η
(%)
rms
in
fund
o
o
o
(mA)
(mA)
THD
H2
H3
H5
H7
H9
90
88.2
86.3
85.2
87.0
84.7
85.3
84.0
0.991
0.996
0.995
0.994
0.982
0.975
0.967
990
782
642
480
385
359
330
8.1
7.0
0.07
0.05
0.03
0.16
0.5
5.9
2.7
1.5
4.0
8.4
9.0
11.0
4.3
5.7
6.8
6.5
7.8
7.8
7.0
1.5
1.1
1.1
3.1
5.3
7.4
9.0
1.7
0.8
1.5
4.0
1.9
3.8
4.0
181
222
265
360
379
384
392
31.2
26.4
20.8
16.0
14.0
14.0
13.2
440
360
300
225
210
210
205
79.6
79.9
79.5
81.0
79.6
80.6
80.4
90.2
92.6
93.3
93.1
94.4
94.5
95.7
110
135
180
220
240
260
8.2
9.5
15
16.5
18.8
0.7
0.7
*Measurements performed using Voltech PM1200 ac power analysis.
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18
MC33260
R
stup
r
D1...D4
+
15 V
C
pin8
V
CC
+
1
2
3
4
8
7
6
5
PDIP−8 CONFIGURATION SHOWN
Figure 38. Circuit Supply Voltage
MC33260 VCC SUPPLY VOLTAGE
When the PFC preconverter is loaded by an SMPS, the
MC33260 should preferably be supplied by the SMPS itself.
In this configuration, the SMPS starts first and the PFC gets
In some applications, the arrangement shown in Figure 38
must be implemented to supply the circuit. A startup resistor
is connected between the rectified voltage (or one−half
active when the MC33260 V
supplied by the power
CC
wave) to charge the MC33260 V
up to its startup
supply, exceeds the device startup level. With this
configuration, the PFC preconverter doesn’t require any
auxiliary winding and finally a simple coil can be used.
CC
threshold (11 V typically). The MC33260 turns on and the
capacitor (C ) starts to be charged by the PFC
V
CC
pin8
transformer auxiliary winding. A resistor, r (in the range of
22 W) and a 15 V Zener should be added to protect the circuit
from excessive voltages.
PCB LAYOUT
The connections of the oscillator and V
should be as short as possible.
capacitors
control
Preconverter Output
+
+
+
V
+
CC
1
2
3
4
8
7
6
5
+
+
+
SMPS Driver
DIP−8 CONFIGURATION SHOWN
Figure 39. Preconverter Loaded by a Flyback SMPS: MC33260 VCC Supply
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19
MC33260
ORDERING INFORMATION
Device
†
Package
Shipping
MC33260P
PDIP−8
50 Units / Rail
50 Units / Rail
MC33260PG
PDIP−8
(Pb−Free)
MC33260D
SOIC−8
98 Units / Rail
98 Units / Rail
MC33260DG
SOIC−8
(Pb−Free)
MC33260DR2
SOIC−8
2500 Units / Tape & Reel
2500 Units / Tape & Reel
MC33260DR2G
SOIC−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
PACKAGE DIMENSIONS
PDIP−8
P SUFFIX
PLASTIC PACKAGE
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
8
5
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−B−
MILLIMETERS
DIM MIN MAX
INCHES
MIN
1
4
MAX
0.400
0.260
0.175
0.020
0.070
A
B
C
D
F
9.40
6.10
3.94
0.38
1.02
10.16 0.370
6.60 0.240
4.45 0.155
0.51 0.015
1.78 0.040
F
−A−
NOTE 2
L
G
H
J
2.54 BSC
0.100 BSC
0.76
0.20
2.92
1.27 0.030
0.30 0.008
3.43
0.050
0.012
0.135
K
L
0.115
C
7.62 BSC
0.300 BSC
M
N
−−−
0.76
10
−−−
10
_
_
1.01 0.030
0.040
J
−T−
SEATING
PLANE
N
M
D
K
G
H
M
M
M
0.13 (0.005)
T
A
B
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20
MC33260
PACKAGE DIMENSIONS
SOIC−8
CASE 751−07
ISSUE AG
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
0.25 (0.010)
Z
Y
X
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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21
MC33260
The product described herein (MC33260), may be covered by one or more of the following U.S. patents: 5,073,850; 6,177,782.
There may be other patents pending.
GreenLine is a trademark of Motorola, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
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Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
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Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
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