MC33260 [ONSEMI]
GreenLine Compact Power Factor Controller:Innovative Circuit for Cost Effective Solutions; 绿线紧凑型功率因数控制器：创新电路的成本效益解决方案
| 型号： | MC33260 |
| 厂家： | 
ONSEMI |
| 描述： | GreenLine Compact Power Factor Controller:Innovative Circuit for Cost Effective Solutions |
| 文件： | 总21页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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The MC33260 is a controller for Power Factor Correction
preconverters meeting international standard requirements in
electronic ballast and off–line power conversion applications.
Designed to drive a free frequency discontinuous mode, it can also be
synchronized and in any case, it features very effective protections that
ensure a safe and reliable operation.
This circuit is also optimized to offer extremely compact and cost
effective PFC solutions. While it requires a minimum number of
external components, the MC33260 can control the follower boost
operation that is an innovative mode allowing a drastic size reduction
of both the inductor and the power switch. Ultimately, the solution
system cost is significantly lowered.
8
1
DIP–8
P SUFFIX
CASE 626
Also able to function in a traditional way (constant output voltage
regulation level), any intermediary solutions can be easily
implemented. This flexibility makes it ideal to optimally cope with a
wide range of applications.
PIN CONNECTIONS AND
MARKING DIAGRAM
General Features
Feedback Input
1
2
3
4
8
7
6
5
V
CC
• Standard Constant Output Voltage or “Follower Boost” Mode
• Switch Mode Operation: Voltage Mode
• Latching PWM for Cycle–by–Cycle On–Time Control
• Constant On–Time Operation That Saves the Use of an Extra Multiplier
• Totem Pole Output Gate Drive
• Undervoltage Lockout with Hysteresis
• Low Start–Up and Operating Current
• Improved Regulation Block Dynamic Behavior
• Synchronization Capability
V
control
Gate Drive
Gnd
Oscillator
Capacitor (C )
T
Current Sense
Input
Synchronization
Input
AWL = Manufacturing Code
YYWW = Date Code
(Top View)
• Internally Trimmed Reference Current Source
ORDERING INFORMATION
Safety Features
Device
MC33260P
Package
Shipping
50 Units / Rail
• Overvoltage Protection: Output Overvoltage Detection
• Undervoltage Protection: Protection Against Open Loop
• Effective Zero Current Detection
Plastic DIP–8
• Accurate and Adjustable Maximum On–Time Limitation
• Overcurrent Protection
• ESD Protection on Each Pin
TYPICAL APPLICATION
Filtering
Capacitor
D1...D4
L1
D1
C1
+
V
LOAD
(SMPS, Lamp
Ballast,...)
CC
1
2
3
4
8
7
6
5
M1
V
control
R
o
Sync
CT
R
OCP
R
cs
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
November, 1999 – Rev. 1
MC33260/D
MC33260
BLOCK DIAGRAM
V
o
Current Mirror
I
o
2 x I x I
FB
O
O
I
– ch =
OSC
I
o
I
ref
1
Current
Mirror
I
o
I
o
I
ref
CT
3
V
ref
11 V
1.5 V
1
0
15 pF
300 k
V
reg
V
control
I
o
2
97%I
I
ref
ref
Output_Ctrl
I
/I
11 V
ovpH ovpL
V
ref
REGULATOR
Enable
+
–
I
ref
OVP
UVP
r
I
r
uvp
–
11 V/8.5 V
+
–
+
I
cs
(205 A)
Synchro
r
–60 mV
5
1
0
11 V
+
–
Current
Sense
Synchro
Arrangement
4
LEB
V
CC
11 V
Output_Ctrl
8
ThStdwn
Drive
7
Gnd
S
6
R
R
R
Q
PWM
Latch
+
–
Output_Ctrl
Q
PWM Comparator
MC33260
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2
MC33260
MAXIMUM RATINGS
Rating
Pin #
Symbol
Value
Unit
Gate Drive Current (Pin 7)*
7
mA
Source
Sink
I
–500
500
O(Source)
O(Sink)
I
V
(Pin 8) Maximum Voltage
8
(Vcc)
16
V
V
CC
max
Input Voltage
V
in
–0.3 to +10
Power Dissipation and Thermal Characteristics
P Suffix, DIP Package
Maximum Power Dissipation @ T = 85°C
Thermal Resistance Junction to Air
P
600
100
mW
°C/W
A
D
R
θJA
Operating Junction Temperature
T
150
°C
°C
J
Operating Ambient Temperature
T
A
–40 to +105
*The maximum package power dissipation must be observed.
ELECTRICAL CHARACTERISTICS (V
= 13 V, T = 25°C for typical values, T = –40 to 105°C for min/max values
J J
CC
unless otherwise noted.)
Characteristic
Pin #
Symbol
Min
Typ
Max
Unit
GATE DRIVE SECTION
Gate Drive Resistor
7
Ω
Source Resistor @ I
= 100 mA
= 100 mA
R
R
OH
10
5
20
10
35
25
pin7
OL
Sink Resistor @ I
pin7
Gate Drive Voltage Rise Time (From 3 V Up to 9 V)
(Note 1)
7
7
t
—
—
50
50
—
—
ns
ns
r
Output Voltage Falling Time (From 9 V Down to 3 V)
(Note 1)
t
f
OSCILLATOR SECTION
Maximum Oscillator Swing
3
3
3
∆V
1.4
87.5
350
1.5
100
400
1.6
112.5
450
V
T
Charge Current @ I
= 100 µA
= 200 µA
I
I
µA
µA
pin1
pin1
charge
charge
Charge Current @ I
Ratio Multiplier Gain Over Maximum Swing
@ I =100 µA
3
K
5600
6400
7200
1/(V.A)
osc
osc
pin1
Ratio Multiplier Gain Over Maximum Swing
@ I =200 µA
3
3
K
5600
10
6400
15
7200
20
1/(V.A)
pF
pin1
Average Internal Pin 3 Capacitance Over Oscillator
C
int
Maximum Swing (V
(Note 2)
Varying From 0 Up to 1.5 V)
pin3
Discharge Time (C = 1 nF)
T
3
T
disch
—
0.5
1
µs
REGULATION SECTION
Regulation High Current Reference
Ratio (Regulation Low Current Reference)/I
Pin 2 Impedance
1
1
1
1
1
I
192
0.965
—
200
0.97
300
2.1
208
0.98
—
µA
—
kΩ
V
reg–H
I
/I
reg–H
reg–L reg–H
Z
pin3
Pin 1 Clamp Voltage @ I
= 100 µA
= 200 µA
V
V
1.5
2
2.5
3
pin1
pin1
pin1–100
pin1–200
Pin 1 Clamp Voltage @ I
2.6
V
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3
MC33260
ELECTRICAL CHARACTERISTICS (V
= 13 V, T = 25°C for typical values, T = –40 to 105°C for min/max values
J J
CC
unless otherwise noted.)
Characteristic
Pin #
Symbol
Min
Typ
Max
Unit
CURRENT SENSE SECTION
Zero Current Detection Comparator Threshold
Negative Clamp Level (I = –1 mA)
4
4
4
7
4
V
–90
—
–60
–0.7
—
–30
—
mV
V
ZCD–th
Cl–neg
pin2
Bias Current @ V
= V
I
b–cs
–0.2
—
—
µA
ns
µA
ns
ns
pin4
ZCD–th
> V
Propagation Delay (V
) to Gate Drive High
ZCD–th
T
ZCD
500
205
400
160
—
pin4
Pin 4 Internal Current Source
Leading Edge Blanking Duration
OverCurrent Protection Propagation Delay
I
192
—
218
—
OCP
τ
LEB
7
T
OCP
100
240
(Pin 4 < V to Gate Drive Low)
ZCD–th
SYNCHRONIZATION SECTION
Synchronization Threshold
5
5
7
5
V
0.8
—
1
1.2
—
V
V
sync–th
Negative Clamp Level (I
Minimum Off–Time
= –1 mA)
Cl–neg
–0.7
2.1
—
pin5
T
off
1.5
—
2.7
0.5
µs
µs
Minimum Required Synchronization Pulse Duration
OVERVOLTAGE PROTECTION SECTION
T
sync
OverVoltage Protection High Current Threshold
1
1
I
–I
8
0
13
—
18
—
µA
OVP–H reg–H
and I
Difference
reg–H
OverVoltage Protection Low Current Threshold
I
–I
—
OVP–L reg–H
and I
Difference
reg–H
Ratio (I
/I
)
1
7
I
/I
1.02
—
—
—
—
—
ns
OVP–H OVP–L
OVP–H OVP–L
Propagation Delay (I
> 110% I to Gate Drive Low)
ref
T
500
pin1
OVP
UNDERVOLTAGE PROTECTION SECTION
Ratio (UnderVoltage Protection Current Threshold)/I
1
7
I
/I
12
—
14
16
—
%
reg–H
UVP reg–H
Propagation Delay (I
pin1
< 12% I to Gate Drive Low)
ref
T
500
ns
UVP
THERMAL SHUTDOWN SECTION
Thermal Shutdown Threshold
Hysteresis
7
7
T
—
—
150
30
—
—
°C
°C
stdwn
∆T
stdwn
V
CC
UNDERVOLTAGE LOCKOUT SECTION
Start–Up Threshold
8
8
V
9.7
7.4
11
12.3
9.6
V
V
stup–th
Disable Voltage After Threshold Turn–On
V
8.5
disable
TOTAL DEVICE
Power Supply Current
8
I
mA
CC
Start–Up (V
= 5 V with V
CC
Increasing)
—
—
0.1
4
0.25
8
CC
Operating @ I
pin1
= 200 µA
NOTES:
(1) 1 nF being connected between the pin 7 and ground.
(2) Guaranteed by design.
(3) No load is connected to the gate drive which is kept high during the test.
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4
MC33260
1.6
1.4
1.2
1.0
0.8
0.6
0.4
1.6
–40°C
25°C
1.4
1.2
1.0
0.8
0.6
0.4
105°C
–40°C
25°C
105°C
0.2
0
0.2
0
0
20 40 60 80 100 120 140 160 180 200 220 240
185
190
195
200
205
210
I
: FEEDBACK CURRENT (µA)
I : FEEDBACK CURRENT (µA)
pin1
pin1
Figure 1. Regulation Block Output versus
Feedback Current
Figure 2. Regulation Block Output versus
Feedback Current
1.340
1.335
1.330
1.325
1.320
1.315
1.310
3.5
3.0
2.5
2.0
1.5
1.0
–40°C
25°C
0.5
0
1.305
1.300
105°C
–40
–20
0
20
40
60
80
100
0
20 40 60 80 100 120 140 160 180 200 220 240
: FEEDBACK CURRENT (µA)
JUNCTION TEMPERATURE (°C)
I
pin1
Figure 3. Maximum Oscillator Swing versus
Temperature
Figure 4. Feedback Input Voltage versus
Feedback Current
500
450
400
350
410
405
400
395
–40°C
25°C
I
= 200 A
pin1
105°C
300
250
200
150
100
390
385
50
0
0
20 40 60 80 100 120 140 160 180 200 220 240
: FEEDBACK CURRENT (µA)
–40
–20
0
20
40
60
80
100
I
JUNCTION TEMPERATURE (°C)
pin1
Figure 5. Oscillator Charge Current versus
Feedback Current
Figure 6. Oscillator Charge Current versus
Temperature
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5
MC33260
104
103
102
101
100
99
120
–40°C
25°C
I
= 100 A
pin1
100
80
105°C
1 nF Connected to Pin 3
60
40
20
0
98
97
–40
–20
0
20
40
60
80
100
30 50
70
90
110 130 150 170 190 210
T , JUNCTION TEMPERATURE (°C)
J
I
: FEEDBACK CURRENT ( A)
pin1
Figure 7. Oscillator Charge Current versus
Temperature
Figure 8. On–Time versus Feedback Current
75
65
55
45
35
207
206
205
204
203
202
201
200
199
I
OCP
–40°C
25°C
105°C
1 nF Connected to Pin 3
I
regH
25
15
198
197
–40
50
60
70
80
90
100
–20
0
20
40
60
80
100
I
: FEEDBACK CURRENT (µA)
T , JUNCTION TEMPERATURE (°C)
J
pin1
Figure 9. On–Time versus Feedback Current
Figure 10. Internal Current Sources versus
Temperature
1.07
1.06
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.150
0.148
0.146
0.144
0.142
(I /I )
ovpH ref
(I /I )
ovpL ref
0.140
0.138
0.136
0.134
(I
/I
)
regL ref
0.97
0.96
0.132
0.130
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. (I
/I ), (I
/I ), (I
/I
)
Figure 12. Undervoltage Ratio versus
Temperature
ovpH ref ovpL ref regL ref
versus Temperature
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MC33260
–54.8
–55
4.5
–40°C
25°C
4.0
3.5
3.0
2.5
2.0
1.5
1.0
–55.2
–55.4
–55.6
–55.8
–56
105°C
–56.2
–56.4
–56.6
0.5
0
–40
–20
0
20
40
60
80
100
0
2
4
6
8
10
12
14
16
T , JUNCTION TEMPERATURE (°C)
J
V : SUPPLY VOLTAGE (V)
CC
Figure 14. Circuit Consumption versus
Supply Voltage
Figure 13. Current Sense Threshold versus
Temperature
Vgate
20
15
10
–40°C
25°C
25°C
1
V
C
= 12 V
CC
= 1 nF
gate
I
(50 mA/div)
cross–cond
105°C
5
0
2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Ch1 10.0 V Ch2 10.0 mV
M 1.00
s
Ch1
600 mV
V : PIN 2 VOLTAGE (V)
control
Figure 15. Oscillator Pin Internal Capacitance
Figure 16. Gate Drive Cross Conduction
Vgate
Vgate
–40°C
105°C
1
1
V
= 12 V
= 1 nF
V
= 12 V
= 1 nF
CC
CC
C
gate
C
gate
I
(50 mA/div)
I
(50 mA/div)
cross–cond
cross–cond
2
2
Ch1 10.0 V Ch2 10.0 mV
M 1.00
s
Ch1
600 mV
Ch1 10.0 V Ch2 10.0 mV
M 1.00
s
Ch1
600 mV
Figure 17. Gate Drive Cross Conduction
Figure 18. Gate Drive Cross Conduction
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MC33260
PIN FUNCTION DESCRIPTION
Pin No.
Function
Description
1
Feedback Input
This pin is designed to receive a current that is proportional to the preconverter output voltage. This
information is used for both the regulation and the overvoltage and undervoltage protections. The
current drawn by this pin is internally squared to be used as oscillator capacitor charge current.
2
V
This pin makes available the regulation block output. The capacitor connected between this pin and
ground, adjusts the control bandwidth. It is typically set below 20 Hz to obtain a nondistorted input
current.
control
3
4
Oscillator Capacitor The circuit uses an on–time control mode. This on–time is controlled by comparing the C voltage to
T
(C )
the V
voltage. C is charged by the squared feedback current.
T
control T
Zero Current
Detection Input
This pin is designed to receive a negative voltage signal proportional to the current flowing through
the inductor. This information is generally built using a sense resistor. The Zero Current Detection
prevents any restart as long as the pin 4 voltage is below (–60 mV). This pin is also used to perform
the peak current limitation. The overcurrent threshold is programmed by the resistor connected
between the pin and the external current sense resistor.
5
Synchronization
Input
This pin is designed to receive a synchronization signal. For instance, it enables to synchronize the
PFC preconverter to the associated SMPS. If not used, this pin must be grounded.
6
7
8
Ground
This pin must be connected to the preregulator ground.
Gate Drive
The gate drive current capability is suited to drive an IGBT or a power MOSFET.
V
CC
This pin is the positive supply of the IC. The circuit turns on when V
operating range after start–up being 8.5 V up to 16 V.
becomes higher than 11 V, the
CC
APPLICATION SCHEMATIC
Filtering
Capacitor
L1
D1...D4
D1
C1
+
Load
(SMPS, Lamp
Ballast,...)
V
CC
1
2
3
4
8
7
6
5
M1
R
o
V
control
Sync
R
OCP
CT
R
cs
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8
MC33260
FUNCTIONAL DESCRIPTION
INTRODUCTION
OPERATION DESCRIPTION
The need of meeting the requirements of legislation on
line current harmonic content, results in an increasing
demand for cost effective solutions to comply with the
Power Factor regulations. This data sheet describes a
monolithic controller specially designed for this purpose.
Most off–line appliances use a bridge rectifier associated
to a huge bulk capacitor to derive raw dc voltage from the
utility ac line.
The MC33260 is optimized to just as well drive a free
running as a synchronized discontinuous voltage mode.
It also features valuable protections (overvoltage and
undervoltage protection, overcurrent limitation, ...) that
make the PFC preregulator very safe and reliable while
requiring very few external components. In particular, it is
able to safely face any uncontrolled direct charges of the
output capacitor from the mains which occur when the
output voltage is lower than the input voltage (start–up,
overload, ...).
In addition to the low count of elements, the circuit can
control an innovative mode named “Follower Boost” that
permits to significantly reduce the size of the preconverter
inductor and power MOSFET. With this technique, the
output regulation level is not forced to a constant value, but
can vary according to the a.c. line amplitude and to the
power. The gap between the output voltage and the ac line
is then lowered, what allows the preconverter inductor and
power MOSFET size reduction. Finally, this method brings
a significant cost reduction.
Rectifiers
Converter
AC
Line
+
Bulk
Load
Storage
Capacitor
Figure 19. Typical Circuit Without PFC
This technique results in a high harmonic content and in
poor power factor ratios. In effect, the simple rectification
technique draws power from the mains when the
instantaneousac voltage exceeds the capacitor voltage. This
occurs near the line voltage peak and results in a high charge
current spike. Consequently, a poor power factor (in the
rangeof0.5–0.7)isgenerated, resultinginanapparentinput
power that is much higher than the real power.
A description of the functional blocks is given below.
REGULATION SECTION
Connecting a resistor between the output voltage to be
regulated and the pin 1, a feedback current is obtained.
Typically, this current is built by connecting a resistor
between the output voltage and the pin 1. Its value is then
given by the following equation:
V
pk
Rectified DC
V
V
0
0
o
pin1
I
Line Sag
pin1
R
o
where:
R is the feedback resistor,
AC Line Voltage
AC Line Current
o
o
V is the output voltage,
V
pin1
is the pin 1 clamp value.
The feedback current is compared to the reference current
so that the regulation block outputs a signal following the
characteristic depicted in Figure 22. According to the power
and the input voltage, the output voltage regulation level
Figure 20. Line Waveforms Without PFC
varies between two values (V )
and (V )
o regL
o regH
Active solutions are the most popular way to meet the
legislation requirements. They consist of inserting a PFC
pre–regulator between the rectifier bridge and the bulk
capacitor. This interface is, in fact, a step–up SMPS that
outputs a constant voltage while drawing a sinusoidal
current from the line.
corresponding to the I
regL
and I
levels.
regH
Regulation Block Output
1.5 V
Rectifiers
PFC Preconverter
Converter
AC
Line
+
I
o
I
I
reg–L
(97%I
reg–H
(I
)
)
ref
ref
Figure 22. Regulation Characteristic
Figure 21. PFC Preconverter
The feedback resistor must be chosen so that the feedback
current should equal the internal current source I when
TheMC33260wasdevelopedtocontrolanactivesolution
with the goal of increasing its robustness while lowering its
global cost.
regH
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9
MC33260
2
the output voltage exceeds the chosen upper regulation
2
V
V
voltage [(V )
]. Consequently:
o regH
o
pin1
I
V
V
charge
2
o
R
I
regH
pin1
o
ref
R
o
I
where:
V is the output voltage,
regH
o
o
In practice, V
equation can be simplified as follows (I
replaced by its typical value 200 µA):
is small compared to (V )
and this
pin1
o regH
being also
R is the feedback resistor,
regH
V
pin1
is the pin 1 clamp voltage.
Inpractice, V
thatisintherangeof2.5V, isverysmall
compared to V . The equation can then be simplified by
pin1
< >
k
R
5
V
o
o
regH
o
neglecting V
:
pin1
The regulation block output is connected to the pin 2
through a 300 kΩ resistor. The pin 2 voltage (V ) is
2
2
V
I
o
control
compared to the oscillator sawtooth for PWM control.
I
charge
2
R
o
ref
An external capacitor must be connected between pin 2
and ground, for external loop compensation. The bandwidth
is typically set below 20 Hz so that the regulation block
output should be relatively constant over a given ac line
cycle.Thisintegrationthatresultsinaconstanton–timeover
the ac line period, prevents the mains frequency output
ripple from distorting the ac line current.
It must be noticed that the oscillator terminal (pin 3) has
an internal capacitance (C ) that varies versus the pin 3
voltage. Over the oscillator swing, its average value
typically equals 15 pF (min 10 pF, max 20 pF).
Thetotaloscillatorcapacitoristhenthesumoftheinternal
and external capacitors.
int
C
C
C
pin3
T
int
OSCILLATOR SECTION
The oscillator consists of three phases:
• Charge Phase: The oscillator capacitor voltage grows
up linearly from its bottom value (ground) until it
PWM LATCH SECTION
The MC33260 operates in voltage mode: the regulation
block output (V – pin 2 voltage) is compared to the
control
oscillator sawtooth so that the gate drive signal (pin 7) is
high until the oscillator ramp exceeds V
exceedsV
(regulationblockoutputvoltage).At
control
that moment, the PWM latch output gets low and the
oscillator discharge sequence is set.
.
control
The on–time is then given by the following equation:
• Discharge Phase: The oscillator capacitor is abruptly
discharged down to its valley value (0 V).
• Waiting Phase: At the end of the discharge sequence,
the oscillator voltage is maintained in a low state until
the PWM latch is set again.
C
V
pin3
control
t
on
I
ch
where:
is the on–time,
t
C
on
is the total oscillator capacitor (sum of the
pin3
internal and external capacitor),
is the oscillator charge current (pin 3 current),
I
= 2
I
o
I / I
o ref
charge
I
V
charge
control
is the pin 2 voltage (regulation block output).
1
0
Output_Ctrl
0
Consequently,replacingI
the Oscillator Section:
bytheexpressiongivenin
charge
CT
3
2
R
I
C
V
o
ref
pin3
2
V
control
t
1
on
2
o
15 pF
One can notice that the on–time depends on V
o
(preconverter output voltage) and that the on–time is
maximum when Vcontrol is maximum (1.5 V typically).
Figure 23. Oscillator
At a given V , the maximum on–time is then expressed by
the following equation:
o
Theoscillatorchargecurrentisdependentonthefeedback
current (I ). In effect
2
o
C
R
I
V
o
pin3
ref
control
max
2
I
t
max
o
on
2
V
I
2
2
charge
o
I
ref
This equation can be simplified replacing
where:
I
is the oscillator charge current,
2 / [(V
l)
* I ] by K
osc
charge
contro max ref
I is the feedback current (drawn by pin 1),
o
ref
Refer to Electrical Characteristics, Oscillator Section.
I
is the internal reference current (200 µA).
Then:
So, the oscillator charge current is linked to the output
voltage level as follows:
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10
MC33260
Zero Current Detection
2
R
C
o
pin3
The Zero Current Detection function guarantees that the
MOSFET cannot turn on as long as the inductor current
hasn’t reached zero (discontinuous mode).
The pin 4 voltage is simply compared to the (–60 mV)
threshold so that as long as V is lower than this threshold,
the circuit gate drive signal is kept in low state.
Consequently, no power MOSFET turn on is possible until
t
max
on
2
V
K
osc
o
This equation shows that the maximum on–time is
inversely proportional to the squared output voltage. This
property is used for follower boost operation (refer to
Follower Boost section).
cs
theinductorcurrentismeasuredassmallerthan(60mV/R )
that is, the inductor current nearly equals zero.
CURRENT SENSE BLOCK
The inductor current is converted into a voltage by
cs
insertingagroundreferencedresistor(R )inserieswiththe
cs
input diodes bridge (and the input filtering capacitor).
Therefore a negative voltage proportional to the inductor
current is built:
I
(205 A)
ocp
Output_Ctrl
–60 mV
D1...D4
S
PWM
Latch
V
R
I
1
0
cs
cs
L
Output_Ctrl
R
Q
+
–
where:
I is the inductor current,
R
OCP
R
L
4
LEB
R
is the current sense resistor,
cs
V
OCP
R
cs
V
cs
is the measured R voltage.
cs
To Output Buffer
(Output_Ctrl Low <=> Gate Drive in Low State)
Figure 25. Current Sense Block
Overcurrent Protection
Time
During the power switch conduction (i.e. when the Gate
Drive pin voltage is high), a current source is applied to the
pin 4. A voltage drop V
resistor R
OCP
is then generated across the
that is connected between the sense resistor
OCP
and the Current Sense pin (refer to Figure 25). So, instead of
V ,thesum(V +V )iscomparedto(–60mV)andthe
cs cs OCP
maximum permissible current is the solution of the
following equation:
R
Ipk
V
60 mV
cs
max
OCP
where:
Ipk
is maximum allowed current,
max
is the sensing resistor.
V
OCP
R
cs
The overcurrent threshold is then:
3
R
I
60 10
OCP
OCP
R
Ipk
max
–60 mV
Zero Current Detection
cs
where:
R
is the resistor connected between the pin and the
OCP
sensing resistor (R ),
cs
V
= R
OCP
pin4
I
OCP
OCP
I
is the current supplied by the Current Sense pin
when the gate drive signal is high (power switch
OCP
An overcurrent is detected if V
crosses the threshold (–60 mV)
during the Power Switch on state
conduction phase). I
equals 205 µA typically.
OCP
Figure 24. Current Sensing
Practically, the V
OCP
offset is high compared to 60 mV
and theprecedentequationcanbesimplified. Themaximum
current is then given by the following equation:
The negative signal V is applied to the current sense
cs
through a resistor R . The pin is internally protected by a
OCP
negative clamp (–0.7 V) that prevents substrate injection.
As long as the pin 4 voltage is lower than (–60 mV), the
Current Sense comparator resets the PWM latch to force the
gate drive signal low state. In that condition, the power
MOSFET cannot be on.
During the on–time, the pin 4 information is used for the
overcurrent limitation while it serves the zero current
detection during the off time.
<
>
k
R
OCP
< >
< >
A
Ipk
0.205
max
R
cs
Consequently, the R
resistor can program the OCP
level whatever the R value is. This gives a high freedom in
the choice of R . In particular, the inrush resistor can be
cs
OCP
cs
utilized.
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11
MC33260
V
CC
Th–Stdwn
Synchronization
Arrangement
S
Output
Buffer
5
7
Q
Q
OVP, UVP
Current Sense
Comparator
PWM
Latch
–
ZCD & OCP
R
+
&
Output_Ctrl
–60 mV
PWM Latch
Comparator
+
–
V
(V
– Regulation Output)
control pin2
Oscillator Sawtooth
Figure 26. PWM Latch
A LEB (Leading Edge Blanking) has been implemented.
This circuitry disconnects the Current Sense comparator
from pin 4 and disables it during the 400 first ns of the power
switch conduction. This prevents the block from reacting on
the current spikes that generally occur at power switch turn
on. Consequently, proper operation does not require any
filtering capacitor on pin 4.
Practically, V
that is in the range of 2.5 V, can be
neglected. The equation can then be simplified:
pin1
<
>
<
> < >
A V
V
R
M
I
o
ovpH
ovpH
On the other hand, the OVP low threshold is:
V
V
R
I
o
ovpL
pin1
ovpL
where I
Consequently, V
is the internal low OVP current threshold.
ovp–L
PROTECTIONS
being neglected:
pin1
OCP (Overcurrent Protection)
Refer to Current Sense Block.
<
>
<
> < >
A V
V
R
M
I
o
ovpL
ovpL
The OVP hysteresis prevents erratic behavior.
is guaranteed to be higher than IregH (refer to
OVP (Overvoltage Protection)
The feedback current (I ) is compared to a threshold
I
ovpL
parameters specification). This ensures that the OVP
function doesn’t interfere with the regulation one.
o
current (I
). If it exceeds this value, the gate drive signal
ovpH
is maintained low until this current gets lower than a second
level (I ).
UVP (Undervoltage Protection)
This function detects when the feedback current is lower
ovpL
than 14% of I . In this case, the PWM latch is reset and the
power switch is kept off.
This protection is useful to:
• Protect the preregulator from working in too low
mains conditions.
• To detect the feedback current absence (in case of a
nonproper connection for instance).
The UVP threshold is:
ref
Gate
Drive
Enable
V
control
I
o
<
>
<
>
( )
A
V
V
R
M
I
V
I
I
I I I
uvp
o
uvp
uvp
regL regH ovpL ovpH
pin1
Figure 27. Internal Current Thresholds
Practically (V
being neglected),
pin1
<
>
<
> < >
A V
V
R
M
I
uvp
o
uvp
So, the OVP upper threshold is:
Maximum On–Time Limitation
As explained in PWM Latch, the maximum on–time is
V
V
R
I
o
ovpH
pin1
ovpH
where:
accurately controlled.
R is the feedback resistor that is connected between
o
Pin Protection
All the pins are ESD protected.
pin 1 and the output voltage,
is the internal upper OVP current threshold,
is the pin 1 clamp voltage.
I
V
ovp–H
pin1
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12
MC33260
In particular, a 11 V zener diode is internally connected
between the terminal and ground on the following pins:
Feedback, V
Synchronization.
, Oscillator, Current Sense, and
control
Sync
+
5
S1
Q1
Q1 High <=>
Synchronization Mode
–
1 V
R
sync
UVLO
R2
PWM
Latch
Set
2
s
&
S2
R2
Q2
1 V
Output_Ctrl
Figure 28. Synchronization Arrangement
SYNCHRONIZATION BLOCK
have been controlled to typically equal 50 ns while loaded
by 1 nF.
The MC33260 features two modes of operation:
• Free RunningDiscontinuousMode: The powerswitch
is turned on as soon as there is no current left in the
inductor (Zero Current Detection). This mode is
simply obtained by grounding the synchronization
terminal (pin 5).
• Synchronization Mode: This mode is set as soon as a
signal crossing the 1 V threshold, is applied to the pin
5. In this case, operation in free running can only be
recoveredafteranewcircuitstart–up. Inthismode, the
power switch cannot turn on before the two following
conditions are fulfilled.
REFERENCE SECTION
Aninternalreferencecurrentsource(I )istrimmedtobe
ref
±4% accurate over the temperature range (the typical value
is 200 µA).I isthereferenceusedfortheregulation(I
ref
regH
= I ).
ref
UNDERVOLTAGE LOCKOUT SECTION
An Undervoltage Lockout comparator has been
implemented to guarantee that the integrated circuit is
operating only if its supply voltage (V ) is high enough to
CC
enable a proper working. The UVLO comparator monitors
the pin 8 voltage and when it exceeds 11 V, the device gets
active. To prevent erratic operation as the threshold is
crossed, 2.5 V of hysteresis is provided.
— Still, the zero current must have been detected.
— The precedent turn on must have been followed by
(at least) one synchronization raising edge
crossing the 1 V threshold.
The circuit off state consumption is very low: in the range
of 100 µA @ V
= 5 V. This consumption varies versus
In other words, the synchronization acts to prolong the
power switch off time.
CC
as the circuit presents a resistive load in this mode.
V
CC
Consequently, a proper synchronized operation requires
that the current cycle (on–time + inductor demagnetization)
is shorter than the synchronization period. Practically, the
inductor must be chosen accordingly. Otherwise, the system
will keep working in free running discontinuous mode.
Figure 33 illustrates this behavior.
It must be noticed that whatever the mode is, a 2 µs
minimum off–time is forced. This delay limits the switching
frequency in light load conditions.
THERMAL SHUTDOWN
An internal thermal circuitry is provided to disable the
circuit gate drive and then to prevent it from oscillating, if
the junction temperature exceeds 150°C typically.
The output stage is again enabled when the temperature
drops below 120°C typically (30°C hysteresis).
FOLLOWER BOOST
Traditional PFC preconverters provide the load with a fixed
and regulated voltage that generally equals 230 V or 400 V
according to the mains type (U.S., European, or universal).
In the “Follower Boost” operation, the preconverter
output regulation level is not fixed but varies linearly versus
the ac line amplitude at a given input power.
OUTPUT SECTION
The output stage contains a totem pole optimized to
minimize the cross conduction current during high speed
operation. Thegatedriveiskeptinasinkingmodewhenever
the Undervoltage Lockout is active. The rise and fall times
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13
MC33260
traditional preconverter
follower boost preconverter
Traditional Output
Ipk
IL
V (Follower Boost)
o
time
V
ac
Vin
Vin
Vin
Vout
Vin
IL
Load
IL
Figure 29. Follower Boost Characteristics
the power switch is off
Figure 30. Off–Time Duration Increase
the power switch is on
This technique aims at reducing the gap between the
output and the input voltages to minimize the boost
efficiency degradation.
Follower Boost Implementation
In the MC33260, the on–time is differently controlled
according to the feedback current level. Two areas can be
defined:
Follower Boost Benefits
The boost presents two phases:
• The on–time during which the power switch is on. The
• When the feedback current is higher than I
(refer
regL
inductor current grows up linearly according to a slope
to regulation section), the regulation block output
(V )ismodulatedtoforcetheoutputvoltagetoa
(V /L ), where V is the instantaneous input voltage
in
p
in
control
and L the inductor value.
p
desired value.
• The off–time during which the power switch is off.
• On the other hand, when the feedback current is lower
The inductor current decreases linearly according the
than I
, the regulation block output and therefore,
regL
slope (V – V )/L , where V is the output voltage.
o
in
p
o
the on–time are maximum. As explained in PWM
Latch Section, the on–time is then inversely
proportional to the output voltage square. The
Follower Boost is active in these conditions in which
the on–time is simply limited by the output voltage
level. Note: In this equation, the feedback pin voltage
This sequence that terminates when the current equals
zero, hasadurationthatisinverselyproportionaltothe
gap between the output and input voltages.
Consequently, the off–time duration becomes longer
in follower boost.
Consequently, for a given peak inductor current, the
longer the off time, the smaller power switch duty cycle and
thenitsconductiondissipation. Thisisthefirstbenefitofthis
technique: the MOSFET on–time losses are reduced.
The increase of the off time duration also results in a
switching frequency diminution (for a given inductor
value). Given that in practise, the boost inductor is selected
big enough to limit the switching frequency down to an
acceptablelevel, onecanimmediatelyseethesecondbenefit
of the follower boost: it allows the use of smaller, lighter and
cheaper inductors compared to traditional systems.
Finally, this technique utilization brings a drastic system
cost reduction by lowering the size and then the cost of both
the inductor and the power switch.
(V
) is neglected compared to the output voltage
pin1
(refer to the PWM Latch Section).
2
R
C
o
pin3
t
t
max
on
on
2
V
K
osc
o
where:
C
is the total oscillator capacitor (sum of the
pin3
internal and external capacitors – C + C ),
int
T
K
is the ratio (oscillator swing over oscillator gain),
osc
V is the output voltage,
o
R is the feedback resistor.
o
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14
MC33260
On the other hand, the boost topology has its own rule that
dictatestheon–timenecessarytodelivertherequiredpower:
Regulation Block is Active
V = V
V
o
o
pk
4
L
P
p
2
pk
in
(P )min
in
t
on
V
where:
P
in
V
is the peak ac line voltage,
pk
L is the inductor value,
p
in
(P )max
in
P
is the input power.
Combining the two equations, one can obtain the
Follower Boost equation:
non usable area
C
R
pin3
o
V
V
o
pk
2
K
L
p
P
osc
in
V
ac
Consequently, a linear dependency links the output
voltage to the ac line amplitude at a given input power.
V
acLL
V
ac
V
acHL
Figure 32. Follower Boost Output Voltage
The Regulation Block is Active
(V )max
ac
Mode Selection
The operation mode is simply selected by adjusting the
oscillator capacitor value. As shown in Figure 32, the output
voltagefirsthasanincreasinglinearcharacteristicversusthe
ac line magnitude and then is clamped down to the
regulation value. In the traditional mode, the linear area
must be rejected. This is achieved by dimensioning the
oscillator capacitor so that the boost can deliver the
maximum power while the output voltage equals its
regulation level and this, whatever the given input voltage.
Practically, that means that whatever the power and input
voltage conditions are, the follower boost would generate
output voltages values higher than the regulation level, if
there was no regulation block.
V
ac
Output Voltage
Input Power
P
in
(V )min
ac
V
o
2
= k/V
o
t
on
t
on–time
on
Figure 31. Follower Boost Characteristics
In other words, if (V )
level:
is the low output regulation
o regL
The behavior of the output voltage is depicted in Figures
31 and 32. In particular, Figure 31 illustrates how the output
voltage converges to a stable equilibrium level. First, at a
given ac line voltage, the on–time is dictated by the power
demand. Then, the follower boost characteristic makes
correspond one output voltage level to this on–time.
Combining these two laws, it appears that the power level
forces the output voltage.
C
C
R
o
T
L
int
P
V
V
o
regL
pk
2
K
max
osc
p
in
Consequently,
2
regL
4
K
L
P
max
V
o
osc
p
in
V
C
C
One can notice that the system is fully stable:
T
int
2
2
pk
R
o
• If an output voltage increase makes it move away from
its equilibrium value, the on–time will immediately
diminishaccording to the follower boost law. This will
result in a delivered power decrease. Consequently,
the supplied power being too low, the output voltage
will decrease back,
• In the same way, if the output voltage decreases, more
power will be transferred and then the output voltage
will increase back.
Using I
(regulation block current reference), this
regL
equation can be simplified as follows:
2
regL
4
K
L
P
max
I
osc
p
in
C
C
T
int
2
pk
V
In the Follower Boost case, the oscillator capacitor must
be chosen so that the wished characteristics are obtained.
Consequently, the simple choice of the oscillator
capacitor enables the mode selection.
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15
MC33260
Synchronization
Signal
Zero Current
Detection
2
s
Delay
2
s
2
s
2
s
2
s
V
control
Oscillator
Circuit
Output
205
A
I
cs
Inductor
Current
1
2
3
4
case no. 1: the turn on is delayed by the Zero Current Detection
cases no. 2 and no. 3: the turn on is delayed by the synchronization signal
case no. 4: the turn on is delayed by the minimum off–time (2 s)
Figure 33. Typical Waveforms
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16
MC33260
MAIN DESIGN EQUATIONS (Note 1)
rms Input Current (I
ac
)
η (preconverter efficiency) is generally in the
range of 90 – 95%.
P
o
V
I
ac
ac
Maximum Inductor Peak Current ((I )max):
pk
2
2
(P )max
o
(I )max is the maximum inductor current.
pk
(I )max
pk
V
acLL
Output Voltage Peak to Peak 100Hz (120Hz) Ripple ((∆Vo)pk–pk):
f
ac
is the ac line frequency (50 or 60Hz)
P
o
( V )
o
pk–pk
2
f
C
V
o
ac
o
V
Inductor Value (L ):
p
o
t is the maximum switching period.
(t=40µs) for universal mains operation and
(t=20µs) for narrow range are generally used.
2
2
t
V
V
acLL
acLL
2
L
p
V
V
(I )max
o
acLL
pk
Maximum Power MOSFET Conduction Losses ((p )max):
on
(Rds)on is the MOSFET drain source on–time
resistor.
1.2
V
acLL
1
(Rds)on (I ) max2
pk
1
In Follower Boost, the ratio (V
/V ) is
acLL
o
(P )max
on
3
V
higher. The on–time MOSFET losses are then
reduced
o
Maximum Average Diode Current (I ):
d
The Average Diode Current depends on the
power and on the output voltage.
(P ) max
o
(I )max
d
(V ) min
o
Current Sense Resistor Losses (pR ):
cs
This formula indicates the required dissipation
capability for R (current sense resistor).
cs
1
pR
cs
6
(Rds)on (I )2 max
pk
Over Current Protection Resistor (R
):
The overcurrent threshold is adjusted by R
OCP
OCP
R
(I )max
pk
0.205
at a given R
.
cs
can be a preconverter inrush resistor
cs
(k
)
R
R
cs
OCP
Oscillator External Capacitor Value (C ):
T
–Traditional Operation
2
K
L
(P )max I2
osc
C
p
in
regL
The Follower Boost characteristic is adjusted
C
C
V2
ac
T
int
by the C choice.
T
The Traditional Mode is also selected by C .
T
– Follower Boost:
C
is the oscillator pin internal capacitor.
int
C
R
o
T
int
V
V
o
pk
2
K
L
P
osc
V
p
in
Feedback Resistor (R ):
o
(V )
o reg
The output voltage regulation level is adjusted
by R .
V
pin1
o
200
(M
)
R
o
o
I
regH
Note 1. The preconverter design requires the following characteristics specification:
– (V ) : desired output voltage regulation level
o reg
– (∆V )
: admissible output peak to peak ripple voltage
o pk–pk
– P : desired output power
o
– V : ac rms operating line voltage
ac
acLL
– V
: minimum ac rms operating line voltage
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17
MC33260
L1 320
H
D5
MUR460E
1N4007
D1
R1
1 M
0.25 W
80 W Load
(SMPS, Lamp
Ballast,...)
D2
D4
Q1
MTP4N50E
+
C2
47
450 V
C1
330 nF
500 Vdc
90 to
EMI
D3
F
270 Vac
Filter
R2
1 M
0.25 W
R4
R3
15 k /0.25 W
1
/2 W
R5
22 /0.25 W
V
I
ref
I
I
ref
MC33260
o
ref
I
o
Feedback
Block
11 V/8.5 V
I
I
ref
–
o
REGULATOR
Enable
UVP, OVP
1
V
V
prot
CC
+
V
reg
Regulation
Block
1.5 V
8
V
control
V
reg
I
o
V
prot
(– – –)
C3
680 nF
I
o
2
300 k
I
I
I
uvp ovpL ovpH
ThStdwn
Drive
7
Output
Buffer
97%.I
ref
I
ref
PWM Comp
Gnd
6
Oscillator
+
–
R
S
Q
Q
2x|0x|0
I
PWM
Latch
osc–ch
I
ref
Current
Sense
Block
Output
I
(205 A)
–60 mV
ocp
CT
3
C4
330 pF
0
1
1
0
+
Synchro
5
15 pF
Synchronization
Block
–
LEB
Output
4
L1: Coilcraft N2881 – A (primary: 62 turns of # 22 AWG – Secondary: 5 turns of # 22 AWG Core: Coilcraft PT2510, EE 25
L1: Gap: 0.072″ total for a primary inductance (Lp) of 320 H)
Figure 34. 80 W Wide Mains Power Factor Corrector
POWER FACTOR CONTROLLER TEST DATA*
AC Line Input
DC Output
Current Harmonic Distortion (% I
fund
)
V
(V)
P
(W)
PF
(–)
I
V
(V)
∆V
(V)
I
P
o
(W)
η
(%)
rms
in
fund
o
o
o
(mA)
(mA)
THD
H2
H3
H5
H7
H9
90
88.2
86.3
85.2
87.0
84.7
85.3
84.0
0.991
0.996
0.995
0.994
0.982
0.975
0.967
990
782
642
480
385
359
330
8.1
7.0
0.07
0.05
0.03
0.16
0.5
5.9
2.7
1.5
4.0
8.4
9.0
11.0
4.3
5.7
6.8
6.5
7.8
7.8
7.0
1.5
1.1
1.1
3.1
5.3
7.4
9.0
1.7
0.8
1.5
4.0
1.9
3.8
4.0
181
222
265
360
379
384
392
31.2
26.4
20.8
16.0
14.0
14.0
13.2
440
360
300
225
210
210
205
79.6
79.9
79.5
81.0
79.6
80.6
80.4
90.2
92.6
93.3
93.1
94.4
94.5
95.7
110
135
180
220
240
260
8.2
9.5
15
16.5
18.8
0.7
0.7
*Measurements performed using Voltech PM1200 ac power analysis.
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18
MC33260
R
stup
r
D1...D4
+
15 V
C
pin8
V
CC
+
1
2
3
4
8
7
6
5
Figure 35. Circuit Supply Voltage
MC33260 V
CC
SUPPLY VOLTAGE
When the PFC preconverter is loaded by an SMPS, the
MC33260should preferably be supplied by the SMPS itself.
In this configuration, the SMPS starts first and the PFC gets
Insome applications, the arrangement shown in Figure 35
must be implemented to supply the circuit. A start–up
resistor is connected between the rectified voltage (or
active when the MC33260 V
supplied by the power
CC
one–half wave) to charge the MC33260 V
up to its
supply, exceeds the device start–up level. With this
configuration, the PFC preconverter doesn’t require any
auxiliary winding and finally a simple coil can be used.
CC
start–up threshold (11 V typically). The MC33260 turns on
andtheV capacitor(C )startstobechargedbythePFC
CC pin8
transformer auxiliary winding. A resistor, r (in the range of
22 Ω) and a 15 V zener should be added to protect the circuit
from excessive voltages.
PCB LAYOUT
The connections of the oscillator and V
should be as short as possible.
capacitors
control
Preconverter Output
+
+
+
V
CC
1
2
3
4
8
7
6
5
+
+
+
+
SMPS Driver
Figure 36. Preconverter loaded by a Flyback SMPS: MC33260 V
Supply
CC
http://onsemi.com
19
MC33260
PACKAGE DIMENSIONS
DIP–8
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
8
5
Y14.5M, 1982.
–B–
MILLIMETERS
DIM MIN MAX
INCHES
1
4
MIN
MAX
0.400
0.260
0.175
0.020
0.070
A
B
C
D
F
G
H
J
9.40
6.10
3.94
0.38
1.02
10.16 0.370
6.60 0.240
4.45 0.155
0.51 0.015
1.78 0.040
0.100 BSC
1.27 0.030
0.30 0.008
F
–A–
NOTE 2
2.54 BSC
L
0.76
0.20
2.92
0.050
0.012
0.135
K
L
3.43
0.115
0.300 BSC
7.62 BSC
C
M
N
–––
0.76
10
–––
10
0.040
1.01 0.030
J
–T–
SEATING
PLANE
STYLE 1:
PIN 1. AC IN
N
2. DC + IN
3. DC – IN
4. AC IN
M
D
K
5. GROUND
6. OUTPUT
7. AUXILIARY
G
H
M
M
M
0.13 (0.005)
T A
B
8. V
CC
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