AV16260DGG [NXP]
12-bit to 24-bit multiplexed D-type latches 3-State; 12位至24位多路D型锁存三态
| 型号： | AV16260DGG |
| 厂家： | 
NXP |
| 描述： | 12-bit to 24-bit multiplexed D-type latches 3-State |
| 文件： | 总14页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74ALVT16260
12-bit to 24-bit multiplexed D-type latches
(3-State)
Product specification
IC23 Data Handbook
1998 Jan 30
Philips
Semiconductors
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
FEATURES
DESCRIPTION
The 74ALVT16260 is a 12-bit to 24-bit multiplexed D-type latch used
in applications where two separate data paths must be multiplexed
onto, or demultiplexed from, a single data path. Typical applications
include multiplexing and/or demultiplexing of address and data
information in microprocessor or bus-interface applications. This
device is alto useful in memory-interleaving applications.
• ESD protection exceeds 2000V per Mil-Std-883C, Method 3015;
exceeds 200V using machine model
• Latch-up protection exceeds 500mA per JEDEC Standard
JESD-17.
• Distributed V and GND pin configuration minimizes high-speed
CC
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are
available for address and/or data transfer. The output enable (OE1B,
OE2B, and OEA) inputs control the bus transceiver functions. The
OE1B and OE2B control signals also allow bank control in the A to
B direction.
switching noise.
• Output capability (–32mA I , 64mA I ).
OH
OL
• Bus hold inputs eliminate the need for external pull-up resistors.
• 5V I/O compatible
Address and/or data information can be stored using the internal
storage latches. The latch enable (LE1B, LE2B, LEA1B, and
LEA2B) inputs are used to control data storage. When the latch
enable input is high, the latch is transparent. When the latch enable
input goes low, the data present at the inputs is latched and remains
latched until the latch enable input is returned high.
• Live insertion/extraction permitted
• Power-up 3-State
• Power-up Reset
To ensure the high-impedance state during power-up or
power-down, OE should be tied to V through a pull-up resistor;
CC
the minimum value of the resistor is determined by the current
sinking capability of the driver.
The 74ALVT16260 is available in a 56-pin Shrink Small Outline
Package (SSOP) and 56-pin Thin Shrink Small Outline Package
(TSSOP).
QUICK REFERENCE DATA
TYPICAL
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
UNIT
T
amb
2.5V
3.5
3.3
4
3.3V
2.8
2.6
4
t
t
Propagation delay
PLH
C = 50 pF
L
ns
nAx to nBx nBx to nAx
Input capacitance
PHL
C
V = 0 V or V
I CC
pF
pF
µA
IN
C
Output capacitance
Total supply current
V
= 0 V or 5.0 V
9
9
OUT
CCZ
I/O
I
Outputs disabled
100
80
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
AV16260 DL
DWG NUMBER
SOT371-1
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
–40°C to +85°C
–40°C to +85°C
74ALVT16260 DL
74ALVT16260 DGG
AV16260 DGG
SOT364-1
2
1998 Jan 30
853-2046-18918
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
Data inputs/outputs (A)
8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21
An
23, 24, 26, 31, 33, 34, 36, 37, 38, 40, 41, 42
1Bn
Data inputs/outputs (B1)
Data inputs/outputs (B2)
6, 5, 3, 54, 52, 51, 49, 48, 47, 45, 44, 43
2Bn
OEA, OE1B, OE2B
LE1B, LE2B, LEA1B, LEA2B
SEL
1, 29, 56
2, 27, 30, 55
Output enable input (active low)
Latch enable inputs
28
B1/B2 input select input
Ground (0V)
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
GND
V
CC
Positive supply voltage
PIN CONFIGURATION
FUNCTION TABLES
B to A (OEB = H)
OEA
1
56 OE2B
INPUTS
SEL LE1B LE2B
OUTPUT
A
LE1B
2B3
2
3
4
5
6
7
8
9
55 LEA2B
54 2B4
53 GND
52 2B5
51 2B6
1B
2B
OEA
H
L
X
X
X
H
L
H
H
H
L
H
H
L
X
X
X
H
H
L
L
L
L
L
L
L
H
H
L
GND
2B2
X
X
X
X
X
A0
H
2B1
X
X
X
X
V
50 V
CC
CC
L
L
A1
49 2B7
48 2B8
47 2B9
46 GND
45 2B10
44 2B11
43 2B12
42 1B12
41 1B11
40 1B10
39 GND
38 1B9
37 1B8
36 1B7
X
X
L
A0
Z
A2
X
X
A3 10
A to B (OEA = H)
GND 11
A4 12
INPUTS
LEA1B LEA2B OE1B OE2B
OUTPUT
A5 13
A6 14
A7 15
A
H
L
1B
2B
H
H
H
H
H
L
H
H
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
H
L
L
H
L
L
A8 16
A9 17
GND 18
A10 19
A11 20
A12 21
H
L
H
2B0
2B0
H
L
L
H
L
H
H
L
1B0
1B0
1B0
Z
L
L
X
X
X
X
X
L
2B0
Z
X
X
X
X
X
X
X
X
V
22
35 V
CC
CC
Active
Z
Z
1B1 23
1B2 24
GND 25
1B3 26
LE2B 27
SEL 28
34 1B6
33 1B5
Active
Active
32 GND
31 1B4
Active
30 LEA1B
29 OE1B
SA00435
3
1998 Jan 30
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
LOGIC DIAGRAM (POSITIVE LOGIC)
2
LE1B
27
LE2B
30
LEA1B
55
LEA2B
56
OE2B
29
OE1B
1
OEA
28
SEL
C1
G1
8
23
A1
1
1
1D
1B1
C1
1D
6
2B1
C1
1D
C1
1D
TO 11 OTHER CHANNELS
SA00436
4
1998 Jan 30
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
V
V
CC
I
IK
DC supply voltage
–0.5 to +4.6
–50
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–0.5 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
OUT
DC output voltage
Output in Off or High state
Output in Low state
–0.5 to +7.0
128
I
DC output current
mA
OUT
Output in High state
–64
T
stg
Storage temperature range
–65 to +150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
2.5V RANGE LIMITS 3.3V RANGE LIMITS
SYMBOL
PARAMETER
UNIT
MIN
2.3
0
MAX
2.7
MIN
3.0
0
MAX
3.6
V
CC
DC supply voltage
Input voltage
V
V
V
I
5.5
5.5
V
High-level input voltage
Input voltage
1.7
2.0
V
IH
V
0.7
–8
8
0.8
–32
32
V
IL
I
High-level output current
Low-level output current
mA
OH
I
OL
mA
Low-level output current; current duty cycle ≤ 50%; f ≥ 1kHz
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
24
10
+85
64
∆t/∆v
10
ns/V
T
amb
–40
–40
+85
°C
5
1998 Jan 30
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
DC ELECTRICAL CHARACTERISTICS (3.3V "0.3V RANGE)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
TYP
–0.85
MAX
V
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3.0V; I = –18mA
*1.2
V
V
IK
IK
= 3.0 to 3.6V; I = –100µA
V
0.2
V
CC
OH
CC–
V
OH
High-level output voltage
= 3.0V; I = –32mA
2.0
2.3
0.07
0.25
0.3
OH
= 3.0V; I = 100µA
0.2
0.4
OL
= 3.0V; I = 16mA
OL
V
OL
Low–level output voltage
V
= 3.0V; I = 32mA
0.5
OL
= 3.0V; I = 64mA
0.4
0.55
OL
6
V
Power-up output low voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3.6V; I = 1mA; V = V or GND
0.55
±1
V
RST
O
I
CC
= 3.6V; V = V or GND
Control pins
0.1
0.1
I
CC
= 0 or 3.6V; V = 5.5V
10
I
I
I
Input leakage current
µA
= 3.6V; V = V
0.1
1
I
CC
4
Data pins
= 3.6V; V = 0V
0.1
-5
I
I
Off current
= 0V; V or V = 0 to 4.5V
0.1
±100
µA
µA
OFF
I
O
= 3V; V = 0.8V
75
130
–140
I
Bus Hold current
= 3V; V = 2.0V
–75
I
I
HOLD
7
Data inputs
= 0V to 3.6V; V = 3.6V
±500
CC
Current into an output in the
I
V
= 5.5V; V = 3.0V
10
1
125
µA
µA
EX
O
CC
High state when V > V
O
CC
Power up/down 3-State output
V
CC
≤ 1.2V; V = 0.5V to V ; V = GND or V
O CC I CC
I
±100
PU/PD
3
current
OE/OE = Don’t care
I
3-State output High current
3-State output Low current
V
V
V
V
V
V
= 3.6V; V = 3.0V; V = V or V
0.5
0.5
5
µA
µA
OZH
CC
CC
CC
CC
CC
CC
O
I
IL
IH
IH
I
= 3.6V; V = 0.5V; V = V or V
*5
0.1
6
OZL
O
I
IL
I
= 3.6V; Outputs High, V = GND or V I 0
CC, O =
0.04
3.7
CCH
I
I
Quiescent supply current
= 3.6V; Outputs Low, V = GND or V I 0
CC, O =
mA
mA
CCL
I
5
I
= 3.6V; Outputs Disabled; V = GND or V
I = 0
CC, O
0.04
0.1
CCZ
I
Additional supply current per
= 3V to 3.6V; One input at V –0.6V,
CC
∆I
0.04
0.4
CC
2
input pin
Other inputs at V or GND
CC
NOTES:
1. All typical values are at V = 3.3V and T
= 25°C.
amb
CC
2. This is the increase in supply current for each input at the specified voltage level other than V or GND
CC
3. This parameter is valid for any V between 0V and 1.2V with a transition time of up to 10msec. From V = 1.2V to V = 3.3V ± 0.2V a
CC
CC
CC
transition time of 100µsec is permitted. This parameter is valid for T
= 25°C only.
amb
4. Unused pins at V or GND.
CC
5. I
is measured with outputs pulled up to V or pulled down to ground.
CCZ
CC
6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
6
1998 Jan 30
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
AC ELECTRICAL CHARACTERISTICS (3.3V ± 0.3V RANGE)
GND = 0V; t = t = 2.5ns; C = 50pF; R = 500Ω
R
F
L
L
T
= –40°C to +85°C
amb
V
PARAMETER
= +3.3V ± 0.3V
CC
SYMBOL
UNIT
FROM (INPUT)
TO (OUTPUT)
MIN
1
TYP
2.8
2.6
2.9
3.1
2.3
2.4
2.4
2.4
2.3
2.3
4.4
3.1
MAX
4.8
4.6
4.6
4.7
3.4
3.8
3.6
3.6
4.2
4.0
6.0
5.0
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PLH
A or B
B or A
1
PHL
PLH
PHL
1.1
1.1
1.3
1.1
1.5
1.6
1
LE
A or B
SEL (B1)
SEL (B2)
SEL (B1)
SEL (B2)
A
A
A
A
t
t
PLH
PHL
t
t
t
t
PZH
PZL
PHZ
PLZ
OE
OE
A or B
A or B
1.6
2.2
1.3
AC SETUP CHARACTERISTICS (3.3V ± 0.3V RANGE)
GND = 0V; t = t = 2.5ns; C = 50pF; R = 500Ω
R
F
L
L
T
= –40°C to +85°C
amb
V
= +3.3V ± 0.3V
CC
SYMBOL
PARAMETER
UNIT
MIN
3.3
1
MAX
t
t
t
Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high
Setup time, data before LE1B, LE2B, LEA1B, or LEA2B↓
Hold time, data after LE1B, LE2B, LEA1B, or LEA2B↓
ns
ns
ns
w
su
h
1
7
1998 Jan 30
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
DC ELECTRICAL CHARACTERISTICS (2.5V "0.2V RANGE)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
UNIT
1
MIN
TYP
–0.85
MAX
V
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.3V; I = –18mA
–1.2
V
V
IK
IK
= 2.3 to 3.6V; I = –100µA
V
–0.2
V
CC
OH
CC
V
OH
High-level output voltage
= 2.3V; I = –8mA
1.8
2.1
0.07
0.3
OH
= 2.3V; I = 100µA
0.2
0.5
OL
V
OL
Low-level output voltage
= 2.3V; I = 24mA
OL
7
V
Power-up output low voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.7V; I = 1mA; V = V or GND
0.55
±1
V
RST
O
I
CC
= 2.7V; V = V
or GND
CC
Control pins
0.1
0.1
0.1
0.1
0.1
90
I
= 0 or 2.7V; V = 5.5V
10
I
I
I
Input leakage current
µA
= 2.7V; V = V
1
I
CC
4
Data pins
= 2.7V; V = 0
-5
I
I
Off current
= 0V; V or V = 0 to 4.5V
"100
µA
µA
OFF
I
O
Bus Hold current
= 2.3V; V = 0.7V
I
I
HOLD
6
Data inputs
= 2.3V; V = 1.7V
–10
I
Current into an output in the
I
V
= 5.5V; V = 2.3V
10
1
125
100
µA
µA
EX
O
CC
High state when V > V
O
CC
Power up/down 3-State output
V
CC
≤ 1.2V; V = 0.5V to V ; V = GND or V
;
CC
O
CC
I
I
PU/PD
3
current
OE/OE = Don’t care
I
3-State output High current
3-State output Low current
V
V
V
V
V
V
= 2.7V; V = 2.3V; V = V or V
0.5
0.5
5
µA
µA
OZH
CC
CC
CC
CC
CC
CC
O
I
IL
IH
IH
I
= 2.7V; V = 0.5V; V = V or V
–5
OZL
O
I
IL
I
= 2.7V; Outputs High, V = GND or V I 0
CC, O =
0.04
2.7
0.1
4.5
0.1
CCH
I
I
Quiescent supply current
= 2.7V; Outputs Low, V = GND or V I 0
CC, O =
mA
mA
CCL
CCZ
I
5
I
= 2.7V; Outputs Disabled; V = GND or V
I 0
CC, O =
0.04
I
Additional supply current per
= 2.3V to 2.7V; One input at V –0.6V,
CC
∆I
0.04
0.4
CC
2
input pin
Other inputs at V or GND
CC
NOTES:
1. All typical values are at V = 2.5V and T
= 25°C.
amb
CC
2. This is the increase in supply current for each input at the specified voltage level other than V or GND
CC
3. This parameter is valid for any V between 0V and 1.2V with a transition time of up to 10msec. From V = 1.2V to V = 2.5V ± 0.3V a
CC
CC
CC
transition time of 100µsec is permitted. This parameter is valid for T
= 25°C only.
amb
4. Unused pins at V or GND.
CC
5. I
is measured with outputs pulled up to V or pulled down to ground.
CCZ
CC
6. Not guaranteed.
7. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
8
1998 Jan 30
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
AC ELECTRICAL CHARACTERISTICS (2.5V ± 0.2V RANGE)
GND = 0V; t = t = 2.5ns; C = 50pF; R = 500Ω
R
F
L
L
T
= –40°C to +85°C
amb
V
PARAMETER
= +2.5V ± 0.2V
CC
SYMBOL
UNIT
FROM (INPUT)
TO (OUTPUT)
MIN
1
TYP
3.5
3.3
3.9
4.2
2.9
3.3
3.0
3.2
3.1
2.0
4.0
2.0
MAX
5.3
5.4
6.0
6.2
4.5
4.8
4.5
4.6
5.0
3.0
6.6
3.4
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PLH
A or B
B or A
1
PHL
PLH
PHL
1.1
1.1
1.3
1.1
1.5
1.6
1
LE
A or B
SEL (B1)
SEL (B2)
SEL (B1)
SEL (B2)
A
A
A
A
t
t
PLH
PHL
t
t
t
t
PZH
PZL
PHZ
PLZ
OE
OE
A or B
A or B
1.6
2.2
1.3
AC SETUP CHARACTERISTICS (2.5V ± 0.2V RANGE)
GND = 0V; t = t = 2.5ns; C = 50pF; R = 500Ω
R
F
L
L
T
= –40°C to +85°C
amb
V
= +2.5V ± 0.2V
CC
SYMBOL
PARAMETER
UNIT
MIN
3.3
1
MAX
t
t
t
Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high
Setup time, data before LE1B, LE2B, LEA1B, or LEA2B↓
Hold time, data after LE1B, LE2B, LEA1B, or LEA2B↓
ns
ns
ns
w
su
h
1
9
1998 Jan 30
Philips Semiconductors
Product specification
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
74ALVT16260
AC WAVEFORMS
V
M
= 1.5V for all waveforms
The outputs are measured one at a time with one transition per measurement.
3V
V
TIMING INPUT
DATA INPUT
M
t
w
0V
3V
3V
0V
t
su
t
h
V
V
M
INPUT
M
V
V
M
M
0V
SA00437
SA00439
Figure 1. Pulse duration
Figure 3. Setup and hold times
3V
0V
3V
OUTPUT
CONTROL
V
V
V
V
M
INPUT
M
M
M
0V
t
t
PLZ
t
t
PZL
PLH
PHL
V
V
V
V
3.5V
OH
OL
OH
OL
OUTPUT
WAVEFORM 1
S1 AT 7V
V
V
V
V
V
M
OUTPUT
OUTPUT
M
M
M
M
V
V
+ 0.3V
– 0.3V
OL
V
V
OL
t
t
PHZ
t
t
PZH
PHL
PLH
OH
OUTPUT
WAVEFORM 2
S1 AT OPEN
V
M
OH
≈0V
SA00438
SA00440
All input pulses are supplied by generators having the following
characteristics: PRR ≤ 10MHz, Z = 50Ω, t ≤ 2.5ns, t ≤ 2.5ns.
Waveform 1 is for an output with internal conditions such that the
output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the
output is high except when disabled by the output control.
O
r
f
Figure 2. Propagation delay times;
inverting and non-inverting outputs
Figure 4. Enable and disable times;
low- and high-level enabling
TEST LOAD CIRCUIT
7V
S1
OPEN
GND
500Ω
FROM OUTPUT UNDER TEST
TEST
/t
S1
Open
7V
t
PLH PHL
C
= 50pF
500Ω
L
t
/t
PLZ PZL
(INCLUDES PROBE AND
JIG CAPACITANCE)
t
/t
Open
PHZ PZH
Load Circuit for Outputs
SA00441
Figure 5. Test load circuit
10
1998 Jan 30
Philips Semiconductors
Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
74ALVT16260
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
11
1988 Jan 30
Philips Semiconductors
Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
74ALVT16260
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
12
1988 Jan 30
Philips Semiconductors
Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
74ALVT16260
NOTES
13
1988 Jan 30
Philips Semiconductors
Product specification
12-bit to 24-bit multiplexed D-type latches (3-State)
74ALVT16260
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 05-96
9397-750-03337
Document order number:
Philips
Semiconductors
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